RISC-V: Add wrapper for emit vec_extract[NFC]

Add wrapper for vec_extract since my following patch will need to call it.
gcc/ChangeLog:

	* config/riscv/riscv-protos.h (emit_vec_extract): New function.
	* config/riscv/riscv-v.cc (emit_vec_extract): Ditto.
	* config/riscv/riscv.cc (riscv_legitimize_move): Refine codes.

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 52097fe48cfec8f378c253331cd53a83bf9328d4..c74c2e94a4fb92698a7eaaf444bf7a09ba4a1b7d 100644 (file)
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -558,6 +558,7 @@ void expand_cond_binop (unsigned, rtx *);
 void expand_cond_ternop (unsigned, rtx *);
 void expand_popcount (rtx *);
 void expand_rawmemchr (machine_mode, rtx, rtx, rtx);
+void emit_vec_extract (rtx, rtx, poly_int64);
 
 /* Rounding mode bitfield for fixed point VXRM.  */
 enum fixed_point_rounding_mode

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 24b09c0dd2d5753559d98aa1d4a7fd90ff562263..72b96d8339d624610d18e003ea14d5b49fdde46f 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -4636,4 +4636,26 @@ can_be_broadcasted_p (rtx op)
   return can_create_pseudo_p () && nonmemory_operand (op, mode);
 }
 
+/* Helper function to emit vec_extract_optab.  */
+void
+emit_vec_extract (rtx target, rtx src, poly_int64 index)
+{
+  machine_mode vmode = GET_MODE (src);
+  machine_mode smode = GET_MODE (target);
+  class expand_operand ops[3];
+  enum insn_code icode
+    = convert_optab_handler (vec_extract_optab, vmode, smode);
+  gcc_assert (icode != CODE_FOR_nothing);
+  create_output_operand (&ops[0], target, smode);
+  ops[0].target = 1;
+  create_input_operand (&ops[1], src, vmode);
+  if (index.is_constant ())
+    create_integer_operand (&ops[2], index);
+  else
+    create_input_operand (&ops[2], gen_int_mode (index, Pmode), Pmode);
+  expand_insn (icode, 3, ops);
+  if (ops[0].value != target)
+    emit_move_insn (target, ops[0].value);
+}
+
 } // namespace riscv_vector

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d0efb939bf24fe70bf5475e9e0b672086292f302..425463ebb1852fb1129350eac142577e6412a59d 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2616,14 +2616,10 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
          nunits = nunits * 2;
        }
       vmode = riscv_vector::get_vector_mode (smode, nunits).require ();
-      enum insn_code icode
-       = convert_optab_handler (vec_extract_optab, vmode, smode);
-      gcc_assert (icode != CODE_FOR_nothing);
       rtx v = gen_lowpart (vmode, SUBREG_REG (src));
 
       for (unsigned int i = 0; i < num; i++)
        {
-         class expand_operand ops[3];
          rtx result;
          if (num == 1)
            result = dest;
@@ -2631,13 +2627,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
            result = gen_lowpart (smode, dest);
          else
            result = gen_reg_rtx (smode);
-         create_output_operand (&ops[0], result, smode);
-         ops[0].target = 1;
-         create_input_operand (&ops[1], v, vmode);
-         create_integer_operand (&ops[2], index + i);
-         expand_insn (icode, 3, ops);
-         if (ops[0].value != result)
-           emit_move_insn (result, ops[0].value);
+         riscv_vector::emit_vec_extract (result, v, index + i);
 
          if (i == 1)
            {