iommu/arm-smmu: Re-enable context caching in smmu reset operation

Default MMU-500 reset operation disables context caching in prefetch
buffer. It is however expected for context banks using the ACTLR
register to retain their prefetch value during reset and runtime
suspend.

Add config 'ARM_SMMU_MMU_500_CPRE_ERRATA' to gate this errata workaround
in default MMU-500 reset operation which defaults to 'Y' and provide
option to disable workaround for context caching in prefetch buffer as
and when needed.

Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Link: https://lore.kernel.org/r/20241212151402.159102-2-quic_bibekkum@quicinc.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index b42fea07c5cec8af004ffdce00ed9523ebd79bb8..f074f6219f5c337d3fab74fa68211b84247f7952 100644 (file)
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -198,7 +198,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |
 +----------------+-----------------+-----------------+-----------------------------+
-| ARM            | MMU-500         | #841119,826419  | N/A                         |
+| ARM            | MMU-500         | #841119,826419  | ARM_SMMU_MMU_500_CPRE_ERRATA|
+|                |                 | #562869,1047329 |                             |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | MMU-600         | #1076982,1209401| N/A                         |
 +----------------+-----------------+-----------------+-----------------------------+

diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 47c46e4b739ef32ff6aea519c6024a765956f002..ec1b5e32b9725bc1104d10e5d7a32af7b211b50a 100644 (file)
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -367,6 +367,18 @@ config ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT
          'arm-smmu.disable_bypass' will continue to override this
          config.
 
+config ARM_SMMU_MMU_500_CPRE_ERRATA
+       bool "Enable errata workaround for CPRE in SMMU reset path"
+       depends on ARM_SMMU
+       default y
+       help
+         Say Y here (by default) to apply workaround to disable
+         MMU-500's next-page prefetcher for sake of 4 known errata.
+
+         Say N here only when it is sure that any errata related to
+         prefetch enablement are not applicable on the platform.
+         Refer silicon-errata.rst for info on errata IDs.
+
 config ARM_SMMU_QCOM
        def_tristate y
        depends on ARM_SMMU && ARCH_QCOM

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
index 99030e6b16e7aaf752b19fb0bc5cf3d01ac75248..db9b9a8e139c8788122ebaca3505962df6a10d59 100644 (file)
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
@@ -110,7 +110,6 @@ static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smm
 int arm_mmu500_reset(struct arm_smmu_device *smmu)
 {
        u32 reg, major;
-       int i;
        /*
         * On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before
         * writes to the context bank ACTLRs will stick. And we just hope that
@@ -128,11 +127,12 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu)
        reg |= ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN;
        arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg);
 
+#ifdef CONFIG_ARM_SMMU_MMU_500_CPRE_ERRATA
        /*
         * Disable MMU-500's not-particularly-beneficial next-page
         * prefetcher for the sake of at least 5 known errata.
         */
-       for (i = 0; i < smmu->num_context_banks; ++i) {
+       for (int i = 0; i < smmu->num_context_banks; ++i) {
                reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
                reg &= ~ARM_MMU500_ACTLR_CPRE;
                arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
@@ -140,6 +140,7 @@ int arm_mmu500_reset(struct arm_smmu_device *smmu)
                if (reg & ARM_MMU500_ACTLR_CPRE)
                        dev_warn_once(smmu->dev, "Failed to disable prefetcher for errata workarounds, check SACR.CACHE_LOCK\n");
        }
+#endif
 
        return 0;
 }