drm/msm/dpu: don't overwrite CTL_MERGE_3D_ACTIVE register

In case of complex pipelines (e.g. the forthcoming quad-pipe) the DPU
might use more that one MERGE_3D block for a single output.  Follow the
pattern and extend the CTL_MERGE_3D_ACTIVE active register instead of
simply writing new value there. Currently at most one MERGE_3D block is
being used, so this has no impact on existing targets.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/641580/
Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-1-5d20655f10ca@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 411a7cf088eb72f856940c09b0af9e108ccade4b..cef3bfaa4af82ebc55fb8cf76adef3075c7d73e3 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -563,6 +563,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
        u32 wb_active = 0;
        u32 cwb_active = 0;
        u32 mode_sel = 0;
+       u32 merge_3d_active = 0;
 
        /* CTL_TOP[31:28] carries group_id to collate CTL paths
         * per VM. Explicitly disable it until VM support is
@@ -578,6 +579,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
        wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE);
        cwb_active = DPU_REG_READ(c, CTL_CWB_ACTIVE);
        dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE);
+       merge_3d_active = DPU_REG_READ(c, CTL_MERGE_3D_ACTIVE);
 
        if (cfg->intf)
                intf_active |= BIT(cfg->intf - INTF_0);
@@ -591,15 +593,15 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
        if (cfg->dsc)
                dsc_active |= cfg->dsc;
 
+       if (cfg->merge_3d)
+               merge_3d_active |= BIT(cfg->merge_3d - MERGE_3D_0);
+
        DPU_REG_WRITE(c, CTL_TOP, mode_sel);
        DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
        DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
        DPU_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
        DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
-
-       if (cfg->merge_3d)
-               DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
-                             BIT(cfg->merge_3d - MERGE_3D_0));
+       DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
 
        if (cfg->cdm)
                DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm);