MIPS/opcodes: Rename the AL membership shorthand to ALX

Make room for AL as a shorthand for INSN2_ALIAS with the regular MIPS
opcode table, just as with the MIPS16 opcode table.  No functional
change.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 734a02752825cf2c3a05b5a1d3375ef54ce861f6..56b09e8430264181b49caaead49b17ec3fb2f18b 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -316,7 +316,7 @@ decode_mips_operand (const char *p)
 /* Emotion Engine MIPS r5900. */
 #define EE      INSN_5900
 #define M1     INSN_10000
-#define AL     INSN_ALLEGREX
+#define ALX    INSN_ALLEGREX
 #define SB1     INSN_SB1
 #define N411   INSN_4111
 #define N412   INSN_4120
@@ -342,7 +342,7 @@ decode_mips_operand (const char *p)
 #define G3      EE
 
 /* CPU without 64 bit FPU support (single float only). */
-#define SF      (AL             \
+#define SF      (ALX            \
                  |EE            \
                  )
 
@@ -973,8 +973,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"flushid",            "",             0xbc030000, 0xffffffff, 0,                      0,              L1,             0,      0 },
 {"wb",                 "o(b)",         0xbc040000, 0xfc1f0000, RD_2|SM,                0,              L1,             0,      0 },
 {"cache",              "k,+j(b)",      0x7c000025, 0xfc00007f, RD_3,                   0,              I37,            0,      0 },
-{"cache",              "k,o(b)",       0xbc000000, 0xfc000000, RD_3,                   0,              I3_32|T3|AL,    0,      I37 },
-{"cache",              "k,A(b)",       0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3_32|T3|AL,    0,      0 },
+{"cache",              "k,o(b)",       0xbc000000, 0xfc000000, RD_3,                   0,              I3_32|T3|ALX,   0,      I37 },
+{"cache",              "k,A(b)",       0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3_32|T3|ALX,   0,      0 },
 {"ceil.l.d",           "D,S",          0x4620000a, 0xffff003f, WR_1|RD_2|FP_D,         0,              I3_33,          0,      0 },
 {"ceil.l.s",           "D,S",          0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I3_33,          0,      0 },
 {"ceil.w.d",           "D,S",          0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I2,             0,      SF },
@@ -990,10 +990,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cins32",             "t,r,+p,+s",    0x70000033, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"cins",               "t,r,+P,+S",    0x70000033, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 }, /* cins32 */
 {"cins",               "t,r,+p,+S",    0x70000032, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
-{"clo",                        "d,s",          0x00000017, 0xfc1f07ff, WR_1|RD_2,              0,              AL,             0,      0 },
+{"clo",                        "d,s",          0x00000017, 0xfc1f07ff, WR_1|RD_2,              0,              ALX,            0,      0 },
 {"clo",                        "d,s",          0x00000051, 0xfc1f07ff, WR_1|RD_2,              0,              I37,            0,      0 },
 {"clo",                        "U,s",          0x70000021, 0xfc0007ff, WR_1|RD_2,              0,              I32|N55,        0,      I37 },
-{"clz",                        "d,s",          0x00000016, 0xfc1f07ff, WR_1|RD_2,              0,              AL,             0,      0 },
+{"clz",                        "d,s",          0x00000016, 0xfc1f07ff, WR_1|RD_2,              0,              ALX,            0,      0 },
 {"clz",                        "d,s",          0x00000050, 0xfc1f07ff, WR_1|RD_2,              0,              I37,            0,      0 },
 {"clz",                        "U,s",          0x70000020, 0xfc0007ff, WR_1|RD_2,              0,              I32|N55,        0,      I37 },
 /* ctc0 is at the bottom of the table.  */
@@ -1029,7 +1029,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"daddu",              "d,v,t",        0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"daddu",              "t,r,I",        0,    (int) M_DADDU_I,  INSN_MACRO,             0,              I3,             0,      0 },
 {"daddwc",             "d,s,t",        0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0,          XLR,            0,      0 },
-{"dbreak",             "",             0x7000003f, 0xffffffff, 0,                      0,              N5|AL,          0,      0 },
+{"dbreak",             "",             0x7000003f, 0xffffffff, 0,                      0,              N5|ALX,         0,      0 },
 {"dclo",               "d,s",          0x00000053, 0xfc1f07ff, WR_1|RD_2,              0,              I69,            0,      0 },
 {"dclo",               "U,s",          0x70000025, 0xfc0007ff, WR_1|RD_2,      0,              I64|N55,        0,      I69 },
 {"dclz",               "d,s",          0x00000052, 0xfc1f07ff, WR_1|RD_2,              0,              I69,            0,      0 },
@@ -1139,7 +1139,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dremu",              "z,s,t",        0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I3,             0,      M32|I69 },
 {"dremu",              "d,v,t",        0,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3,             0,      M32|I69 },
 {"dremu",              "d,v,I",        0,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3,             0,      M32|I69 },
-{"dret",               "",             0x7000003e, 0xffffffff, 0,                      0,              N5|AL,          0,      0 },
+{"dret",               "",             0x7000003e, 0xffffffff, 0,                      0,              N5|ALX,         0,      0 },
 {"drol",               "d,v,t",        0,    (int) M_DROL,     INSN_MACRO,             0,              I3,             0,      0 },
 {"drol",               "d,v,I",        0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3,             0,      0 },
 {"dror",               "d,v,t",        0,    (int) M_DROR,     INSN_MACRO,             0,              I3,             0,      0 },
@@ -1191,13 +1191,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ei",                 "t",            0x41606020, 0xffe0ffff, WR_1|WR_C0,             0,              I33,            0,      0 },
 {"emt",                        "",             0x41600be1, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
 {"emt",                        "t",            0x41600be1, 0xffe0ffff, WR_1|TRAP,              0,              0,              MT32,   0 },
-{"eret",               "",             0x42000018, 0xffffffff, NODS,                   0,              I3_32|AL,       0,      0 },
+{"eret",               "",             0x42000018, 0xffffffff, NODS,                   0,              I3_32|ALX,      0,      0 },
 {"eretnc",             "",             0x42000058, 0xffffffff, NODS,                   0,              I36,            0,      0 },
 {"evpe",               "",             0x41600021, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
 {"evpe",               "t",            0x41600021, 0xffe0ffff, WR_1|TRAP,              0,              0,              MT32,   0 },
 {"evp",                        "",             0x41600004, 0xffffffff, TRAP,                   0,              I37,            0,      0 },
 {"evp",                        "t",            0x41600004, 0xffe0ffff, WR_1|TRAP,              0,              I37,            0,      0 },
-{"ext",                        "t,r,+A,+C",    0x7c000000, 0xfc00003f, WR_1|RD_2,              0,              I33|AL,         0,      0 },
+{"ext",                        "t,r,+A,+C",    0x7c000000, 0xfc00003f, WR_1|RD_2,              0,              I33|ALX,                0,      0 },
 {"exts32",             "t,r,+p,+s",    0x7000003b, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"exts",               "t,r,+P,+S",    0x7000003b, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 }, /* exts32 */
 {"exts",               "t,r,+p,+S",    0x7000003a, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
@@ -1208,7 +1208,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"hibernate",          "",             0x42000023, 0xffffffff, 0,                      0,              V1,             0,      0 },
 {"hypcall",            "",             0x42000028, 0xffffffff, TRAP,                   0,              0,              IVIRT,  0 },
 {"hypcall",            "+J",           0x42000028, 0xffe007ff, TRAP,                   0,              0,              IVIRT,  0 },
-{"ins",                        "t,r,+A,+B",    0x7c000004, 0xfc00003f, WR_1|RD_2,              0,              I33|AL,         0,      0 },
+{"ins",                        "t,r,+A,+B",    0x7c000004, 0xfc00003f, WR_1|RD_2,              0,              I33|ALX,                0,      0 },
 {"iret",               "",             0x42000038, 0xffffffff, NODS,                   0,              0,              MC,     0 },
 {"jr",                 "s",            0x00000009, 0xfc1fffff, RD_1|UBD,               INSN2_ALIAS,    I37,            0,      0 }, /* jalr $0 */
 {"jr",                 "s",            0x00000008, 0xfc1fffff, RD_1|UBD,               0,              I1,             0,      I37 },
@@ -1281,10 +1281,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"l.d",                        "T,o(b)",       0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D,     0,              I2,             0,      SF }, /* ldc1 */
 {"l.d",                        "T,A(b)",       0,    (int) M_L_DAB,    INSN_MACRO,             INSN2_M_FP_D,   I1,             0,      0 },
 {"ldc2",               "E,+:(d)",      0x49c00000, 0xffe00000, RD_3|WR_C2|CLD,         0,              I37,            0,      0 },
-{"ldc2",               "E,o(b)",       0xd8000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I2,             0,      N54|IOCT|IOCTP|IOCT2|EE|AL|I37 },
-{"ldc2",               "E,A(b)",       0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2,             0,      N54|IOCT|IOCTP|IOCT2|EE|AL },
-{"ldc3",               "E,o(b)",       0xdc000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I2,             0,      I3_32|EE|AL },
-{"ldc3",               "E,A(b)",       0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2,             0,      I3_32|EE|AL },
+{"ldc2",               "E,o(b)",       0xd8000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I2,             0,      N54|IOCT|IOCTP|IOCT2|EE|ALX|I37 },
+{"ldc2",               "E,A(b)",       0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2,             0,      N54|IOCT|IOCTP|IOCT2|EE|ALX },
+{"ldc3",               "E,o(b)",       0xdc000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I2,             0,      I3_32|EE|ALX },
+{"ldc3",               "E,A(b)",       0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2,             0,      I3_32|EE|ALX },
 {"ldl",                        "t,o(b)",       0x68000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      I69 },
 {"ldl",                        "t,A(b)",       0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3,             0,      I69 },
 {"ldr",                        "t,o(b)",       0x6c000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      I69 },
@@ -1330,8 +1330,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lwc2",               "E,+:(d)",      0x49400000, 0xffe00000, RD_3|WR_C2|CLD,         0,              I37,            0,      0 },
 {"lwc2",               "E,o(b)",       0xc8000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      N54|IOCT|IOCTP|IOCT2|EE|I37 },
 {"lwc2",               "E,A(b)",       0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1,             0,      N54|IOCT|IOCTP|IOCT2|EE },
-{"lwc3",               "E,o(b)",       0xcc000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      I3_32|EE|AL },
-{"lwc3",               "E,A(b)",       0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1,             0,      I3_32|EE|AL },
+{"lwc3",               "E,o(b)",       0xcc000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      I3_32|EE|ALX },
+{"lwc3",               "E,A(b)",       0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1,             0,      I3_32|EE|ALX },
 {"lwl",                        "t,o(b)",       0x88000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      I37 },
 {"lwl",                        "t,A(b)",       0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1,             0,      I37 },
 {"lcache",             "t,o(b)",       0x88000000, 0xfc000000, WR_1|RD_3|LM,           0,              I2,             0,      I37 }, /* same */
@@ -1371,7 +1371,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madd.ps",            "D,R,S,T",      0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,         I5_33,          0,      I37 },
 {"madd.ps",            "D,S,T",        0x45600018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,         0,         IL2E,           0,      0 },
 {"madd.ps",            "D,S,T",        0x72c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,         0,         IL2F,           0,      0 },
-{"madd",               "s,t",          0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,         L1|AL,          0,      0 },
+{"madd",               "s,t",          0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,         L1|ALX,         0,      0 },
 {"madd",               "s,t",          0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,         I32|N55,        0,      I37 },
 {"madd",               "s,t",          0x70000000, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M,      0,         G1,             0,      0 },
 {"madd",               "7,s,t",        0x70000000, 0xfc00e7ff, RD_2|RD_3|MOD_a,             0,         0,              D32,    0 },
@@ -1380,7 +1380,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madd1",              "d,s,t",        0x70000020, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,         EE,             0,      0 },
 {"madda.s",            "S,T",          0x4600001e, 0xffe007ff, RD_1|RD_2|FP_S,              0,         EE,             0,      0 },
 {"maddp",              "s,t",          0x70000441, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,         0,              SMT,    0 },
-{"maddu",              "s,t",          0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,         L1|AL,          0,      0 },
+{"maddu",              "s,t",          0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,         L1|ALX,         0,      0 },
 {"maddu",              "s,t",          0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,         I32|N55,        0,      I37 },
 {"maddu",              "s,t",          0x70000001, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M,      0,         G1,             0,      0 },
 {"maddu",              "7,s,t",        0x70000001, 0xfc00e7ff, RD_2|RD_3|MOD_a,             0,         0,              D32,    0 },
@@ -1388,7 +1388,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"maddu1",             "s,t",          0x70000021, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M,      0,         EE,             0,      0 },
 {"maddu1",             "d,s,t",        0x70000021, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,         EE,             0,      0 },
 {"madd16",             "s,t",          0x00000028, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              N411,           0,      0 },
-{"max",                        "d,v,t",        0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              AL,             0,      0 },
+{"max",                        "d,v,t",        0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              ALX,            0,      0 },
 {"max.ob",             "X,Y,Q",        0x78000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"max.ob",             "D,S,Q",        0x48000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"max.qh",             "X,Y,Q",        0x78200007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1435,7 +1435,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* mfc2 is at the bottom of the table.  */
 /* mfhc2 is at the bottom of the table.  */
 /* mfc3 is at the bottom of the table.  */
-{"mfdr",               "t,G",          0x7000003d, 0xffe007ff, WR_1|RD_C0|LC,          0,              N5|AL,          0,      0 },
+{"mfdr",               "t,G",          0x7000003d, 0xffe007ff, WR_1|RD_C0|LC,          0,              N5|ALX,         0,      0 },
 {"mfhi",               "d",            0x00000010, 0xffff07ff, WR_1|RD_HI,             0,              I1,             0,      I37 },
 {"mfhi",               "d,9",          0x00000010, 0xff9f07ff, WR_1|RD_HI,             0,              0,              D32,    0 },
 {"mfhi1",              "d",            0x70000010, 0xffff07ff, WR_1|RD_HI,             0,              EE,             0,      0 },
@@ -1445,7 +1445,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mflhxu",             "d",            0x00000052, 0xffff07ff, WR_1|MOD_HILO,          0,              0,              SMT,    0 },
 {"mfcr",               "t,s",          0x70000018, 0xfc00ffff, WR_1|RD_2,              0,              XLR,            0,      0 },
 {"mfsa",               "d",            0x00000028, 0xffff07ff, WR_1,                   0,              EE,             0,      0 },
-{"min",                        "d,v,t",        0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              AL,             0,      0 },
+{"min",                        "d,v,t",        0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              ALX,            0,      0 },
 {"min.ob",             "X,Y,Q",        0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"min.ob",             "D,S,Q",        0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"min.qh",             "X,Y,Q",        0x78200006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1461,7 +1461,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movf.l",             "X,Y,N",        0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              SB1,            MX,     0 },
 {"movf.s",             "D,S,N",        0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,              I4_32,          0,      I37 },
 {"movf.ps",            "D,S,N",        0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I5_33,          0,      I37 },
-{"movn",               "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I4_32|IL2E|IL2F|EE|AL, 0,       I37 },
+{"movn",               "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I4_32|IL2E|IL2F|EE|ALX, 0,      I37 },
 {"movnz",              "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E|IL2F,      LEXT,   0 },
 {"ffc",                        "d,v",          0x0000000b, 0xfc1f07ff, WR_1|RD_2,              0,              L1,             0,      0 },
 {"movn.d",             "D,S,t",        0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I4_32,          0,      I37 },
@@ -1475,7 +1475,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movt.l",             "X,Y,N",        0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              SB1,            MX,     0 },
 {"movt.s",             "D,S,N",        0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,              I4_32,          0,      I37 },
 {"movt.ps",            "D,S,N",        0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I5_33,          0,      I37 },
-{"movz",               "d,v,t",        0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I4_32|IL2E|IL2F|EE|AL, 0,       I37 },
+{"movz",               "d,v,t",        0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I4_32|IL2E|IL2F|EE|ALX, 0,      I37 },
 {"ffs",                        "d,v",          0x0000000a, 0xfc1f07ff, WR_1|RD_2,              0,              L1,             0,      0 },
 {"movz.d",             "D,S,t",        0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I4_32,          0,      I37 },
 {"movz.l",             "D,S,t",        0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
@@ -1503,12 +1503,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msub.ps",            "D,R,S,T",      0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I5_33,          0,      I37 },
 {"msub.ps",            "D,S,T",        0x45600019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"msub.ps",            "D,S,T",        0x72c00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F,           0,      0 },
-{"msub",               "s,t",          0x0000002e, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              AL,             0,      0 },
+{"msub",               "s,t",          0x0000002e, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              ALX,            0,      0 },
 {"msub",               "s,t",          0x0000001e, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              L1,             0,      0 },
 {"msub",               "s,t",          0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              I32|N55,        0,      I37 },
 {"msub",               "7,s,t",        0x70000004, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,              D32,    0 },
 {"msuba.s",            "S,T",          0x4600001f, 0xffe007ff, RD_1|RD_2|FP_S,         0,              EE,             0,      0 },
-{"msubu",              "s,t",          0x0000002f, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              AL,             0,      0 },
+{"msubu",              "s,t",          0x0000002f, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              ALX,            0,      0 },
 {"msubu",              "s,t",          0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              L1,             0,      0 },
 {"msubu",              "s,t",          0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              I32|N55,        0,      I37 },
 {"msubu",              "7,s,t",        0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,              D32,    0 },
@@ -1536,7 +1536,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* mtc2 is at the bottom of the table.  */
 /* mthc2 is at the bottom of the table.  */
 /* mtc3 is at the bottom of the table.  */
-{"mtdr",               "t,G",          0x7080003d, 0xffe007ff, RD_1|WR_C0|CM,          0,              N5|AL,          0,      0 },
+{"mtdr",               "t,G",          0x7080003d, 0xffe007ff, RD_1|WR_C0|CM,          0,              N5|ALX,         0,      0 },
 {"mthi",               "s",            0x00000011, 0xfc1fffff, RD_1|WR_HI,             0,              I1,             0,      I37 },
 {"mthi",               "s,7",          0x00000011, 0xfc1fe7ff, RD_1|WR_HI,             0,              0,              D32,    0 },
 {"mthi1",              "s",            0x70000011, 0xfc1fffff, RD_1|WR_HI,             0,              EE,             0,      0 },
@@ -1807,13 +1807,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"rol",                        "d,v,I",        0,    (int) M_ROL_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"ror",                        "d,v,t",        0,    (int) M_ROR,      INSN_MACRO,             0,              I1,             0,      0 },
 {"ror",                        "d,v,I",        0,    (int) M_ROR_I,    INSN_MACRO,             0,              I1,             0,      0 },
-{"ror",                        "d,w,<",        0x00200002, 0xffe0003f, WR_1|RD_2,              0,              N5|I33|AL,      SMT,    0 },
-{"rorv",               "d,t,s",        0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              N5|I33|AL,      SMT,    0 },
-{"rotl",               "d,v,t",        0,    (int) M_ROL,      INSN_MACRO,             0,              I33|AL,         SMT,    0 },
-{"rotl",               "d,v,I",        0,    (int) M_ROL_I,    INSN_MACRO,             0,              I33|AL,         SMT,    0 },
-{"rotr",               "d,v,t",        0,    (int) M_ROR,      INSN_MACRO,             0,              I33|AL,         SMT,    0 },
-{"rotr",               "d,v,I",        0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33|AL,         SMT,    0 },
-{"rotrv",              "d,t,s",        0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I33|AL,         SMT,    0 },
+{"ror",                        "d,w,<",        0x00200002, 0xffe0003f, WR_1|RD_2,              0,              N5|I33|ALX,     SMT,    0 },
+{"rorv",               "d,t,s",        0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              N5|I33|ALX,     SMT,    0 },
+{"rotl",               "d,v,t",        0,    (int) M_ROL,      INSN_MACRO,             0,              I33|ALX,        SMT,    0 },
+{"rotl",               "d,v,I",        0,    (int) M_ROL_I,    INSN_MACRO,             0,              I33|ALX,        SMT,    0 },
+{"rotr",               "d,v,t",        0,    (int) M_ROR,      INSN_MACRO,             0,              I33|ALX,        SMT,    0 },
+{"rotr",               "d,v,I",        0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33|ALX,        SMT,    0 },
+{"rotrv",              "d,t,s",        0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I33|ALX,        SMT,    0 },
 {"round.l.d",          "D,S",          0x46200008, 0xffff003f, WR_1|RD_2|FP_D,         0,              I3_33,          0,      0 },
 {"round.l.s",          "D,S",          0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I3_33,          0,      0 },
 {"round.w.d",          "D,S",          0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I2,             0,      SF },
@@ -1863,10 +1863,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdc1",               "T,A(b)",       0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,             0,      SF },
 {"sdc1",               "E,A(b)",       0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,             0,      SF },
 {"sdc2",               "E,+:(d)",      0x49e00000, 0xffe00000, RD_3|RD_C2|SM,          0,              I37,            0,      0 },
-{"sdc2",               "E,o(b)",       0xf8000000, 0xfc000000, RD_3|RD_C2|SM,          0,              I2,             0,      N54|IOCT|IOCTP|IOCT2|EE|AL|I37 },
-{"sdc2",               "E,A(b)",       0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2,             0,      N54|IOCT|IOCTP|IOCT2|EE|AL },
-{"sdc3",               "E,o(b)",       0xfc000000, 0xfc000000, RD_3|RD_C3|SM,          0,              I2,             0,      I3_32|EE|AL },
-{"sdc3",               "E,A(b)",       0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2,             0,      I3_32|EE|AL },
+{"sdc2",               "E,o(b)",       0xf8000000, 0xfc000000, RD_3|RD_C2|SM,          0,              I2,             0,      N54|IOCT|IOCTP|IOCT2|EE|ALX|I37 },
+{"sdc2",               "E,A(b)",       0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2,             0,      N54|IOCT|IOCTP|IOCT2|EE|ALX },
+{"sdc3",               "E,o(b)",       0xfc000000, 0xfc000000, RD_3|RD_C3|SM,          0,              I2,             0,      I3_32|EE|ALX },
+{"sdc3",               "E,A(b)",       0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2,             0,      I3_32|EE|ALX },
 {"s.d",                        "T,o(b)",       0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D,      0,              I2,             0,      SF },
 {"s.d",                        "T,A(b)",       0,    (int) M_S_DAB,    INSN_MACRO,             INSN2_M_FP_D,   I1,             0,      0 },
 {"sdl",                        "t,o(b)",       0xb0000000, 0xfc000000, RD_1|RD_3|SM,           0,              I3,             0,      I69 },
@@ -1874,8 +1874,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdr",                        "t,o(b)",       0xb4000000, 0xfc000000, RD_1|RD_3|SM,           0,              I3,             0,      I69 },
 {"sdr",                        "t,A(b)",       0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3,             0,      I69 },
 {"sdxc1",              "S,t(b)",       0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0,              I4_33,          0,      I37 },
-{"seb",                        "d,w",          0x7c000420, 0xffe007ff, WR_1|RD_2,              0,              I33|AL,         0,      0 },
-{"seh",                        "d,w",          0x7c000620, 0xffe007ff, WR_1|RD_2,              0,              I33|AL,         0,      0 },
+{"seb",                        "d,w",          0x7c000420, 0xffe007ff, WR_1|RD_2,              0,              I33|ALX,        0,      0 },
+{"seh",                        "d,w",          0x7c000620, 0xffe007ff, WR_1|RD_2,              0,              I33|ALX,        0,      0 },
 {"selsl",              "d,v,t",        0x00000005, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              L1,             0,      0 },
 {"selsr",              "d,v,t",        0x00000001, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              L1,             0,      0 },
 {"seq",                        "d,v,t",        0x7000002a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IOCT,           0,      0 },
@@ -2000,8 +2000,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"swc2",               "E,+:(d)",      0x49600000, 0xffe00000, RD_3|RD_C2|SM,          0,              I37,            0,      0 },
 {"swc2",               "E,o(b)",       0xe8000000, 0xfc000000, RD_3|RD_C2|SM,          0,              I1,             0,      N54|IOCT|IOCTP|IOCT2|EE|I37 },
 {"swc2",               "E,A(b)",       0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1,             0,      N54|IOCT|IOCTP|IOCT2|EE },
-{"swc3",               "E,o(b)",       0xec000000, 0xfc000000, RD_3|RD_C3|SM,          0,              I1,             0,      I3_32|EE|AL },
-{"swc3",               "E,A(b)",       0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1,             0,      I3_32|EE|AL },
+{"swc3",               "E,o(b)",       0xec000000, 0xfc000000, RD_3|RD_C3|SM,          0,              I1,             0,      I3_32|EE|ALX },
+{"swc3",               "E,A(b)",       0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1,             0,      I3_32|EE|ALX },
 {"swl",                        "t,o(b)",       0xa8000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      I37 },
 {"swl",                        "t,A(b)",       0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1,             0,      I37 },
 {"scache",             "t,o(b)",       0xa8000000, 0xfc000000, RD_1|RD_3,              0,              I2,             0,      I37 }, /* same */
@@ -2027,21 +2027,21 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"synci",              "o(b)",         0x041f0000, 0xfc1f0000, RD_2|SM,                0,              I33,            0,      0 },
 {"syscall",            "",             0x0000000c, 0xffffffff, TRAP,                   0,              I1,             0,      0 },
 {"syscall",            "B",            0x0000000c, 0xfc00003f, TRAP,                   0,              I1,             0,      0 },
-{"teqi",               "s,j",          0x040c0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL },
-{"teq",                        "s,t",          0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"teq",                        "s,t,q",        0x00000034, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"teq",                        "s,j",          0x040c0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL }, /* teqi */
-{"teq",                        "s,I",          0,    (int) M_TEQ_I,    INSN_MACRO,             0,              I2,             0,      AL },
-{"tgei",               "s,j",          0x04080000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL },
-{"tge",                        "s,t",          0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"tge",                        "s,t,q",        0x00000030, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"tge",                        "s,j",          0x04080000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL }, /* tgei */
-{"tge",                        "s,I",          0,    (int) M_TGE_I,    INSN_MACRO,             0,              I2,             0,      AL },
-{"tgeiu",              "s,j",          0x04090000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL },
-{"tgeu",               "s,t",          0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"tgeu",               "s,t,q",        0x00000031, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"tgeu",               "s,j",          0x04090000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL }, /* tgeiu */
-{"tgeu",               "s,I",          0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2,             0,      AL },
+{"teqi",               "s,j",          0x040c0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX },
+{"teq",                        "s,t",          0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"teq",                        "s,t,q",        0x00000034, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"teq",                        "s,j",          0x040c0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX }, /* teqi */
+{"teq",                        "s,I",          0,    (int) M_TEQ_I,    INSN_MACRO,             0,              I2,             0,      ALX },
+{"tgei",               "s,j",          0x04080000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX },
+{"tge",                        "s,t",          0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"tge",                        "s,t,q",        0x00000030, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"tge",                        "s,j",          0x04080000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX }, /* tgei */
+{"tge",                        "s,I",          0,    (int) M_TGE_I,    INSN_MACRO,             0,              I2,             0,      ALX },
+{"tgeiu",              "s,j",          0x04090000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX },
+{"tgeu",               "s,t",          0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"tgeu",               "s,t,q",        0x00000031, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"tgeu",               "s,j",          0x04090000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX }, /* tgeiu */
+{"tgeu",               "s,I",          0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2,             0,      ALX },
 {"tlbinv",             "",             0x42000003, 0xffffffff, INSN_TLB,               0,              I37,            TLBINV, 0 },
 {"tlbinvf",            "",             0x42000004, 0xffffffff, INSN_TLB,               0,              I37,            TLBINV, 0 },
 {"tlbp",               "",             0x42000008, 0xffffffff, INSN_TLB,               0,              I1,             0,      0 },
@@ -2054,21 +2054,21 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tlbginvf",           "",             0x4200000c, 0xffffffff, INSN_TLB,               0,              0,              IVIRT,  0 },
 {"tlbgwr",             "",             0x4200000e, 0xffffffff, INSN_TLB,               0,              0,              IVIRT,  0 },
 {"tlbgp",              "",             0x42000010, 0xffffffff, INSN_TLB,               0,              0,              IVIRT,  0 },
-{"tlti",               "s,j",          0x040a0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL },
-{"tlt",                        "s,t",          0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"tlt",                        "s,t,q",        0x00000032, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"tlt",                        "s,j",          0x040a0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL }, /* tlti */
-{"tlt",                        "s,I",          0,    (int) M_TLT_I,    INSN_MACRO,             0,              I2,             0,      AL },
-{"tltiu",              "s,j",          0x040b0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL },
-{"tltu",               "s,t",          0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"tltu",               "s,t,q",        0x00000033, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"tltu",               "s,j",          0x040b0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL }, /* tltiu */
-{"tltu",               "s,I",          0,    (int) M_TLTU_I,   INSN_MACRO,             0,              I2,             0,      AL },
-{"tnei",               "s,j",          0x040e0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL },
-{"tne",                        "s,t",          0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"tne",                        "s,t,q",        0x00000036, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      AL },
-{"tne",                        "s,j",          0x040e0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|AL }, /* tnei */
-{"tne",                        "s,I",          0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2,             0,      AL },
+{"tlti",               "s,j",          0x040a0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX },
+{"tlt",                        "s,t",          0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"tlt",                        "s,t,q",        0x00000032, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"tlt",                        "s,j",          0x040a0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX }, /* tlti */
+{"tlt",                        "s,I",          0,    (int) M_TLT_I,    INSN_MACRO,             0,              I2,             0,      ALX },
+{"tltiu",              "s,j",          0x040b0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX },
+{"tltu",               "s,t",          0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"tltu",               "s,t,q",        0x00000033, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"tltu",               "s,j",          0x040b0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX }, /* tltiu */
+{"tltu",               "s,I",          0,    (int) M_TLTU_I,   INSN_MACRO,             0,              I2,             0,      ALX },
+{"tnei",               "s,j",          0x040e0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX },
+{"tne",                        "s,t",          0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"tne",                        "s,t,q",        0x00000036, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      ALX },
+{"tne",                        "s,j",          0x040e0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37|ALX }, /* tnei */
+{"tne",                        "s,I",          0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2,             0,      ALX },
 {"trunc.l.d",          "D,S",          0x46200009, 0xffff003f, WR_1|RD_2|FP_D,         0,              I3_33,          0,      0 },
 {"trunc.l.s",          "D,S",          0x46000009, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I3_33,          0,      0 },
 {"trunc.w.d",          "D,S",          0x4620000d, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I2,             0,      SF },
@@ -2098,8 +2098,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"wait",               "J",            0x42000020, 0xfe00003f, NODS,                   0,              I32|N55,        0,      0 },
 {"waiti",              "",             0x42000020, 0xffffffff, NODS,                   0,              L1,             0,      0 },
 {"wrpgpr",             "d,w",          0x41c00000, 0xffe007ff, RD_2,                   0,              I33,            0,      0 },
-{"wsbh",               "d,w",          0x7c0000a0, 0xffe007ff, WR_1|RD_2,              0,              I33|AL,         0,      0 },
-{"wsbw",               "d,w",          0x7c0000e0, 0xffe007ff, WR_1|RD_2,              0,              AL,             0,      0 },
+{"wsbh",               "d,w",          0x7c0000a0, 0xffe007ff, WR_1|RD_2,              0,              I33|ALX,        0,      0 },
+{"wsbw",               "d,w",          0x7c0000e0, 0xffe007ff, WR_1|RD_2,              0,              ALX,            0,      0 },
 {"xor",                        "d,v,t",        0x00000026, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"xor",                        "t,r,I",        0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"xor",                        "D,S,T",        0x47800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
@@ -2135,7 +2135,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addu_s.ob",          "d,s,t",        0x7c000114, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              D64,    0 },
 {"addu_s.qb",          "d,s,t",        0x7c000110, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              D32,    0 },
 {"addwc",              "d,s,t",        0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              0,              D32,    0 },
-{"bitrev",             "d,w",          0x7c000520, 0xffe007ff, WR_1|RD_2,              0,              AL,             0,      0 },
+{"bitrev",             "d,w",          0x7c000520, 0xffe007ff, WR_1|RD_2,              0,              ALX,            0,      0 },
 {"bitrev",             "d,t",          0x7c0006d2, 0xffe007ff, WR_1|RD_2,              0,              0,              D32,    0 },
 {"bposge32",           "p",            0x041c0000, 0xffff0000, CBD,                    0,              0,              D32,    0 },
 {"bposge32c",          "p",            0x04180000, 0xffff0000, NODS,                   FS,             0,              D34,    0 },
@@ -3353,7 +3353,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ctc0",               "t,g",          0x40c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      I32 },
 
 /* RFE conflicts with the new Virt spec instruction tlbgp. */
-{"rfe",                        "",             0x42000010, 0xffffffff, 0,                      0,              I1|T3,          0,      I3_32|AL },
+{"rfe",                        "",             0x42000010, 0xffffffff, 0,                      0,              I1|T3,          0,      I3_32|ALX },
 
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
@@ -3386,13 +3386,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfhc2",              "t,G",          0x48600000, 0xffe007ff, WR_1|RD_C2|LC,          0,              I33,            0,      IOCT|IOCTP|IOCT2 },
 {"mfhc2",              "t,G,H",        0x48600000, 0xffe007f8, WR_1|RD_C2|LC,          0,              I33,            0,      IOCT|IOCTP|IOCT2 },
 {"mfhc2",              "t,i",          0x48600000, 0xffe00000, WR_1|RD_C2|LC,          0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mfic",               "t,G",          0x70000024, 0xffe007ff, WR_1|RD_C0|LC,          0,              AL,             0,      0 },
+{"mfic",               "t,G",          0x70000024, 0xffe007ff, WR_1|RD_C0|LC,          0,              ALX,            0,      0 },
 {"mtc2",               "t,G",          0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM,    0,              I1,             0,      N54|IOCT|IOCTP|IOCT2|EE },
 {"mtc2",               "t,G,H",        0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM,    0,              I32,            0,      IOCT|IOCTP|IOCT2 },
 {"mthc2",              "t,G",          0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM,    0,              I33,            0,      IOCT|IOCTP|IOCT2 },
 {"mthc2",              "t,G,H",        0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM,    0,              I33,            0,      IOCT|IOCTP|IOCT2 },
 {"mthc2",              "t,i",          0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM,    0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mtic",               "t,G",          0x70000026, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              AL,             0,      0 },
+{"mtic",               "t,G",          0x70000026, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              ALX,            0,      0 },
 {"qmfc2",              "t,+6",         0x48200000, 0xffe007ff, WR_1|RD_C2,             0,              EE,             0,      0 },
 {"qmfc2.i",            "t,+6",         0x48200001, 0xffe007ff, WR_1|RD_C2,             0,              EE,             0,      0 },
 {"qmfc2.ni",           "t,+6",         0x48200000, 0xffe007ff, WR_1|RD_C2,             0,              EE,             0,      0 },
@@ -3402,16 +3402,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
    instructions, so they are here for the latters to take precedence.  */
-{"bc3f",               "p",            0x4d000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      I3_33|EE|AL },
-{"bc3fl",              "p",            0x4d020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      I3_33|EE|AL },
-{"bc3t",               "p",            0x4d010000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      I3_33|EE|AL },
-{"bc3tl",              "p",            0x4d030000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      I3_33|EE|AL },
-{"cfc3",               "t,g",          0x4c400000, 0xffe007ff, WR_1|RD_C3|LC,          0,              I1,             0,      I3_33|EE|AL },
-{"ctc3",               "t,g",          0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      I3_33|EE|AL },
-{"mfc3",               "t,G",          0x4c000000, 0xffe007ff, WR_1|RD_C3|LC,          0,              I1,             0,      I3_33|EE|AL },
-{"mfc3",               "t,G,H",        0x4c000000, 0xffe007f8, WR_1|RD_C3|LC,          0,              I32,            0,      I3_33|EE|AL },
-{"mtc3",               "t,G",          0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM,    0,              I1,             0,      I3_33|EE|AL },
-{"mtc3",               "t,G,H",        0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM,    0,              I32,            0,      I3_33|EE|AL },
+{"bc3f",               "p",            0x4d000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      I3_33|EE|ALX },
+{"bc3fl",              "p",            0x4d020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      I3_33|EE|ALX },
+{"bc3t",               "p",            0x4d010000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      I3_33|EE|ALX },
+{"bc3tl",              "p",            0x4d030000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      I3_33|EE|ALX },
+{"cfc3",               "t,g",          0x4c400000, 0xffe007ff, WR_1|RD_C3|LC,          0,              I1,             0,      I3_33|EE|ALX },
+{"ctc3",               "t,g",          0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      I3_33|EE|ALX },
+{"mfc3",               "t,G",          0x4c000000, 0xffe007ff, WR_1|RD_C3|LC,          0,              I1,             0,      I3_33|EE|ALX },
+{"mfc3",               "t,G,H",        0x4c000000, 0xffe007f8, WR_1|RD_C3|LC,          0,              I32,            0,      I3_33|EE|ALX },
+{"mtc3",               "t,G",          0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM,    0,              I1,             0,      I3_33|EE|ALX },
+{"mtc3",               "t,G,H",        0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM,    0,              I32,            0,      I3_33|EE|ALX },
 
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the