]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: ti: k3-am62/a: use sub-node for USB_PHY_CTRL registers
authorRoger Quadros <rogerq@kernel.org>
Fri, 12 Apr 2024 12:01:58 +0000 (15:01 +0300)
committerNishanth Menon <nm@ti.com>
Mon, 29 Apr 2024 19:35:28 +0000 (14:35 -0500)
Exposing the entire CTRL_MMR space to syscon is not a good idea.
Add sub-nodes for USB0_PHY_CTRL and USB1_PHY_CTRL and use them
in the USB0/USB1 nodes.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240412-for-v6-10-am62-usb-typec-dt-v7-1-93b827adf97e@kernel.org
Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi

index e0ec28b14a07aa142013573e449e977713dd076d..448a59dc53a77c9bc6dca12d0914118eb85141da 100644 (file)
                      <0x00 0x0f908000 0x00 0x400>;
                clocks = <&k3_clks 161 3>;
                clock-names = "ref";
-               ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
+               ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
                #address-cells = <2>;
                #size-cells = <2>;
                power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
                      <0x00 0x0f918000 0x00 0x400>;
                clocks = <&k3_clks 162 3>;
                clock-names = "ref";
-               ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
+               ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
                #address-cells = <2>;
                #size-cells = <2>;
                power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
index 23ce1bfda8d6abbb75472d3b8a321f6e9eb3d8c3..66ddf2dc51afa7870a27ebabac19799726a834aa 100644 (file)
                        compatible = "ti,am654-chipid";
                        reg = <0x14 0x4>;
                };
+
+               usb0_phy_ctrl: syscon@4008 {
+                       compatible = "ti,am62-usb-phy-ctrl", "syscon";
+                       reg = <0x4008 0x4>;
+               };
+
+               usb1_phy_ctrl: syscon@4018 {
+                       compatible = "ti,am62-usb-phy-ctrl", "syscon";
+                       reg = <0x4018 0x4>;
+               };
        };
 
        target-module@2b300050 {
index 93494e30305bd2d52128e020813732e83f116fa9..31fc59b02f21a957988c5ba4890b4c959af49007 100644 (file)
                      <0x00 0x0f908000 0x00 0x400>;
                clocks = <&k3_clks 161 3>;
                clock-names = "ref";
-               ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
+               ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>;
                #address-cells = <2>;
                #size-cells = <2>;
                power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
                      <0x00 0x0f918000 0x00 0x400>;
                clocks = <&k3_clks 162 3>;
                clock-names = "ref";
-               ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
+               ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
                #address-cells = <2>;
                #size-cells = <2>;
                power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
index f7bec484705ad61f894aa58d91c4e1bb4feb3029..98043e9aa316b82f1c781eb1f4c84dded1e81ec6 100644 (file)
                        compatible = "ti,am654-chipid";
                        reg = <0x14 0x4>;
                };
+
+               usb0_phy_ctrl: syscon@4008 {
+                       compatible = "ti,am62-usb-phy-ctrl", "syscon";
+                       reg = <0x4008 0x4>;
+               };
+
+               usb1_phy_ctrl: syscon@4018 {
+                       compatible = "ti,am62-usb-phy-ctrl", "syscon";
+                       reg = <0x4018 0x4>;
+               };
        };
 
        wkup_uart0: serial@2b300000 {