drm/gfx10: Program DB_RING_CONTROL

This is needed to allocate occlusion counters across
both gfx pipes.

Fixes: b7a1a0ef12b8 ("drm/amd/amdgpu: add pipe1 hardware support")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 6807352cbabb74b61ba42888769283af72191f66)
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index b4b27e4c495d20be51433e10eae91e8536852e66..a9961d5048333812873eb2c171f7fc56acf3d7ee 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5350,6 +5350,15 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
        gfx_v10_0_get_tcc_info(adev);
        adev->gfx.config.pa_sc_tile_steering_override =
                gfx_v10_0_init_pa_sc_tile_steering_override(adev);
+       /* Program DB_RING_CONTROL for multiple GFX pipes
+        * Default power up value is 1.
+        * Possible values:
+        * 0 - split occlusion counters between gfx pipes
+        * 1 - all occlusion counters to pipe 0
+        * 2 - all occlusion counters to pipe 1
+        */
+       WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL,
+                      (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1);
 
        /* XXX SH_MEM regs */
        /* where to put LDS, scratch, GPUVM in FSA64 space */