5.10-stable patches

added patches:
	x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch

diff --git a/queue-5.10/series b/queue-5.10/series
index 9be22a2112cb6a3aed62a19b2f28ff80597b1857..0d8a295dc650c23b39d5ab63fa6e0b3c334d0717 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -178,3 +178,4 @@ dt-binding-cdns-usb3-fix-cdns-on-chip-buff-size-type.patch
 x86-mm-avoid-incomplete-global-invlpg-flushes.patch
 selftests-memfd-fix-unknown-type-name-build-failure.patch
 parisc-fix-flush_dcache_page-for-usage-from-irq-context.patch
+x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch

diff --git a/queue-5.10/x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch b/queue-5.10/x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch
new file mode 100644 (file)
index 0000000..85cad4c
--- /dev/null
+++ b/queue-5.10/x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch
@@ -0,0 +1,90 @@
+From edc0a2b5957652f4685ef3516f519f84807087db Mon Sep 17 00:00:00 2001
+From: Zhang Rui <rui.zhang@intel.com>
+Date: Thu, 23 Mar 2023 09:56:40 +0800
+Subject: x86/topology: Fix erroneous smp_num_siblings on Intel Hybrid platforms
+
+From: Zhang Rui <rui.zhang@intel.com>
+
+commit edc0a2b5957652f4685ef3516f519f84807087db upstream.
+
+Traditionally, all CPUs in a system have identical numbers of SMT
+siblings.  That changes with hybrid processors where some logical CPUs
+have a sibling and others have none.
+
+Today, the CPU boot code sets the global variable smp_num_siblings when
+every CPU thread is brought up. The last thread to boot will overwrite
+it with the number of siblings of *that* thread. That last thread to
+boot will "win". If the thread is a Pcore, smp_num_siblings == 2.  If it
+is an Ecore, smp_num_siblings == 1.
+
+smp_num_siblings describes if the *system* supports SMT.  It should
+specify the maximum number of SMT threads among all cores.
+
+Ensure that smp_num_siblings represents the system-wide maximum number
+of siblings by always increasing its value. Never allow it to decrease.
+
+On MeteorLake-P platform, this fixes a problem that the Ecore CPUs are
+not updated in any cpu sibling map because the system is treated as an
+UP system when probing Ecore CPUs.
+
+Below shows part of the CPU topology information before and after the
+fix, for both Pcore and Ecore CPU (cpu0 is Pcore, cpu 12 is Ecore).
+...
+-/sys/devices/system/cpu/cpu0/topology/package_cpus:000fff
+-/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-11
++/sys/devices/system/cpu/cpu0/topology/package_cpus:3fffff
++/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-21
+...
+-/sys/devices/system/cpu/cpu12/topology/package_cpus:001000
+-/sys/devices/system/cpu/cpu12/topology/package_cpus_list:12
++/sys/devices/system/cpu/cpu12/topology/package_cpus:3fffff
++/sys/devices/system/cpu/cpu12/topology/package_cpus_list:0-21
+
+Notice that the "before" 'package_cpus_list' has only one CPU.  This
+means that userspace tools like lscpu will see a little laptop like
+an 11-socket system:
+
+-Core(s) per socket:  1
+-Socket(s):           11
++Core(s) per socket:  16
++Socket(s):           1
+
+This is also expected to make the scheduler do rather wonky things
+too.
+
+[ dhansen: remove CPUID detail from changelog, add end user effects ]
+
+CC: stable@kernel.org
+Fixes: bbb65d2d365e ("x86: use cpuid vector 0xb when available for detecting cpu topology")
+Fixes: 95f3d39ccf7a ("x86/cpu/topology: Provide detect_extended_topology_early()")
+Suggested-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
+Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
+Link: https://lore.kernel.org/all/20230323015640.27906-1-rui.zhang%40intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/cpu/topology.c |    5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/kernel/cpu/topology.c
++++ b/arch/x86/kernel/cpu/topology.c
+@@ -79,7 +79,7 @@ int detect_extended_topology_early(struc
+        * initial apic id, which also represents 32-bit extended x2apic id.
+        */
+       c->initial_apicid = edx;
+-      smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx);
++      smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx));
+ #endif
+       return 0;
+ }
+@@ -109,7 +109,8 @@ int detect_extended_topology(struct cpui
+        */
+       cpuid_count(leaf, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
+       c->initial_apicid = edx;
+-      core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx);
++      core_level_siblings = LEVEL_MAX_SIBLINGS(ebx);
++      smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx));
+       core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
+       die_level_siblings = LEVEL_MAX_SIBLINGS(ebx);
+       pkg_mask_width = die_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);