--- /dev/null
+From 0811b9e4530d7c46542a8993ce6b725d042c6154 Mon Sep 17 00:00:00 2001
+From: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Date: Thu, 6 Oct 2022 17:17:40 -0400
+Subject: drm/amd/display: Add HUBP surface flip interrupt handler
+
+From: Aurabindo Pillai <aurabindo.pillai@amd.com>
+
+commit 0811b9e4530d7c46542a8993ce6b725d042c6154 upstream.
+
+Add the hubp surface flip handler. This fixes some flip timeout issues.
+
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 6.0.x
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubp.c
+@@ -179,6 +179,7 @@ static struct hubp_funcs dcn32_hubp_func
+ .hubp_init = hubp3_init,
+ .set_unbounded_requesting = hubp31_set_unbounded_requesting,
+ .hubp_soft_reset = hubp31_soft_reset,
++ .hubp_set_flip_int = hubp1_set_flip_int,
+ .hubp_in_blank = hubp1_in_blank,
+ .hubp_update_force_pstate_disallow = hubp32_update_force_pstate_disallow,
+ .phantom_hubp_post_enable = hubp32_phantom_hubp_post_enable,
--- /dev/null
+From 54fae65ff469a79fc0ca46f480c4e7fce50f3963 Mon Sep 17 00:00:00 2001
+From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Date: Tue, 20 Sep 2022 16:06:36 -0400
+Subject: drm/amd/display: Enable 2 to 1 ODM policy if supported
+
+From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+
+commit 54fae65ff469a79fc0ca46f480c4e7fce50f3963 upstream.
+
+If the current configuration supports 2 to 1 ODM policy, let's also
+enable the windowed MPO feature.
+
+Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
+Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 6.0.x
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+@@ -1001,6 +1001,10 @@ void dcn32_init_hw(struct dc *dc)
+ dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
+ dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
+ }
++
++ /* Enable support for ODM and windowed MPO if policy flag is set */
++ if (dc->debug.enable_single_display_2to1_odm_policy)
++ dc->config.enable_windowed_mpo_odm = true;
+ }
+
+ static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
--- /dev/null
+From f6aa84b83aee629fbbbc4ea16c2c142caf920d5a Mon Sep 17 00:00:00 2001
+From: Roman Li <roman.li@amd.com>
+Date: Thu, 29 Sep 2022 14:37:00 -0400
+Subject: drm/amd/display: Enable dpia support for dcn314
+
+From: Roman Li <roman.li@amd.com>
+
+commit f6aa84b83aee629fbbbc4ea16c2c142caf920d5a upstream.
+
+[Why]
+DCN 3.1.4 supports DPIA.
+
+[How]
+ - Set dpia_supported flag for dcn314 in dmub_hw_init()
+ - Remove comment that becomes irrelevant after this change.
+
+Signed-off-by: Roman Li <roman.li@amd.com>
+Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
+Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 6.0.x
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -1109,7 +1109,8 @@ static int dm_dmub_hw_init(struct amdgpu
+ hw_params.fb[i] = &fb_info->fb[i];
+
+ switch (adev->ip_versions[DCE_HWIP][0]) {
+- case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */
++ case IP_VERSION(3, 1, 3):
++ case IP_VERSION(3, 1, 4):
+ hw_params.dpia_supported = true;
+ hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
+ break;
--- /dev/null
+From 6094b9136ca9038b61e9c4b5d25cd5512ce50b34 Mon Sep 17 00:00:00 2001
+From: Shirish S <shirish.s@amd.com>
+Date: Fri, 7 Oct 2022 20:31:49 +0530
+Subject: drm/amd/display: explicitly disable psr_feature_enable appropriately
+
+From: Shirish S <shirish.s@amd.com>
+
+commit 6094b9136ca9038b61e9c4b5d25cd5512ce50b34 upstream.
+
+[Why]
+If psr_feature_enable is set to true by default, it continues to be enabled
+for non capable links.
+
+[How]
+explicitly disable the feature on links that are not capable of the same.
+
+Fixes: 8c322309e48e9 ("drm/amd/display: Enable PSR")
+Signed-off-by: Shirish S <shirish.s@amd.com>
+Reviewed-by: Leo Li <sunpeng.li@amd.com>
+Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 5.15+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+@@ -60,11 +60,15 @@ static bool link_supports_psrsu(struct d
+ */
+ void amdgpu_dm_set_psr_caps(struct dc_link *link)
+ {
+- if (!(link->connector_signal & SIGNAL_TYPE_EDP))
++ if (!(link->connector_signal & SIGNAL_TYPE_EDP)) {
++ link->psr_settings.psr_feature_enabled = false;
+ return;
++ }
+
+- if (link->type == dc_connection_none)
++ if (link->type == dc_connection_none) {
++ link->psr_settings.psr_feature_enabled = false;
+ return;
++ }
+
+ if (link->dpcd_caps.psr_info.psr_version == 0) {
+ link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
--- /dev/null
+From 8799c0be89ebb99a16098bdf618f49f817bef76a Mon Sep 17 00:00:00 2001
+From: Yunxiang Li <Yunxiang.Li@amd.com>
+Date: Wed, 21 Sep 2022 17:20:19 -0400
+Subject: drm/amd/display: Fix vblank refcount in vrr transition
+
+From: Yunxiang Li <Yunxiang.Li@amd.com>
+
+commit 8799c0be89ebb99a16098bdf618f49f817bef76a upstream.
+
+manage_dm_interrupts disable/enable vblank using drm_crtc_vblank_off/on
+which causes drm_crtc_vblank_get in vrr_transition to fail, and later
+when drm_crtc_vblank_put is called the refcount on vblank will be messed
+up. Therefore move the call to after manage_dm_interrupts.
+
+Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1247
+Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1380
+
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Yunxiang Li <Yunxiang.Li@amd.com>
+Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 55 ++++++++++------------
+ 1 file changed, 26 insertions(+), 29 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -7491,15 +7491,15 @@ static void amdgpu_dm_handle_vrr_transit
+ * We also need vupdate irq for the actual core vblank handling
+ * at end of vblank.
+ */
+- dm_set_vupdate_irq(new_state->base.crtc, true);
+- drm_crtc_vblank_get(new_state->base.crtc);
++ WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0);
++ WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
+ DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
+ __func__, new_state->base.crtc->base.id);
+ } else if (old_vrr_active && !new_vrr_active) {
+ /* Transition VRR active -> inactive:
+ * Allow vblank irq disable again for fixed refresh rate.
+ */
+- dm_set_vupdate_irq(new_state->base.crtc, false);
++ WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0);
+ drm_crtc_vblank_put(new_state->base.crtc);
+ DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
+ __func__, new_state->base.crtc->base.id);
+@@ -8254,23 +8254,6 @@ static void amdgpu_dm_atomic_commit_tail
+ mutex_unlock(&dm->dc_lock);
+ }
+
+- /* Count number of newly disabled CRTCs for dropping PM refs later. */
+- for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
+- new_crtc_state, i) {
+- if (old_crtc_state->active && !new_crtc_state->active)
+- crtc_disable_count++;
+-
+- dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+- dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+-
+- /* For freesync config update on crtc state and params for irq */
+- update_stream_irq_parameters(dm, dm_new_crtc_state);
+-
+- /* Handle vrr on->off / off->on transitions */
+- amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
+- dm_new_crtc_state);
+- }
+-
+ /**
+ * Enable interrupts for CRTCs that are newly enabled or went through
+ * a modeset. It was intentionally deferred until after the front end
+@@ -8280,16 +8263,29 @@ static void amdgpu_dm_atomic_commit_tail
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
+ #ifdef CONFIG_DEBUG_FS
+- bool configure_crc = false;
+ enum amdgpu_dm_pipe_crc_source cur_crc_src;
+ #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
+- struct crc_rd_work *crc_rd_wrk = dm->crc_rd_wrk;
++ struct crc_rd_work *crc_rd_wrk;
++#endif
++#endif
++ /* Count number of newly disabled CRTCs for dropping PM refs later. */
++ if (old_crtc_state->active && !new_crtc_state->active)
++ crtc_disable_count++;
++
++ dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
++ dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
++
++ /* For freesync config update on crtc state and params for irq */
++ update_stream_irq_parameters(dm, dm_new_crtc_state);
++
++#ifdef CONFIG_DEBUG_FS
++#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
++ crc_rd_wrk = dm->crc_rd_wrk;
+ #endif
+ spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
+ cur_crc_src = acrtc->dm_irq_params.crc_src;
+ spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
+ #endif
+- dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+
+ if (new_crtc_state->active &&
+ (!old_crtc_state->active ||
+@@ -8297,16 +8293,19 @@ static void amdgpu_dm_atomic_commit_tail
+ dc_stream_retain(dm_new_crtc_state->stream);
+ acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
+ manage_dm_interrupts(adev, acrtc, true);
++ }
++ /* Handle vrr on->off / off->on transitions */
++ amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
+
+ #ifdef CONFIG_DEBUG_FS
++ if (new_crtc_state->active &&
++ (!old_crtc_state->active ||
++ drm_atomic_crtc_needs_modeset(new_crtc_state))) {
+ /**
+ * Frontend may have changed so reapply the CRC capture
+ * settings for the stream.
+ */
+- dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+-
+ if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
+- configure_crc = true;
+ #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
+ if (amdgpu_dm_crc_window_is_activated(crtc)) {
+ spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
+@@ -8318,12 +8317,10 @@ static void amdgpu_dm_atomic_commit_tail
+ spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
+ }
+ #endif
+- }
+-
+- if (configure_crc)
+ if (amdgpu_dm_crtc_configure_crc_source(
+ crtc, dm_new_crtc_state, cur_crc_src))
+ DRM_DEBUG_DRIVER("Failed to configure crc source");
++ }
+ #endif
+ }
+ }
--- /dev/null
+From 9799702360d51a714e888fef4ab5fb9123dfb41f Mon Sep 17 00:00:00 2001
+From: Alvin Lee <Alvin.Lee2@amd.com>
+Date: Wed, 29 Jun 2022 12:35:12 -0400
+Subject: drm/amd/display: Fix watermark calculation
+
+From: Alvin Lee <Alvin.Lee2@amd.com>
+
+commit 9799702360d51a714e888fef4ab5fb9123dfb41f upstream.
+
+Watermark calculation was incorrect due to missing brackets.
+
+Fixes: 85f4bc0c333c ("drm/amd/display: Add SubVP required code")
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 6.0
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
++++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+@@ -719,7 +719,7 @@ void dc_dmub_setup_subvp_dmub_command(st
+ // Store the original watermark value for this SubVP config so we can lower it when the
+ // MCLK switch starts
+ wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
+- dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 / 1000;
++ (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
+
+ cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
+ }
--- /dev/null
+From 4f5bdde386d3b8e9317df5562950e1b4fa177599 Mon Sep 17 00:00:00 2001
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Date: Fri, 9 Sep 2022 15:24:55 -0400
+Subject: drm/amd/display: Update PMFW z-state interface for DCN314
+
+From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+
+commit 4f5bdde386d3b8e9317df5562950e1b4fa177599 upstream.
+
+[Why]
+Request from PMFW to change the messaging format to specify whether we
+support z-state via individual bits.
+
+[How]
+Update the args we pass in the support message.
+
+Fixes: d5c6909e7460 ("drm/amd/display: Add DCN314 clock manager")
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
+Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 6.0
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c | 11 +++--------
+ drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 3 ++-
+ 2 files changed, 5 insertions(+), 9 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
+@@ -339,29 +339,24 @@ void dcn314_smu_set_zstate_support(struc
+ if (!clk_mgr->smu_present)
+ return;
+
+- if (!clk_mgr->base.ctx->dc->debug.enable_z9_disable_interface &&
+- (support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY))
+- support = DCN_ZSTATE_SUPPORT_DISALLOW;
+-
+-
+ // Arg[15:0] = 8/9/0 for Z8/Z9/disallow -> existing bits
+ // Arg[16] = Disallow Z9 -> new bit
+ switch (support) {
+
+ case DCN_ZSTATE_SUPPORT_ALLOW:
+ msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
+- param = 9;
++ param = (1 << 10) | (1 << 9) | (1 << 8);
+ break;
+
+ case DCN_ZSTATE_SUPPORT_DISALLOW:
+ msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
+- param = 8;
++ param = 0;
+ break;
+
+
+ case DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY:
+ msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
+- param = 0x00010008;
++ param = (1 << 10);
+ break;
+
+ default: //DCN_ZSTATE_SUPPORT_UNKNOWN
+--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+@@ -881,7 +881,8 @@ static const struct dc_plane_cap plane_c
+ };
+
+ static const struct dc_debug_options debug_defaults_drv = {
+- .disable_z10 = true, /*hw not support it*/
++ .disable_z10 = false,
++ .enable_z9_disable_interface = true,
+ .disable_dmcu = true,
+ .force_abm_enable = false,
+ .timing_trace = false,
--- /dev/null
+From 876fcc4222e1d0e5b73343f4010a8b66be058f48 Mon Sep 17 00:00:00 2001
+From: Fangzhi Zuo <Jerry.Zuo@amd.com>
+Date: Tue, 30 Aug 2022 12:12:53 -0400
+Subject: drm/amd/display: Validate DSC After Enable All New CRTCs
+
+From: Fangzhi Zuo <Jerry.Zuo@amd.com>
+
+commit 876fcc4222e1d0e5b73343f4010a8b66be058f48 upstream.
+
+Before enabling new crtc, stream_count in dc_state does not sync with
+that in drm_atomic_state. Validating dsc in such case would leave newly
+added stream not jointly participating in dsc optimization with existing
+streams, but simply using default initialized vcpi all the time which
+gives wrong dsc determination decision.
+
+Consider the scenaio where one 4k60 connected to the dock under dp-alt mode.
+Since dp-alt mode is 2-lane setup, stream 1 consumes 63 slots with dsc needed.
+Then hook up a second 4k60 to the dock.
+stream 2 connected with 65 slot initialized by default without dsc. dsc
+pre validate will not jointly optimize stream 2 with stream 1 before
+crtc 2 added into the dc_state. That leads to stream 2 not getting dsc
+optimization, and trigger atomic_check failure all the time, as 65 > 63
+limit.
+
+After getting all new crtcs added into the state, stream_count in
+dc_state correctly reflect that in drm_atomic_state which comes up with
+correct dsc decision.
+
+Fixes: 71be4b16d39a ("drm/amd/display: dsc validate fail not pass to atomic check")
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Reviewed-by: Roman Li <Roman.Li@amd.com>
+Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
+Tested-by: Mark Broadworth <mark.broadworth@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -9408,10 +9408,6 @@ static int amdgpu_dm_atomic_check(struct
+ }
+ }
+ }
+- if (!pre_validate_dsc(state, &dm_state, vars)) {
+- ret = -EINVAL;
+- goto fail;
+- }
+ }
+ #endif
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+@@ -9545,6 +9541,15 @@ static int amdgpu_dm_atomic_check(struct
+ }
+ }
+
++#if defined(CONFIG_DRM_AMD_DC_DCN)
++ if (dc_resource_is_dsc_encoding_supported(dc)) {
++ if (!pre_validate_dsc(state, &dm_state, vars)) {
++ ret = -EINVAL;
++ goto fail;
++ }
++ }
++#endif
++
+ /* Run this here since we want to validate the streams we created */
+ ret = drm_atomic_helper_check_planes(dev, state);
+ if (ret) {
--- /dev/null
+From 5ff32b52995155f91de582124485d0f0f8881363 Mon Sep 17 00:00:00 2001
+From: Martin Leung <Martin.Leung@amd.com>
+Date: Tue, 27 Sep 2022 18:13:38 -0400
+Subject: drm/amd/display: zeromem mypipe heap struct before using it
+
+From: Martin Leung <Martin.Leung@amd.com>
+
+commit 5ff32b52995155f91de582124485d0f0f8881363 upstream.
+
+[Why & How]
+bug was caused when moving variable from stack to
+heap because it was reusable and garbage was left
+over, so we need to zero mem
+
+Fixes: 7acc487ab57e ("drm/amd/display: reduce stack size in dcn32 dml (v2)")
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
+Signed-off-by: Martin Leung <Martin.Leung@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+@@ -733,6 +733,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleep
+ mode_lib->vba.FCLKChangeLatency, v->UrgentLatency,
+ mode_lib->vba.SREnterPlusExitTime);
+
++ memset(&v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe, 0, sizeof(DmlPipe));
++
+ v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.Dppclk = mode_lib->vba.DPPCLK[k];
+ v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.Dispclk = mode_lib->vba.DISPCLK;
+ v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.PixelClock = mode_lib->vba.PixelClock[k];
--- /dev/null
+From 21a550de5faf9f54013334c9a6a7643b8fd80b36 Mon Sep 17 00:00:00 2001
+From: Ruili Ji <ruiliji2@amd.com>
+Date: Mon, 3 Oct 2022 17:39:45 +0800
+Subject: drm/amdgpu: Enable F32_WPTR_POLL_ENABLE in mqd
+
+From: Ruili Ji <ruiliji2@amd.com>
+
+commit 21a550de5faf9f54013334c9a6a7643b8fd80b36 upstream.
+
+This patch is to fix the SDMA user queue doorbell missing issue on
+SDMA 6.0. F32_WPTR_POLL_ENABLE has to be set if doorbell mode is
+used. Otherwise ringing SDMA user queue doorbell can't wake up
+system from gfxoff.
+
+Signed-off-by: Ruili Ji <ruiliji2@amd.com>
+Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 6.0.x
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 3 ++-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 3 ++-
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+@@ -910,7 +910,8 @@ static int sdma_v6_0_mqd_init(struct amd
+ m->sdmax_rlcx_rb_cntl =
+ order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
+ 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
+- 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
++ 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
++ 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
+
+ m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
+ m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c
+@@ -375,7 +375,8 @@ static void update_mqd_sdma(struct mqd_m
+ << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
+ q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT |
+ 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
+- 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
++ 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
++ 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
+
+ m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
+ m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
--- /dev/null
+From e626d9b9c6e038a6918aad1b5affd38f6b9deaed Mon Sep 17 00:00:00 2001
+From: Sonny Jiang <sonny.jiang@amd.com>
+Date: Fri, 30 Sep 2022 16:23:32 -0400
+Subject: drm/amdgpu: Enable VCN PG on GC11_0_1
+
+From: Sonny Jiang <sonny.jiang@amd.com>
+
+commit e626d9b9c6e038a6918aad1b5affd38f6b9deaed upstream.
+
+Enable VCN PG on GC11_0_1
+
+Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
+Reviewed-by: James Zhu <James.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # 6.0.x
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
+@@ -625,6 +625,7 @@ static int soc21_common_early_init(void
+ AMD_CG_SUPPORT_JPEG_MGCG;
+ adev->pg_flags =
+ AMD_PG_SUPPORT_GFX_PG |
++ AMD_PG_SUPPORT_VCN |
+ AMD_PG_SUPPORT_VCN_DPG |
+ AMD_PG_SUPPORT_JPEG;
+ adev->external_rev_id = adev->rev_id + 0x1;
drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch
drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch
drm-i915-fix-display-problems-after-resume.patch
+drm-amd-display-fix-watermark-calculation.patch
+drm-amd-display-update-pmfw-z-state-interface-for-dcn314.patch
+drm-amd-display-zeromem-mypipe-heap-struct-before-using-it.patch
+drm-amd-display-validate-dsc-after-enable-all-new-crtcs.patch
+drm-amd-display-enable-dpia-support-for-dcn314.patch
+drm-amd-display-enable-2-to-1-odm-policy-if-supported.patch
+drm-amd-display-fix-vblank-refcount-in-vrr-transition.patch
+drm-amd-display-add-hubp-surface-flip-interrupt-handler.patch
+drm-amd-display-explicitly-disable-psr_feature_enable-appropriately.patch
+drm-amdgpu-enable-vcn-pg-on-gc11_0_1.patch
+drm-amdgpu-enable-f32_wptr_poll_enable-in-mqd.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
