-From: George Moussalem <george.moussalem@outlook.com>
-Date: Fri, 28 Feb 2025 09:11:39 +0400
-Subject: [PATCH v9 6/6] arm64: dts: qcom: ipq5018: Add tsens node
-
+From 450a80623e3b8bb5dae59e0d56046fc3d0a88f3b Mon Sep 17 00:00:00 2001
From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
+Date: Thu, 12 Jun 2025 10:46:14 +0400
+Subject: arm64: dts: qcom: ipq5018: Add tsens node
IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use.
There is no RPM, so tsens has to be manually enabled. Adding the tsens
-and nvmem nodes and adding 4 thermal sensors (zones). With the
-critical temperature being 120'C and action is to reboot.
+and nvmem nodes and adding 4 thermal sensors (zones). The critical trip
+temperature is set to 120'C with an action to reboot.
+
+In addition, adding a cooling device to the CPU thermal zone which uses
+CPU frequency scaling.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+[bjorn: Added tsens-v1 fallback compatible, per binding]
+Link: https://lore.kernel.org/r/20250612-ipq5018-tsens-v13-2-a210f3683240@outlook.com
---
- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 169 ++++++++++++++++++++++++++
- 1 file changed, 169 insertions(+)
+ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 178 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 178 insertions(+)
+
+(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -182,6 +182,117 @@
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+ #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
++#include <dt-bindings/thermal/thermal.h>
+
+ / {
+ interrupt-parent = <&intc>;
+@@ -39,6 +40,7 @@
+ next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
++ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+@@ -49,6 +51,7 @@
+ next-level-cache = <&l2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
++ #cooling-cells = <2>;
+ };
+
+ l2_0: l2-cache {
+@@ -182,6 +185,117 @@
status = "disabled";
};
+ };
+
+ tsens: thermal-sensor@4a9000 {
-+ compatible = "qcom,ipq5018-tsens";
-+ reg = <0x004a9000 0x1000>, /* TM */
-+ <0x004a8000 0x1000>; /* SROT */
++ compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
++ reg = <0x004a9000 0x1000>,
++ <0x004a8000 0x1000>;
+
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base1>,
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5018-tlmm";
reg = <0x01000000 0x300000>;
-@@ -630,6 +741,64 @@
+@@ -630,6 +744,70 @@
};
};
};
+
+ thermal-zones {
+ cpu-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
+ thermal-sensors = <&tsens 2>;
+
+ trips {
+ cpu-critical {
+ temperature = <120000>;
-+ hysteresis = <2>;
++ hysteresis = <1000>;
+ type = "critical";
+ };
++
++ cpu_alert: cpu-passive {
++ temperature = <100000>;
++ hysteresis = <1000>;
++ type = "passive";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&cpu_alert>;
++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++ };
+ };
+ };
+
+ gephy-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
+ thermal-sensors = <&tsens 4>;
+
+ trips {
+ gephy-critical {
+ temperature = <120000>;
-+ hysteresis = <2>;
++ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ top-glue-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
+ thermal-sensors = <&tsens 3>;
+
+ trips {
-+ top_glue-critical {
++ top-glue-critical {
+ temperature = <120000>;
-+ hysteresis = <2>;
++ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ ubi32-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
+ thermal-sensors = <&tsens 1>;
+
+ trips {
+ ubi32-critical {
+ temperature = <120000>;
-+ hysteresis = <2>;
++ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
--- /dev/null
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+Date: Mon, 18 Aug 2025 15:33:47 +0400
+Subject: [PATCH 2/2] arm64: dts: qcom: ipq5018: Remove tsens v1 fallback
+ compatible
+Precedence: bulk
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+In-Reply-To: <20250818-ipq5018-tsens-fix-v1-0-0f08cf09182d@outlook.com>
+To: Amit Kucheria <amitk@kernel.org>,
+ Thara Gopinath <thara.gopinath@gmail.com>,
+ "Rafael J. Wysocki" <rafael@kernel.org>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>, Zhang Rui <rui.zhang@intel.com>,
+ Lukasz Luba <lukasz.luba@arm.com>, Rob Herring <robh@kernel.org>,
+ Krzysztof Kozlowski <krzk+dt@kernel.org>,
+ Conor Dooley <conor+dt@kernel.org>,
+ Sricharan Ramabadhran <quic_srichara@quicinc.com>,
+ Bjorn Andersson <andersson@kernel.org>,
+ Konrad Dybcio <konradybcio@kernel.org>
+Cc: linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org,
+ devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
+ George Moussalem <george.moussalem@outlook.com>,
+ Dmitry Baryshkov <lumag@kernel.org>,
+ Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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+From: George Moussalem <george.moussalem@outlook.com>
+
+From: George Moussalem <george.moussalem@outlook.com>
+
+Remove qcom,tsens-v1 as fallback compatible since this IP has no RPM
+and, as such, must use its own init routine available in the driver.
+
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
+Signed-off-by: George Moussalem <george.moussalem@outlook.com>
+---
+ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+@@ -340,7 +340,7 @@
+ };
+
+ tsens: thermal-sensor@4a9000 {
+- compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
++ compatible = "qcom,ipq5018-tsens";
+ reg = <0x004a9000 0x1000>,
+ <0x004a8000 0x1000>;
+
projects / thirdparty / openwrt.git / commitdiff
