RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vaadd.vv to the
vaadd.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

  #define DEF_VX_MERGE_0(T)                                      \
  void                                                           \
  test_vx_merge_##T##_case_0 (T * restrict out, T * restrict in, \
                              T x,  unsigned n)                  \
  {                                                              \
    for (unsigned i = 0; i < n; i++)                             \
      {                                                          \
        if (i % 2 == 0)                                          \
          out[i] = x;                                            \
        else                                                     \
          out[i] = in[i];                                        \
      }                                                          \
  }

  DEF_VX_MERGE_0(int32_t)

Before this patch:
  11   │     beq a3,zero,.L8
  12   │     vsetvli a5,zero,e32,m1,ta,ma
  13   │     vmv.v.x v2,a2
  ...
  16   │ .L3:
  17   │     vsetvli a5,a3,e32,m1,ta,ma
  ...
  22   │     vmerge.vvm v1,v1,v2,v0
  ...
  25   │     bne a3,zero,.L3

After this patch:
  11   │     beq a3,zero,.L8
  ...
  14   │ .L3:
  15   │     vsetvli a5,a3,e32,m1,ta,ma
  ...
  20   │     vmerge.vxm v1,v1,a2,v0
  ...
  23   │     bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*merge_vx_<mode>): Add new
	pattern to combine the vmerge.vxm.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 65319960bc015b2e5d93821da7fcaa73c592c88f..4559d25ff732cc443097bbcc59fd573f5e1fde4d 100644 (file)
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1782,6 +1782,24 @@
   }
   [(set_attr "type" "vaalu")])
 
+(define_insn_and_split "*merge_vx_<mode>"
+ [(set (match_operand:V_VLSI 0 "register_operand")
+   (if_then_else:V_VLSI
+    (match_operand:<VM>      3 "vector_mask_operand")
+    (vec_duplicate:V_VLSI
+     (match_operand:<VEL>    2 "reg_or_int_operand"))
+    (match_operand:V_VLSI    1 "register_operand")))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    insn_code icode = code_for_pred_merge_scalar (<MODE>mode);
+    riscv_vector::emit_vlmax_insn (icode, riscv_vector::MERGE_OP, operands);
+    DONE;
+  }
+  [(set_attr "type" "vimerge")])
+
 ;; =============================================================================
 ;; Combine vec_duplicate + op.vv to op.vf
 ;; Include