LoongArch: Clarify 3 MSG interrupt features

LoongArch's MSG interrupt features are used across multiple subsystems.
Clarify these features to avoid misuse, existing users will be adjusted
if necessary.

MSGINT: Infrastructure, means the CPU core supports message interupts.
Indicated by CPUCFG1.MSGINT.

AVECINT: AVEC interrupt controller based on MSGINT, means the CPU chip
supports direct message interrupts. Indicated by IOCSR.FEATURES.DMSI.

REDIRECTINT: REDIRECT interrupt controller based on MSGINT and AVECINT,
means the CPU chip supports redirect message interrupts. Indicated by
IOCSR.FEATURES.RMSI.

For example:
Loongson-3A5000/3C5000 doesn't support MSGINT/AVECINT/REDIRECTINT;
Loongson-3A6000 supports MSGINT but doesn't support AVECINT/REDIRECTINT;
Loongson-3C6000 supports MSGINT/AVECINT/REDIRECTINT.

Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/include/asm/cpu-features.h
index fc83bb32f9f09d1ea942a80d21f7854bab2a9ccb..bd5f0457ad21d89ab902fb1971cc8b41b1d340ad 100644 (file)
--- a/arch/loongarch/include/asm/cpu-features.h
+++ b/arch/loongarch/include/asm/cpu-features.h
@@ -67,6 +67,8 @@
 #define cpu_has_hypervisor     cpu_opt(LOONGARCH_CPU_HYPERVISOR)
 #define cpu_has_ptw            cpu_opt(LOONGARCH_CPU_PTW)
 #define cpu_has_lspw           cpu_opt(LOONGARCH_CPU_LSPW)
+#define cpu_has_msgint         cpu_opt(LOONGARCH_CPU_MSGINT)
 #define cpu_has_avecint                cpu_opt(LOONGARCH_CPU_AVECINT)
+#define cpu_has_redirectint    cpu_opt(LOONGARCH_CPU_REDIRECTINT)
 
 #endif /* __ASM_CPU_FEATURES_H */

diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h
index dfb982fe870192384565c6712d15bae6a45e9a9a..d4cd4041bee7ea3148c5202ea963ba0ea1f89af5 100644 (file)
--- a/arch/loongarch/include/asm/cpu.h
+++ b/arch/loongarch/include/asm/cpu.h
@@ -101,7 +101,9 @@ enum cpu_type_enum {
 #define CPU_FEATURE_HYPERVISOR         26      /* CPU has hypervisor (running in VM) */
 #define CPU_FEATURE_PTW                        27      /* CPU has hardware page table walker */
 #define CPU_FEATURE_LSPW               28      /* CPU has LSPW (lddir/ldpte instructions) */
-#define CPU_FEATURE_AVECINT            29      /* CPU has AVEC interrupt */
+#define CPU_FEATURE_MSGINT             29      /* CPU has MSG interrupt */
+#define CPU_FEATURE_AVECINT            30      /* CPU has AVEC interrupt */
+#define CPU_FEATURE_REDIRECTINT                31      /* CPU has interrupt remapping */
 
 #define LOONGARCH_CPU_CPUCFG           BIT_ULL(CPU_FEATURE_CPUCFG)
 #define LOONGARCH_CPU_LAM              BIT_ULL(CPU_FEATURE_LAM)
@@ -132,6 +134,8 @@ enum cpu_type_enum {
 #define LOONGARCH_CPU_HYPERVISOR       BIT_ULL(CPU_FEATURE_HYPERVISOR)
 #define LOONGARCH_CPU_PTW              BIT_ULL(CPU_FEATURE_PTW)
 #define LOONGARCH_CPU_LSPW             BIT_ULL(CPU_FEATURE_LSPW)
+#define LOONGARCH_CPU_MSGINT           BIT_ULL(CPU_FEATURE_MSGINT)
 #define LOONGARCH_CPU_AVECINT          BIT_ULL(CPU_FEATURE_AVECINT)
+#define LOONGARCH_CPU_REDIRECTINT      BIT_ULL(CPU_FEATURE_REDIRECTINT)
 
 #endif /* _ASM_CPU_H */

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 09dfd7eb406e7e19455064d4d58138dcf9fe905f..5b36fa57015fa2f32f8a5a83006b036effa9cde5 100644 (file)
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1137,6 +1137,7 @@
 #define  IOCSRF_FLATMODE               BIT_ULL(10)
 #define  IOCSRF_VM                     BIT_ULL(11)
 #define  IOCSRF_AVEC                   BIT_ULL(15)
+#define  IOCSRF_REDIRECT               BIT_ULL(16)
 
 #define LOONGARCH_IOCSR_VENDOR         0x10
 

diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
index cbfce2872d7165fc17a2c4b7e46fa6d8a37453e8..6f943d1391ff758fe6ff62b59b8cd70707cf9078 100644 (file)
--- a/arch/loongarch/kernel/cpu-probe.c
+++ b/arch/loongarch/kernel/cpu-probe.c
@@ -157,6 +157,8 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
                c->options |= LOONGARCH_CPU_TLB;
        if (config & CPUCFG1_IOCSR)
                c->options |= LOONGARCH_CPU_IOCSR;
+       if (config & CPUCFG1_MSGINT)
+               c->options |= LOONGARCH_CPU_MSGINT;
        if (config & CPUCFG1_UAL) {
                c->options |= LOONGARCH_CPU_UAL;
                elf_hwcap |= HWCAP_LOONGARCH_UAL;
@@ -331,6 +333,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int
                c->options |= LOONGARCH_CPU_EIODECODE;
        if (config & IOCSRF_AVEC)
                c->options |= LOONGARCH_CPU_AVECINT;
+       if (config & IOCSRF_REDIRECT)
+               c->options |= LOONGARCH_CPU_REDIRECTINT;
        if (config & IOCSRF_VM)
                c->options |= LOONGARCH_CPU_HYPERVISOR;
 }