arm64: dts: renesas: r9a07g054: Add GPT support

Add GPT support by adding pwm node to RZ/V2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424054050.28310-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 01f59914dd09975f5922817f2882896797c614ca..669eca74da0a6511a2a6d6a1234ed18ad879629a 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -244,6 +244,121 @@
                        status = "disabled";
                };
 
+               gpt: pwm@10048000 {
+                       compatible = "renesas,r9a07g054-gpt",
+                                    "renesas,rzg2l-gpt";
+                       reg = <0 0x10048000 0 0x800>;
+                       #pwm-cells = <3>;
+                       interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 222 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 259 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0",
+                                         "cmpe0", "cmpf0", "adtrga0", "adtrgb0",
+                                         "ovf0", "unf0",
+                                         "ccmpa1", "ccmpb1", "cmpc1", "cmpd1",
+                                         "cmpe1", "cmpf1", "adtrga1", "adtrgb1",
+                                         "ovf1", "unf1",
+                                         "ccmpa2", "ccmpb2", "cmpc2", "cmpd2",
+                                         "cmpe2", "cmpf2", "adtrga2", "adtrgb2",
+                                         "ovf2", "unf2",
+                                         "ccmpa3", "ccmpb3", "cmpc3", "cmpd3",
+                                         "cmpe3", "cmpf3", "adtrga3", "adtrgb3",
+                                         "ovf3", "unf3",
+                                         "ccmpa4", "ccmpb4", "cmpc4", "cmpd4",
+                                         "cmpe4", "cmpf4", "adtrga4", "adtrgb4",
+                                         "ovf4", "unf4",
+                                         "ccmpa5", "ccmpb5", "cmpc5", "cmpd5",
+                                         "cmpe5", "cmpf5", "adtrga5", "adtrgb5",
+                                         "ovf5", "unf5",
+                                         "ccmpa6", "ccmpb6", "cmpc6", "cmpd6",
+                                         "cmpe6", "cmpf6", "adtrga6", "adtrgb6",
+                                         "ovf6", "unf6",
+                                         "ccmpa7", "ccmpb7", "cmpc7", "cmpd7",
+                                         "cmpe7", "cmpf7", "adtrga7", "adtrgb7",
+                                         "ovf7", "unf7";
+                       clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
+                       resets = <&cpg R9A07G054_GPT_RST_C>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
                ssi0: ssi@10049c00 {
                        compatible = "renesas,r9a07g054-ssi",
                                     "renesas,rz-ssi";