--- /dev/null
+From 1a4039bdcf972a7d2e469bb1a5ea616c4c2216fb Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Thu, 31 Aug 2023 12:30:23 +0200
+Subject: Revert "MIPS: Alchemy: fix dbdma2"
+
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+This reverts commit a16419bae292d768546bcd6e0bfbf8a722756fee which is
+commit 2d645604f69f3a772d58ead702f9a8e84ab2b342 upstream.
+
+It breaks the build, so should be dropped.
+
+Reported-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/5b30ff73-46cb-1d1e-3823-f175dbfbd91b@roeck-us.net
+Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Cc: Sasha Levin <sashal@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/mips/alchemy/common/dbdma.c | 27 ++++++++++++---------------
+ 1 file changed, 12 insertions(+), 15 deletions(-)
+
+--- a/arch/mips/alchemy/common/dbdma.c
++++ b/arch/mips/alchemy/common/dbdma.c
+@@ -30,7 +30,6 @@
+ *
+ */
+
+-#include <linux/dma-map-ops.h> /* for dma_default_coherent */
+ #include <linux/init.h>
+ #include <linux/kernel.h>
+ #include <linux/slab.h>
+@@ -624,18 +623,17 @@ u32 au1xxx_dbdma_put_source(u32 chanid,
+ dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
+
+ /*
+- * There is an erratum on certain Au1200/Au1550 revisions that could
+- * result in "stale" data being DMA'ed. It has to do with the snoop
+- * logic on the cache eviction buffer. dma_default_coherent is set
+- * to false on these parts.
++ * There is an errata on the Au1200/Au1550 parts that could result
++ * in "stale" data being DMA'ed. It has to do with the snoop logic on
++ * the cache eviction buffer. DMA_NONCOHERENT is on by default for
++ * these parts. If it is fixed in the future, these dma_cache_inv will
++ * just be nothing more than empty macros. See io.h.
+ */
+- if (!dma_default_coherent)
+- dma_cache_wback_inv(KSEG0ADDR(buf), nbytes);
++ dma_cache_wback_inv((unsigned long)buf, nbytes);
+ dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
+ wmb(); /* drain writebuffer */
+ dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
+ ctp->chan_ptr->ddma_dbell = 0;
+- wmb(); /* force doorbell write out to dma engine */
+
+ /* Get next descriptor pointer. */
+ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
+@@ -687,18 +685,17 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dm
+ dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
+ #endif
+ /*
+- * There is an erratum on certain Au1200/Au1550 revisions that could
+- * result in "stale" data being DMA'ed. It has to do with the snoop
+- * logic on the cache eviction buffer. dma_default_coherent is set
+- * to false on these parts.
++ * There is an errata on the Au1200/Au1550 parts that could result in
++ * "stale" data being DMA'ed. It has to do with the snoop logic on the
++ * cache eviction buffer. DMA_NONCOHERENT is on by default for these
++ * parts. If it is fixed in the future, these dma_cache_inv will just
++ * be nothing more than empty macros. See io.h.
+ */
+- if (!dma_default_coherent)
+- dma_cache_inv(KSEG0ADDR(buf), nbytes);
++ dma_cache_inv((unsigned long)buf, nbytes);
+ dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
+ wmb(); /* drain writebuffer */
+ dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
+ ctp->chan_ptr->ddma_dbell = 0;
+- wmb(); /* force doorbell write out to dma engine */
+
+ /* Get next descriptor pointer. */
+ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));