gcc:

2013-08-14  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/57949
	* doc/invoke.texi: Add documentation of mcompat-align-parm
	option.
	* config/rs6000/rs6000.opt: Add mcompat-align-parm option.
	* config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX
	and Linux, correct BLKmode alignment when 128-bit alignment is
	required and compatibility flag is not set.
	(rs6000_gimplify_va_arg): For AIX and Linux, honor specified
	alignment for zero-size arguments when compatibility flag is not
	set.

gcc/testsuite:

2013-08-14  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/57949
	* gcc.target/powerpc/pr57949-1.c: New.
	* gcc.target/powerpc/pr57949-2.c: New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@201750 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c7f229bb9541ab1787d60bd23a002bcbfe3c411a..1040af8b0464940ad771517be74e8209d02af607 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2013-08-14  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+       PR target/57949
+       * doc/invoke.texi: Add documentation of mcompat-align-parm
+       option.
+       * config/rs6000/rs6000.opt: Add mcompat-align-parm option.
+       * config/rs6000/rs6000.c (rs6000_function_arg_boundary): For AIX
+       and Linux, correct BLKmode alignment when 128-bit alignment is
+       required and compatibility flag is not set.
+       (rs6000_gimplify_va_arg): For AIX and Linux, honor specified
+       alignment for zero-size arguments when compatibility flag is not
+       set.
+
 2013-08-14  Jakub Jelinek  <jakub@redhat.com>
 
        PR tree-optimization/58145

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 30cd6961f7b7e5749f09d6ab269998768913e1a3..c1d4b99b81dcb74b933adf5bc9a959f531a93e39 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -8339,8 +8339,8 @@ rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)
           || (type && TREE_CODE (type) == VECTOR_TYPE
               && int_size_in_bytes (type) >= 16))
     return 128;
-  else if (TARGET_MACHO
-          && rs6000_darwin64_abi
+  else if (((TARGET_MACHO && rs6000_darwin64_abi)
+            || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
           && mode == BLKmode
           && type && TYPE_ALIGN (type) > 64)
     return 128;
@@ -9888,8 +9888,9 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
      We don't need to check for pass-by-reference because of the test above.
      We can return a simplifed answer, since we know there's no offset to add.  */
 
-  if (TARGET_MACHO
-      && rs6000_darwin64_abi 
+  if (((TARGET_MACHO
+        && rs6000_darwin64_abi)
+       || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
       && integer_zerop (TYPE_SIZE (type)))
     {
       unsigned HOST_WIDE_INT align, boundary;

diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index f36e47580314ceafc6f95bc059583625a648598f..cd83cb2d206db72bbce0c593686ce4bebb8895c6 100644 (file)
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -546,3 +546,7 @@ Use ISA 2.07 transactional memory (HTM) instructions
 mquad-memory
 Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
 Generate the quad word memory instructions (lq/stq/lqarx/stqcx).
+
+mcompat-align-parm
+Target Report Var(rs6000_compat_align_parm) Init(0) Save
+Generate aggregate parameter passing code with at most 64-bit alignment.

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 66d7cc5d2eca8d2780c9369bd30df453cb799726..f6a4ec4d40db341b47d99171386cb007300182f9 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -871,7 +871,8 @@ See RS/6000 and PowerPC Options.
 -msave-toc-indirect -mno-save-toc-indirect @gol
 -mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol
 -mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol
--mquad-memory -mno-quad-memory}
+-mquad-memory -mno-quad-memory @gol
+-mcompat-align-parm -mno-compat-align-parm}
 
 @emph{RX Options}
 @gccoptlist{-m64bit-doubles  -m32bit-doubles  -fpu  -nofpu@gol
@@ -18417,6 +18418,22 @@ stack location in the function prologue if the function calls through
 a pointer on AIX and 64-bit Linux systems.  If the TOC value is not
 saved in the prologue, it is saved just before the call through the
 pointer.  The @option{-mno-save-toc-indirect} option is the default.
+
+@item -mcompat-align-parm
+@itemx -mno-compat-align-parm
+@opindex mcompat-align-parm
+Generate (do not generate) code to pass structure parameters with a
+maximum alignment of 64 bits, for compatibility with older versions
+of GCC.
+
+Older versions of GCC (prior to 4.9.0) incorrectly did not align a
+structure parameter on a 128-bit boundary when that structure contained
+a member requiring 128-bit alignment.  This is corrected in more
+recent versions of GCC.  This option may be used to generate code
+that is compatible with functions compiled with older versions of
+GCC.
+
+The @option{-mno-compat-align-parm} option is the default.
 @end table
 
 @node RX Options

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c56c2604343f21e25d006c30364e74e9672bc74b..72fcd6087ce2873d3d8a350ef128d7ffa67c3c67 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2013-08-14  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+       PR target/57949
+       * gcc.target/powerpc/pr57949-1.c: New.
+       * gcc.target/powerpc/pr57949-2.c: New.
+
 2013-08-14  Jakub Jelinek  <jakub@redhat.com>
 
        PR tree-optimization/58145

diff --git a/gcc/testsuite/gcc.target/powerpc/pr57949-1.c b/gcc/testsuite/gcc.target/powerpc/pr57949-1.c
new file mode 100644 (file)
index 0000000..253b2d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr57949-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power7" } */
+
+/* Verify that vs is 16-byte aligned in the absence of -mcompat-align-parm.  */
+
+typedef float v4sf __attribute__ ((vector_size (16)));
+struct s { long m; v4sf v; };
+long n;
+v4sf ve;
+
+void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6,
+             long d7, long d8, long d9, struct s vs) {
+  n = vs.m;
+  ve = vs.v;
+}
+
+/* { dg-final { scan-assembler "li \.\*,144" } } */
+/* { dg-final { scan-assembler "ld \.\*,128\\(1\\)" } } */

diff --git a/gcc/testsuite/gcc.target/powerpc/pr57949-2.c b/gcc/testsuite/gcc.target/powerpc/pr57949-2.c
new file mode 100644 (file)
index 0000000..aa6a0d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr57949-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power7 -mcompat-align-parm" } */
+
+/* Verify that vs is not 16-byte aligned with -mcompat-align-parm.  */
+
+typedef float v4sf __attribute__ ((vector_size (16)));
+struct s { long m; v4sf v; };
+long n;
+v4sf ve;
+
+void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6,
+             long d7, long d8, long d9, struct s vs) {
+  n = vs.m;
+  ve = vs.v;
+}
+
+/* { dg-final { scan-assembler "ld .\*,136\\(1\\)" } } */
+/* { dg-final { scan-assembler "ld .\*,120\\(1\\)" } } */