aarch64: small fix for mrs id_aa64pfr0_el1

The flag for half-precision is 0x1 not 0x11. Probably harmless and gets caught
by the default. Add a comment for the bottom 6 nibbles.

diff --git a/VEX/priv/guest_arm64_helpers.c b/VEX/priv/guest_arm64_helpers.c
index 938df2bd484e0a63ce6bee9e9ed5f6329a86350a..0db067d203ab8a17f09e7dbe80414f7f8e04c075 100644 (file)
--- a/VEX/priv/guest_arm64_helpers.c
+++ b/VEX/priv/guest_arm64_helpers.c
@@ -842,13 +842,19 @@ ULong arm64g_dirtyhelper_MRS_ID_AA64PFR0_EL1 ( void )
    ULong w = 0x5555555555555555ULL; /* overwritten */
    __asm__ __volatile__("mrs %0, id_aa64pfr0_el1" : "=r"(w));
 
+   // The control word uses the following nibbles (as seen on RPi)
+   // unsupported unless indicated
+   // 0 to 3 - EL0 to EL3 exception level handling
+   // 4 - FP includes half-precision (partial support)
+   // 5 - AdvSIMD also includes haf-precision
+
    /* If half-precision fp is present we fall back to normal
       half precision implementation because of missing support in the emulation.
       If no AdvSIMD and FP are implemented, we preserve the value */
    w = (w >> 16);
    w &= 0xff;
    switch(w) {
-     case 0x11:
+     case 0x01:
        w = 0x0;
        break;
      case 0xff: