The SoC has three SPI controllers, not four.
Remove the extra define of an SPI IRQ.
Fixes: 06908a84f036 "hw/arm/fsl-imx8mp: Add SPI controllers"
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <
20250318205709.28862-4-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
FSL_IMX8MP_ECSPI1_IRQ = 31,
FSL_IMX8MP_ECSPI2_IRQ = 32,
FSL_IMX8MP_ECSPI3_IRQ = 33,
- FSL_IMX8MP_ECSPI4_IRQ = 34,
FSL_IMX8MP_I2C1_IRQ = 35,
FSL_IMX8MP_I2C2_IRQ = 36,