Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull kvm updates from Paolo Bonzini:
 "This excludes the bulk of the x86 changes, which I will send
  separately. They have two not complex but relatively unusual conflicts
  so I will wait for other dust to settle.

  guest_memfd:

   - Add support for host userspace mapping of guest_memfd-backed memory
     for VM types that do NOT use support KVM_MEMORY_ATTRIBUTE_PRIVATE
     (which isn't precisely the same thing as CoCo VMs, since x86's
     SEV-MEM and SEV-ES have no way to detect private vs. shared).

     This lays the groundwork for removal of guest memory from the
     kernel direct map, as well as for limited mmap() for
     guest_memfd-backed memory.

     For more information see:
       - commit a6ad54137af9 ("Merge branch 'guest-memfd-mmap' into HEAD")
       - guest_memfd in Firecracker:
           https://github.com/firecracker-microvm/firecracker/tree/feature/secret-hiding
       - direct map removal:
           https://lore.kernel.org/all/20250221160728.1584559-1-roypat@amazon.co.uk/
       - mmap support:
           https://lore.kernel.org/all/20250328153133.3504118-1-tabba@google.com/

  ARM:

   - Add support for FF-A 1.2 as the secure memory conduit for pKVM,
     allowing more registers to be used as part of the message payload.

   - Change the way pKVM allocates its VM handles, making sure that the
     privileged hypervisor is never tricked into using uninitialised
     data.

   - Speed up MMIO range registration by avoiding unnecessary RCU
     synchronisation, which results in VMs starting much quicker.

   - Add the dump of the instruction stream when panic-ing in the EL2
     payload, just like the rest of the kernel has always done. This
     will hopefully help debugging non-VHE setups.

   - Add 52bit PA support to the stage-1 page-table walker, and make use
     of it to populate the fault level reported to the guest on failing
     to translate a stage-1 walk.

   - Add NV support to the GICv3-on-GICv5 emulation code, ensuring
     feature parity for guests, irrespective of the host platform.

   - Fix some really ugly architecture problems when dealing with debug
     in a nested VM. This has some bad performance impacts, but is at
     least correct.

   - Add enough infrastructure to be able to disable EL2 features and
     give effective values to the EL2 control registers. This then
     allows a bunch of features to be turned off, which helps cross-host
     migration.

   - Large rework of the selftest infrastructure to allow most tests to
     transparently run at EL2. This is the first step towards enabling
     NV testing.

   - Various fixes and improvements all over the map, including one BE
     fix, just in time for the removal of the feature.

  LoongArch:

   - Detect page table walk feature on new hardware

   - Add sign extension with kernel MMIO/IOCSR emulation

   - Improve in-kernel IPI emulation

   - Improve in-kernel PCH-PIC emulation

   - Move kvm_iocsr tracepoint out of generic code

  RISC-V:

   - Added SBI FWFT extension for Guest/VM with misaligned delegation
     and pointer masking PMLEN features

   - Added ONE_REG interface for SBI FWFT extension

   - Added Zicbop and bfloat16 extensions for Guest/VM

   - Enabled more common KVM selftests for RISC-V

   - Added SBI v3.0 PMU enhancements in KVM and perf driver

  s390:

   - Improve interrupt cpu for wakeup, in particular the heuristic to
     decide which vCPU to deliver a floating interrupt to.

   - Clear the PTE when discarding a swapped page because of CMMA; this
     bug was introduced in 6.16 when refactoring gmap code.

  x86 selftests:

   - Add #DE coverage in the fastops test (the only exception that's
     guest- triggerable in fastop-emulated instructions).

   - Fix PMU selftests errors encountered on Granite Rapids (GNR),
     Sierra Forest (SRF) and Clearwater Forest (CWF).

   - Minor cleanups and improvements

  x86 (guest side):

   - For the legacy PCI hole (memory between TOLUD and 4GiB) to UC when
     overriding guest MTRR for TDX/SNP to fix an issue where ACPI
     auto-mapping could map devices as WB and prevent the device drivers
     from mapping their devices with UC/UC-.

   - Make kvm_async_pf_task_wake() a local static helper and remove its
     export.

   - Use native qspinlocks when running in a VM with dedicated
     vCPU=>pCPU bindings even when PV_UNHALT is unsupported.

  Generic:

   - Remove a redundant __GFP_NOWARN from kvm_setup_async_pf() as
     __GFP_NOWARN is now included in GFP_NOWAIT.

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (178 commits)
  KVM: s390: Fix to clear PTE when discarding a swapped page
  KVM: arm64: selftests: Cover ID_AA64ISAR3_EL1 in set_id_regs
  KVM: arm64: selftests: Remove a duplicate register listing in set_id_regs
  KVM: arm64: selftests: Cope with arch silliness in EL2 selftest
  KVM: arm64: selftests: Add basic test for running in VHE EL2
  KVM: arm64: selftests: Enable EL2 by default
  KVM: arm64: selftests: Initialize HCR_EL2
  KVM: arm64: selftests: Use the vCPU attr for setting nr of PMU counters
  KVM: arm64: selftests: Use hyp timer IRQs when test runs at EL2
  KVM: arm64: selftests: Select SMCCC conduit based on current EL
  KVM: arm64: selftests: Provide helper for getting default vCPU target
  KVM: arm64: selftests: Alias EL1 registers to EL2 counterparts
  KVM: arm64: selftests: Create a VGICv3 for 'default' VMs
  KVM: arm64: selftests: Add unsanitised helpers for VGICv3 creation
  KVM: arm64: selftests: Add helper to check for VGICv3 support
  KVM: arm64: selftests: Initialize VGICv3 only once
  KVM: arm64: selftests: Provide kvm_arch_vm_post_create() in library code
  KVM: selftests: Add ex_str() to print human friendly name of exception vectors
  selftests/kvm: remove stale TODO in xapic_state_test
  KVM: selftests: Handle Intel Atom errata that leads to PMU event overcount
  ...

diff --cc arch/arm64/kernel/cpufeature.c
Simple merge

diff --cc arch/arm64/kernel/traps.c
Simple merge

diff --cc arch/arm64/kvm/handle_exit.c
Simple merge

diff --cc arch/riscv/include/uapi/asm/kvm.h
Simple merge

diff --cc drivers/perf/riscv_pmu_sbi.c
index 3fc16bbab0250bf18b5eb720f612a2a32ee68f59,0392900d828eeac9b0e5bc79cde301ab69c83a20..e255c1b069ec18d4a66aacf2f6c702c0a36083a6
--- 1/drivers/perf/riscv_pmu_sbi.c
--- 2/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@@ -339,9 -410,74 +410,74 @@@ static bool pmu_sbi_ctr_is_fw(int cidx
        if (!info)
                return false;
  
 -      return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false;
 +      return info->type == SBI_PMU_CTR_TYPE_FW;
  }
  
+ int riscv_pmu_get_event_info(u32 type, u64 config, u64 *econfig)
+ {
+       int ret = -ENOENT;
+ 
+       switch (type) {
+       case PERF_TYPE_HARDWARE:
+               if (config >= PERF_COUNT_HW_MAX)
+                       return -EINVAL;
+               ret = pmu_hw_event_map[config].event_idx;
+               break;
+       case PERF_TYPE_HW_CACHE:
+               ret = pmu_event_find_cache(config);
+               break;
+       case PERF_TYPE_RAW:
+               /*
+                * As per SBI v0.3 specification,
+                *  -- the upper 16 bits must be unused for a hardware raw event.
+                * As per SBI v2.0 specification,
+                *  -- the upper 8 bits must be unused for a hardware raw event.
+                * Bits 63:62 are used to distinguish between raw events
+                * 00 - Hardware raw event
+                * 10 - SBI firmware events
+                * 11 - Risc-V platform specific firmware event
+                */
+               switch (config >> 62) {
+               case 0:
+                       if (sbi_v3_available) {
+                       /* Return error any bits [56-63] is set  as it is not allowed by the spec */
+                               if (!(config & ~RISCV_PMU_RAW_EVENT_V2_MASK)) {
+                                       if (econfig)
+                                               *econfig = config & RISCV_PMU_RAW_EVENT_V2_MASK;
+                                       ret = RISCV_PMU_RAW_EVENT_V2_IDX;
+                               }
+                       /* Return error any bits [48-63] is set  as it is not allowed by the spec */
+                       } else if (!(config & ~RISCV_PMU_RAW_EVENT_MASK)) {
+                               if (econfig)
+                                       *econfig = config & RISCV_PMU_RAW_EVENT_MASK;
+                               ret = RISCV_PMU_RAW_EVENT_IDX;
+                       }
+                       break;
+               case 2:
+                       ret = (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16);
+                       break;
+               case 3:
+                       /*
+                        * For Risc-V platform specific firmware events
+                        * Event code - 0xFFFF
+                        * Event data - raw event encoding
+                        */
+                       ret = SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT;
+                       if (econfig)
+                               *econfig = config & RISCV_PMU_PLAT_FW_EVENT_MASK;
+                       break;
+               default:
+                       break;
+               }
+               break;
+       default:
+               break;
+       }
+ 
+       return ret;
+ }
+ EXPORT_SYMBOL_GPL(riscv_pmu_get_event_info);
+ 
  /*
   * Returns the counter width of a programmable counter and number of hardware
   * counters. As we don't support heterogeneous CPUs yet, it is okay to just