crypto: qat - introduce fuse array

Change the representation of fuses in the accelerator device
structure from a single value to an array.

This allows the structure to accommodate additional fuses that
are required for future generations of QAT hardware.

This does not introduce any functional changes.

Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
index 87c71914ae87a395fc6415cdf10cd19049d93991..98f3c12106662fdbb3a1750d1c365ad93adececd 100644 (file)
--- a/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
@@ -98,7 +98,7 @@ static struct adf_hw_device_class adf_420xx_class = {
 
 static u32 get_ae_mask(struct adf_hw_device_data *self)
 {
-       u32 me_disable = self->fuses;
+       u32 me_disable = self->fuses[ADF_FUSECTL4];
 
        return ~me_disable & ADF_420XX_ACCELENGINES_MASK;
 }

diff --git a/drivers/crypto/intel/qat/qat_420xx/adf_drv.c b/drivers/crypto/intel/qat/qat_420xx/adf_drv.c
index 9589d60fb281da06dabe843c65fd72b5ec58b7d0..8084aa0f7f4170cb7c2f056f4aaae0e9634875bd 100644 (file)
--- a/drivers/crypto/intel/qat/qat_420xx/adf_drv.c
+++ b/drivers/crypto/intel/qat/qat_420xx/adf_drv.c
@@ -79,7 +79,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
        adf_init_hw_data_420xx(accel_dev->hw_device, ent->device);
 
        pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid);
-       pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses);
+       pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]);
 
        /* Get Accelerators and Accelerators Engines masks */
        hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

diff --git a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
index 36eebda3a028196556ab49c9ae2f60b442fb6120..4eb6ef99efddee7612760a6fef813c990bbaf184 100644 (file)
--- a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
@@ -101,7 +101,7 @@ static struct adf_hw_device_class adf_4xxx_class = {
 
 static u32 get_ae_mask(struct adf_hw_device_data *self)
 {
-       u32 me_disable = self->fuses;
+       u32 me_disable = self->fuses[ADF_FUSECTL4];
 
        return ~me_disable & ADF_4XXX_ACCELENGINES_MASK;
 }

diff --git a/drivers/crypto/intel/qat/qat_4xxx/adf_drv.c b/drivers/crypto/intel/qat/qat_4xxx/adf_drv.c
index d7de1cad1335436095c58c63a025df41bdc2698a..5537a9991e4efbc18226f69823aa62108fbe63e5 100644 (file)
--- a/drivers/crypto/intel/qat/qat_4xxx/adf_drv.c
+++ b/drivers/crypto/intel/qat/qat_4xxx/adf_drv.c
@@ -81,7 +81,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
        adf_init_hw_data_4xxx(accel_dev->hw_device, ent->device);
 
        pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid);
-       pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses);
+       pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]);
 
        /* Get Accelerators and Accelerators Engines masks */
        hw_data->accel_mask = hw_data->get_accel_mask(hw_data);

diff --git a/drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c b/drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
index 201f9412c5823034a2b1a8b8cca47579c1856f41..e78f7bfd30b85a72459ac01e4e05e4e396878130 100644 (file)
--- a/drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
@@ -27,8 +27,8 @@ static struct adf_hw_device_class c3xxx_class = {
 
 static u32 get_accel_mask(struct adf_hw_device_data *self)
 {
+       u32 fuses = self->fuses[ADF_FUSECTL0];
        u32 straps = self->straps;
-       u32 fuses = self->fuses;
        u32 accel;
 
        accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET;
@@ -39,8 +39,8 @@ static u32 get_accel_mask(struct adf_hw_device_data *self)
 
 static u32 get_ae_mask(struct adf_hw_device_data *self)
 {
+       u32 fuses = self->fuses[ADF_FUSECTL0];
        u32 straps = self->straps;
-       u32 fuses = self->fuses;
        unsigned long disabled;
        u32 ae_disable;
        int accel;

diff --git a/drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c b/drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c
index caa53882fda65599c6b3fdd59d9dac7c6cdc9b21..b825b35ab4bfcf46385ae4ff8d80fd597ef32c78 100644 (file)
--- a/drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c
+++ b/drivers/crypto/intel/qat/qat_c3xxx/adf_drv.c
@@ -126,7 +126,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
        adf_init_hw_data_c3xxx(accel_dev->hw_device);
        pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid);
        pci_read_config_dword(pdev, ADF_DEVICE_FUSECTL_OFFSET,
-                             &hw_data->fuses);
+                             &hw_data->fuses[ADF_FUSECTL0]);
        pci_read_config_dword(pdev, ADF_C3XXX_SOFTSTRAP_CSR_OFFSET,
                              &hw_data->straps);
 

diff --git a/drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c b/drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
index 6b5b0cf9c7c7464cbde9178dab336dd4dfd8e7d3..32ebe09477a8dd57b9cd80481d29c2cf8900b302 100644 (file)
--- a/drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
@@ -27,8 +27,8 @@ static struct adf_hw_device_class c62x_class = {
 
 static u32 get_accel_mask(struct adf_hw_device_data *self)
 {
+       u32 fuses = self->fuses[ADF_FUSECTL0];
        u32 straps = self->straps;
-       u32 fuses = self->fuses;
        u32 accel;
 
        accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET;
@@ -39,8 +39,8 @@ static u32 get_accel_mask(struct adf_hw_device_data *self)
 
 static u32 get_ae_mask(struct adf_hw_device_data *self)
 {
+       u32 fuses = self->fuses[ADF_FUSECTL0];
        u32 straps = self->straps;
-       u32 fuses = self->fuses;
        unsigned long disabled;
        u32 ae_disable;
        int accel;

diff --git a/drivers/crypto/intel/qat/qat_c62x/adf_drv.c b/drivers/crypto/intel/qat/qat_c62x/adf_drv.c
index b7398fee19edef3e9aa41e1930b6e68d26afaa85..8a7bdec358d61c97e9ae38718ae5222f3d05602e 100644 (file)
--- a/drivers/crypto/intel/qat/qat_c62x/adf_drv.c
+++ b/drivers/crypto/intel/qat/qat_c62x/adf_drv.c
@@ -126,7 +126,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
        adf_init_hw_data_c62x(accel_dev->hw_device);
        pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid);
        pci_read_config_dword(pdev, ADF_DEVICE_FUSECTL_OFFSET,
-                             &hw_data->fuses);
+                             &hw_data->fuses[ADF_FUSECTL0]);
        pci_read_config_dword(pdev, ADF_C62X_SOFTSTRAP_CSR_OFFSET,
                              &hw_data->straps);
 
@@ -169,7 +169,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
        hw_data->accel_capabilities_mask = hw_data->get_accel_cap(accel_dev);
 
        /* Find and map all the device's BARS */
-       i = (hw_data->fuses & ADF_DEVICE_FUSECTL_MASK) ? 1 : 0;
+       i = (hw_data->fuses[ADF_FUSECTL0] & ADF_DEVICE_FUSECTL_MASK) ? 1 : 0;
        bar_mask = pci_select_bars(pdev, IORESOURCE_MEM);
        for_each_set_bit(bar_nr, &bar_mask, ADF_PCI_MAX_BARS * 2) {
                struct adf_bar *bar = &accel_pci_dev->pci_bars[i++];

diff --git a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
index 0509174d6030a0be9f2ef0285ffa4e77716dce12..dc21551153cb66788fbbdb3cfd1794ebd815c8a3 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
@@ -53,6 +53,16 @@ enum adf_accel_capabilities {
        ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
 };
 
+enum adf_fuses {
+       ADF_FUSECTL0,
+       ADF_FUSECTL1,
+       ADF_FUSECTL2,
+       ADF_FUSECTL3,
+       ADF_FUSECTL4,
+       ADF_FUSECTL5,
+       ADF_MAX_FUSES
+};
+
 struct adf_bar {
        resource_size_t base_addr;
        void __iomem *virt_addr;
@@ -345,7 +355,7 @@ struct adf_hw_device_data {
        struct qat_migdev_ops vfmig_ops;
        const char *fw_name;
        const char *fw_mmp_name;
-       u32 fuses;
+       u32 fuses[ADF_MAX_FUSES];
        u32 straps;
        u32 accel_capabilities_mask;
        u32 extended_dc_capabilities;

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c b/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
index 1f64bf49b221c2b2f43a6fcd542adaefae20ff57..2b263442c85658a871fed0957c5a7781287333b3 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
@@ -115,8 +115,8 @@ u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev)
 {
        struct adf_hw_device_data *hw_data = accel_dev->hw_device;
        struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
+       u32 fuses = hw_data->fuses[ADF_FUSECTL0];
        u32 straps = hw_data->straps;
-       u32 fuses = hw_data->fuses;
        u32 legfuses;
        u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
                           ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |

diff --git a/drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c b/drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
index c0661ff5e929278e946a381232f592e538fa371f..e48bcf1818cd1a291fabd02bd6d1b11723c638bd 100644 (file)
--- a/drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
@@ -29,7 +29,7 @@ static struct adf_hw_device_class dh895xcc_class = {
 
 static u32 get_accel_mask(struct adf_hw_device_data *self)
 {
-       u32 fuses = self->fuses;
+       u32 fuses = self->fuses[ADF_FUSECTL0];
 
        return ~fuses >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
                         ADF_DH895XCC_ACCELERATORS_MASK;
@@ -37,7 +37,7 @@ static u32 get_accel_mask(struct adf_hw_device_data *self)
 
 static u32 get_ae_mask(struct adf_hw_device_data *self)
 {
-       u32 fuses = self->fuses;
+       u32 fuses = self->fuses[ADF_FUSECTL0];
 
        return ~fuses & ADF_DH895XCC_ACCELENGINES_MASK;
 }
@@ -99,7 +99,7 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
 
 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
 {
-       int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK)
+       int sku = (self->fuses[ADF_FUSECTL0] & ADF_DH895XCC_FUSECTL_SKU_MASK)
            >> ADF_DH895XCC_FUSECTL_SKU_SHIFT;
 
        switch (sku) {

diff --git a/drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c b/drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c
index 3137fc3b5cf651a95fc4564706cad64aa9219b40..07e9d7e52861352849174ab9d53e2ba84d7ff525 100644 (file)
--- a/drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c
+++ b/drivers/crypto/intel/qat/qat_dh895xcc/adf_drv.c
@@ -126,7 +126,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
        adf_init_hw_data_dh895xcc(accel_dev->hw_device);
        pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid);
        pci_read_config_dword(pdev, ADF_DEVICE_FUSECTL_OFFSET,
-                             &hw_data->fuses);
+                             &hw_data->fuses[ADF_FUSECTL0]);
 
        /* Get Accelerators and Accelerators Engines masks */
        hw_data->accel_mask = hw_data->get_accel_mask(hw_data);