RISC-V: Add test for vec_duplicate + vwsubu.vv signed combine with GR2VR cost 0,...

Add asm dump check and run test for vec_duplicate + vwsubu.vv
combine to vwsubu.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vwsubu.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index bb29ef5638cf52043611f08f2129a0b53884a161..25bb93c8ce501b480f0066e8129a6c8f48224ebf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 1d738571b4982d2831ad32f4d81d5b115b655d97..475b74b10f0d44cbfbc1b782d660cc062eb0c29f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index dc6d1c6b1837df3105865dee5d6eafd484b13366..c7f3f2b25d4d48c6cedc3e365c38d3baa98f2328 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -33,3 +33,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vwaddu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index c6da9c7e19d282f80a1328750a8ab4575dce3b18..1c0024c273ef007abb0aef1033d73144ddcb921f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 6f1adef686c1654f3d54c1d72b38e6b592d15be2..3e88fc0623f7a2f6a9cf47ddb57bb448fe9153c3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 5ea7cc96ae6605cd97abe5240e4c30d096783d00..541b6e678b9a892ac5fa943e60e808b1ce0109df 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index f18409e76432972c97864244f60096bde84f1f5f..6d25e26d83b62e933c1793779439c060471b8079 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index b33d8269136b21f6b4354e16a0696e02c8ef95e2..f0c6624a536c88a17137f7a1d9140e9bb91b962e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 40f4142a88a8891e0990e8915cc56e3c2ee08438..8de1d6fd8070fdc79b4ff58e33f7e912abbc532a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -30,3 +30,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
+/* { dg-final { scan-assembler-not {vwsubu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c
new file mode 100644 (file)
index 0000000..f942810
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwsubu-run-1-u64.c
@@ -0,0 +1,18 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_widen.h"
+#include "vx_widen_data.h"
+
+#define WT        uint64_t
+#define NT        uint32_t
+#define NAME      sub
+#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME)
+#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME)
+
+DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, NAME)
+
+#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \
+  RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N)
+
+#include "vx_widen_vx_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
index 646edab4310d952ebdbad44ca9c3d3bc7b74b8be..290d8a4b5d4385e8f6c4e4390464679aea29c522 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
@@ -28,7 +28,8 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd,   \
 #define RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \
   RUN_VX_WIDEN_BINARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n)
 
-#define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \
-  DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add)
+#define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT)     \
+  DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) \
+  DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub)
 
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
index 48dc4d4c84966cd14215eba5b1b66eaf5bb09900..7359f0bc85d3888394163166bcb7a7a7e5a45e5a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
@@ -36,6 +36,7 @@
   DEF_BINARY_WIDEN_STRUCT_0(WT, NT, NAME)
 
 DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add)
+DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, sub)
 
 DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = {
   {
@@ -76,4 +77,43 @@ DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = {
   },
 };
 
+DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, sub)[] = {
+  {
+    /* vs2 */
+    {
+      2147483648, 2147483648, 2147483648, 2147483648,
+      2147483647, 2147483647, 2147483647, 2147483647,
+      4294967294, 4294967294, 4294967294, 4294967294,
+      4294967295, 4294967295, 4294967295, 4294967295,
+    },
+    /* rs1 */
+    2147483647,
+    /* expect */
+    {
+               1,          1,          1,          1,
+               0,          0,          0,          0,
+      2147483647, 2147483647, 2147483647, 2147483647,
+      2147483648, 2147483648, 2147483648, 2147483648,
+    },
+  },
+  {
+    /* vs2 */
+    {
+      4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull,
+      4294967294ull, 4294967294ull, 4294967294ull, 4294967294ull,
+                  1,             1,             1,             1,
+                  0,             0,             0,             0,
+    },
+    /* rs1 */
+    4294967295,
+    /* expect */
+    {
+                           0,                       0,                       0,                       0,
+     18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull,
+     18446744069414584322ull, 18446744069414584322ull, 18446744069414584322ull, 18446744069414584322ull, 
+     18446744069414584321ull, 18446744069414584321ull, 18446744069414584321ull, 18446744069414584321ull, 
+    },
+  },
+};
+
 #endif