--- /dev/null
+From f0b2e563bc419df7c1b3d2f494574c25125f6aed Mon Sep 17 00:00:00 2001
+From: Jeff Moyer <jmoyer@redhat.com>
+Date: Fri, 14 Aug 2015 16:15:32 -0400
+Subject: blockdev: don't set S_DAX for misaligned partitions
+
+From: Jeff Moyer <jmoyer@redhat.com>
+
+commit f0b2e563bc419df7c1b3d2f494574c25125f6aed upstream.
+
+The dax code doesn't currently support misaligned partitions,
+so disable O_DIRECT via dax until such time as that support
+materializes.
+
+Suggested-by: Boaz Harrosh <boaz@plexistor.com>
+Signed-off-by: Jeff Moyer <jmoyer@redhat.com>
+Signed-off-by: Dan Williams <dan.j.williams@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ fs/block_dev.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/fs/block_dev.c
++++ b/fs/block_dev.c
+@@ -1234,6 +1234,13 @@ static int __blkdev_get(struct block_dev
+ goto out_clear;
+ }
+ bd_set_size(bdev, (loff_t)bdev->bd_part->nr_sects << 9);
++ /*
++ * If the partition is not aligned on a page
++ * boundary, we can't do dax I/O to it.
++ */
++ if ((bdev->bd_part->start_sect % (PAGE_SIZE / 512)) ||
++ (bdev->bd_part->nr_sects % (PAGE_SIZE / 512)))
++ bdev->bd_inode->i_flags &= ~S_DAX;
+ }
+ } else {
+ if (bdev->bd_contains == bdev) {
--- /dev/null
+From 6bea0f6d1c47b07be88dfd93f013ae05fcb3d8bf Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Mon, 28 Sep 2015 18:57:03 +0300
+Subject: dmaengine: dw: properly read DWC_PARAMS register
+
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+commit 6bea0f6d1c47b07be88dfd93f013ae05fcb3d8bf upstream.
+
+In case we have less than maximum allowed channels (8) and autoconfiguration is
+enabled the DWC_PARAMS read is wrong because it uses different arithmetic to
+what is needed for channel priority setup.
+
+Re-do the caclulations properly. This now works on AVR32 board well.
+
+Fixes: fed2574b3c9f (dw_dmac: introduce software emulation of LLP transfers)
+Cc: yitian.bu@tangramtek.com
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Vinod Koul <vinod.koul@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/dma/dw/core.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/dma/dw/core.c
++++ b/drivers/dma/dw/core.c
+@@ -1591,7 +1591,6 @@ int dw_dma_probe(struct dw_dma_chip *chi
+ INIT_LIST_HEAD(&dw->dma.channels);
+ for (i = 0; i < nr_channels; i++) {
+ struct dw_dma_chan *dwc = &dw->chan[i];
+- int r = nr_channels - i - 1;
+
+ dwc->chan.device = &dw->dma;
+ dma_cookie_init(&dwc->chan);
+@@ -1603,7 +1602,7 @@ int dw_dma_probe(struct dw_dma_chip *chi
+
+ /* 7 is highest priority & 0 is lowest. */
+ if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
+- dwc->priority = r;
++ dwc->priority = nr_channels - i - 1;
+ else
+ dwc->priority = i;
+
+@@ -1622,6 +1621,7 @@ int dw_dma_probe(struct dw_dma_chip *chi
+ /* Hardware configuration */
+ if (autocfg) {
+ unsigned int dwc_params;
++ unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
+ void __iomem *addr = chip->regs + r * sizeof(u32);
+
+ dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
arm-dts-omap3-beagle-make-i2c3-ddc-and-tfp410-gpio-work-again.patch
arm-exynos-reset-little-cores-when-cpu-is-up.patch
arm-dts-fix-usb-pin-control-for-imx-rex-dts.patch
+blockdev-don-t-set-s_dax-for-misaligned-partitions.patch
+dmaengine-dw-properly-read-dwc_params-register.patch
+x86-apic-serialize-lvtt-and-tsc_deadline-writes.patch
+x86-alternatives-make-optimize_nops-interrupt-safe-and-synced.patch
+x86-platform-fix-geode-lx-timekeeping-in-the-generic-x86-build.patch
--- /dev/null
+From 66c117d7fa2ae429911e60d84bf31a90b2b96189 Mon Sep 17 00:00:00 2001
+From: Thomas Gleixner <tglx@linutronix.de>
+Date: Thu, 3 Sep 2015 12:34:55 +0200
+Subject: x86/alternatives: Make optimize_nops() interrupt safe and synced
+
+From: Thomas Gleixner <tglx@linutronix.de>
+
+commit 66c117d7fa2ae429911e60d84bf31a90b2b96189 upstream.
+
+Richard reported the following crash:
+
+[ 0.036000] BUG: unable to handle kernel paging request at 55501e06
+[ 0.036000] IP: [<c0aae48b>] common_interrupt+0xb/0x38
+[ 0.036000] Call Trace:
+[ 0.036000] [<c0409c80>] ? add_nops+0x90/0xa0
+[ 0.036000] [<c040a054>] apply_alternatives+0x274/0x630
+
+Chuck decoded:
+
+ " 0: 8d 90 90 83 04 24 lea 0x24048390(%eax),%edx
+ 6: 80 fc 0f cmp $0xf,%ah
+ 9: a8 0f test $0xf,%al
+ >> b: a0 06 1e 50 55 mov 0x55501e06,%al
+ 10: 57 push %edi
+ 11: 56 push %esi
+
+ Interrupt 0x30 occurred while the alternatives code was replacing the
+ initial 0x90,0x90,0x90 NOPs (from the ASM_CLAC macro) with the
+ optimized version, 0x8d,0x76,0x00. Only the first byte has been
+ replaced so far, and it makes a mess out of the insn decoding."
+
+optimize_nops() is buggy in two aspects:
+
+- It's not disabling interrupts across the modification
+- It's lacking a sync_core() call
+
+Add both.
+
+Fixes: 4fd4b6e5537c 'x86/alternatives: Use optimized NOPs for padding'
+Reported-and-tested-by: "Richard W.M. Jones" <rjones@redhat.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Cc: Richard W.M. Jones <rjones@redhat.com>
+Cc: Chuck Ebbert <cebbert.lkml@gmail.com>
+Cc: Borislav Petkov <bp@alien8.de>
+Link: http://lkml.kernel.org/r/alpine.DEB.2.11.1509031232340.15006@nanos
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/alternative.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/x86/kernel/alternative.c
++++ b/arch/x86/kernel/alternative.c
+@@ -325,10 +325,15 @@ done:
+
+ static void __init_or_module optimize_nops(struct alt_instr *a, u8 *instr)
+ {
++ unsigned long flags;
++
+ if (instr[0] != 0x90)
+ return;
+
++ local_irq_save(flags);
+ add_nops(instr + (a->instrlen - a->padlen), a->padlen);
++ sync_core();
++ local_irq_restore(flags);
+
+ DUMP_BYTES(instr, a->instrlen, "%p: [%d:%d) optimized NOPs: ",
+ instr, a->instrlen - a->padlen, a->padlen);
--- /dev/null
+From 5d7c631d926b59aa16f3c56eaeb83f1036c81dc7 Mon Sep 17 00:00:00 2001
+From: Shaohua Li <shli@fb.com>
+Date: Thu, 30 Jul 2015 16:24:43 -0700
+Subject: x86/apic: Serialize LVTT and TSC_DEADLINE writes
+
+From: Shaohua Li <shli@fb.com>
+
+commit 5d7c631d926b59aa16f3c56eaeb83f1036c81dc7 upstream.
+
+The APIC LVTT register is MMIO mapped but the TSC_DEADLINE register is an
+MSR. The write to the TSC_DEADLINE MSR is not serializing, so it's not
+guaranteed that the write to LVTT has reached the APIC before the
+TSC_DEADLINE MSR is written. In such a case the write to the MSR is
+ignored and as a consequence the local timer interrupt never fires.
+
+The SDM decribes this issue for xAPIC and x2APIC modes. The
+serialization methods recommended by the SDM differ.
+
+xAPIC:
+ "1. Memory-mapped write to LVT Timer Register, setting bits 18:17 to 10b.
+ 2. WRMSR to the IA32_TSC_DEADLINE MSR a value much larger than current time-stamp counter.
+ 3. If RDMSR of the IA32_TSC_DEADLINE MSR returns zero, go to step 2.
+ 4. WRMSR to the IA32_TSC_DEADLINE MSR the desired deadline."
+
+x2APIC:
+ "To allow for efficient access to the APIC registers in x2APIC mode,
+ the serializing semantics of WRMSR are relaxed when writing to the
+ APIC registers. Thus, system software should not use 'WRMSR to APIC
+ registers in x2APIC mode' as a serializing instruction. Read and write
+ accesses to the APIC registers will occur in program order. A WRMSR to
+ an APIC register may complete before all preceding stores are globally
+ visible; software can prevent this by inserting a serializing
+ instruction, an SFENCE, or an MFENCE before the WRMSR."
+
+The xAPIC method is to just wait for the memory mapped write to hit
+the LVTT by checking whether the MSR write has reached the hardware.
+There is no reason why a proper MFENCE after the memory mapped write would
+not do the same. Andi Kleen confirmed that MFENCE is sufficient for the
+xAPIC case as well.
+
+Issue MFENCE before writing to the TSC_DEADLINE MSR. This can be done
+unconditionally as all CPUs which have TSC_DEADLINE also have MFENCE
+support.
+
+[ tglx: Massaged the changelog ]
+
+Signed-off-by: Shaohua Li <shli@fb.com>
+Reviewed-by: Ingo Molnar <mingo@kernel.org>
+Cc: <Kernel-team@fb.com>
+Cc: <lenb@kernel.org>
+Cc: <fenghua.yu@intel.com>
+Cc: Andi Kleen <ak@linux.intel.com>
+Cc: H. Peter Anvin <hpa@zytor.com>
+Link: http://lkml.kernel.org/r/20150909041352.GA2059853@devbig257.prn2.facebook.com
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/apic/apic.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/x86/kernel/apic/apic.c
++++ b/arch/x86/kernel/apic/apic.c
+@@ -336,6 +336,13 @@ static void __setup_APIC_LVTT(unsigned i
+ apic_write(APIC_LVTT, lvtt_value);
+
+ if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
++ /*
++ * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
++ * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
++ * According to Intel, MFENCE can do the serialization here.
++ */
++ asm volatile("mfence" : : : "memory");
++
+ printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
+ return;
+ }
--- /dev/null
+From 03da3ff1cfcd7774c8780d2547ba0d995f7dc03d Mon Sep 17 00:00:00 2001
+From: David Woodhouse <dwmw2@infradead.org>
+Date: Wed, 16 Sep 2015 14:10:03 +0100
+Subject: x86/platform: Fix Geode LX timekeeping in the generic x86 build
+
+From: David Woodhouse <dwmw2@infradead.org>
+
+commit 03da3ff1cfcd7774c8780d2547ba0d995f7dc03d upstream.
+
+In 2007, commit 07190a08eef36 ("Mark TSC on GeodeLX reliable")
+bypassed verification of the TSC on Geode LX. However, this code
+(now in the check_system_tsc_reliable() function in
+arch/x86/kernel/tsc.c) was only present if CONFIG_MGEODE_LX was
+set.
+
+OpenWRT has recently started building its generic Geode target
+for Geode GX, not LX, to include support for additional
+platforms. This broke the timekeeping on LX-based devices,
+because the TSC wasn't marked as reliable:
+https://dev.openwrt.org/ticket/20531
+
+By adding a runtime check on is_geode_lx(), we can also include
+the fix if CONFIG_MGEODEGX1 or CONFIG_X86_GENERIC are set, thus
+fixing the problem.
+
+Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
+Cc: Andres Salomon <dilinger@queued.net>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Cc: Marcelo Tosatti <marcelo@kvack.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Thomas Gleixner <tglx@linutronix.de>
+Link: http://lkml.kernel.org/r/1442409003.131189.87.camel@infradead.org
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/kernel/tsc.c | 17 ++++++++++-------
+ 1 file changed, 10 insertions(+), 7 deletions(-)
+
+--- a/arch/x86/kernel/tsc.c
++++ b/arch/x86/kernel/tsc.c
+@@ -21,6 +21,7 @@
+ #include <asm/hypervisor.h>
+ #include <asm/nmi.h>
+ #include <asm/x86_init.h>
++#include <asm/geode.h>
+
+ unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
+ EXPORT_SYMBOL(cpu_khz);
+@@ -1004,15 +1005,17 @@ EXPORT_SYMBOL_GPL(mark_tsc_unstable);
+
+ static void __init check_system_tsc_reliable(void)
+ {
+-#ifdef CONFIG_MGEODE_LX
+- /* RTSC counts during suspend */
++#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
++ if (is_geode_lx()) {
++ /* RTSC counts during suspend */
+ #define RTSC_SUSP 0x100
+- unsigned long res_low, res_high;
++ unsigned long res_low, res_high;
+
+- rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
+- /* Geode_LX - the OLPC CPU has a very reliable TSC */
+- if (res_low & RTSC_SUSP)
+- tsc_clocksource_reliable = 1;
++ rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
++ /* Geode_LX - the OLPC CPU has a very reliable TSC */
++ if (res_low & RTSC_SUSP)
++ tsc_clocksource_reliable = 1;
++ }
+ #endif
+ if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
+ tsc_clocksource_reliable = 1;
projects / thirdparty / kernel / stable-queue.git / commitdiff
