6.16-stable patches

added patches:
	pci-dwc-ensure-that-dw_pcie_wait_for_link-waits-100-ms-after-link-up.patch

diff --git a/queue-6.16/pci-dwc-ensure-that-dw_pcie_wait_for_link-waits-100-ms-after-link-up.patch b/queue-6.16/pci-dwc-ensure-that-dw_pcie_wait_for_link-waits-100-ms-after-link-up.patch
new file mode 100644 (file)
index 0000000..ff769e5
--- /dev/null
+++ b/queue-6.16/pci-dwc-ensure-that-dw_pcie_wait_for_link-waits-100-ms-after-link-up.patch
@@ -0,0 +1,48 @@
+From 80dc18a0cba8dea42614f021b20a04354b213d86 Mon Sep 17 00:00:00 2001
+From: Niklas Cassel <cassel@kernel.org>
+Date: Wed, 25 Jun 2025 12:23:51 +0200
+Subject: PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up
+
+From: Niklas Cassel <cassel@kernel.org>
+
+commit 80dc18a0cba8dea42614f021b20a04354b213d86 upstream.
+
+As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
+greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
+training completes before sending a Configuration Request.
+
+Add this delay in dw_pcie_wait_for_link(), after the link is reported as
+up. The delay will only be performed in the success case where the link
+came up.
+
+DWC glue drivers that have a link up IRQ (drivers that set
+use_linkup_irq = true) do not call dw_pcie_wait_for_link(), instead they
+perform this delay in their threaded link up IRQ handler.
+
+Signed-off-by: Niklas Cassel <cassel@kernel.org>
+Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
+Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
+Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
+Link: https://patch.msgid.link/20250625102347.1205584-14-cassel@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pci/controller/dwc/pcie-designware.c |    8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/pci/controller/dwc/pcie-designware.c
++++ b/drivers/pci/controller/dwc/pcie-designware.c
+@@ -714,6 +714,14 @@ int dw_pcie_wait_for_link(struct dw_pcie
+               return -ETIMEDOUT;
+       }
+ 
++      /*
++       * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link
++       * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms
++       * after Link training completes before sending a Configuration Request.
++       */
++      if (pci->max_link_speed > 2)
++              msleep(PCIE_RESET_CONFIG_WAIT_MS);
++
+       offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+       val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
+ 

diff --git a/queue-6.16/series b/queue-6.16/series
index fc1a771cd89e3fa35c8738a9c89138afc482ea03..e389461e3f154b1e198ab7f91e224bc961575fc9 100644 (file)
--- a/queue-6.16/series
+++ b/queue-6.16/series
@@ -329,3 +329,4 @@ usb-dwc3-pci-add-support-for-the-intel-wildcat-lake.patch
 tracing-remove-unneeded-goto-out-logic.patch
 tracing-limit-access-to-parser-buffer-when-trace_get_user-failed.patch
 ovl-use-i_mutex_parent-when-locking-parent-in-ovl_create_temp.patch
+pci-dwc-ensure-that-dw_pcie_wait_for_link-waits-100-ms-after-link-up.patch