perf/x86: Print PMU counters bitmap in x86_pmu_show_pmu_cap()

Along with the introduction Perfmon v6, pmu counters could be
incontinuous, like fixed counters on CWF, only fixed counters 0-3 and
5-7 are supported, there is no fixed counter 4 on CWF. To accommodate
this change, archPerfmonExt CPUID (0x23) leaves are introduced to
enumerate the true-view of counters bitmap.

Current perf code already supports archPerfmonExt CPUID and uses
counters-bitmap to enumerate HW really supported counters, but
x86_pmu_show_pmu_cap() still only dumps the absolute counter number
instead of true-view bitmap, it's out-dated and may mislead readers.

So dump counters true-view bitmap in x86_pmu_show_pmu_cap() and
opportunistically change the dump sequence and words.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Link: https://lore.kernel.org/r/20250820023032.17128-8-dapeng1.mi@linux.intel.com

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 7610f26dfbd90c1d24076ab5d37a42ade739beaf..745caa6c15a32d0d2c02f0cfe32ed41700ba4138 100644 (file)
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2069,13 +2069,15 @@ static void _x86_pmu_read(struct perf_event *event)
 
 void x86_pmu_show_pmu_cap(struct pmu *pmu)
 {
-       pr_info("... version:                %d\n",     x86_pmu.version);
-       pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
-       pr_info("... generic registers:      %d\n",     x86_pmu_num_counters(pmu));
-       pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
-       pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
-       pr_info("... fixed-purpose events:   %d\n",     x86_pmu_num_counters_fixed(pmu));
-       pr_info("... event mask:             %016Lx\n", hybrid(pmu, intel_ctrl));
+       pr_info("... version:                   %d\n", x86_pmu.version);
+       pr_info("... bit width:                 %d\n", x86_pmu.cntval_bits);
+       pr_info("... generic counters:          %d\n", x86_pmu_num_counters(pmu));
+       pr_info("... generic bitmap:            %016llx\n", hybrid(pmu, cntr_mask64));
+       pr_info("... fixed-purpose counters:    %d\n", x86_pmu_num_counters_fixed(pmu));
+       pr_info("... fixed-purpose bitmap:      %016llx\n", hybrid(pmu, fixed_cntr_mask64));
+       pr_info("... value mask:                %016llx\n", x86_pmu.cntval_mask);
+       pr_info("... max period:                %016llx\n", x86_pmu.max_period);
+       pr_info("... global_ctrl mask:          %016llx\n", hybrid(pmu, intel_ctrl));
 }
 
 static int __init init_hw_perf_events(void)