ARC: Correct instruction length attributes.

This patch changes/corrects the "type" insn attribute on the SImode shift
by one bit instructions in arc.md: {ashl,lshr,ashr}si2_cnt1.  These insns
can use a compact representation, but the default method to determine the
"length" attribute of ARC instruction assumes that instructions of type
"shift" have two input operands, and therefore accesses operands[2].
For the shift by constant templates, a type attribute of "unary" is more
appropriate (when an explicit length isn't specified) to avoid an ICE.

2023-10-04  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	* config/arc/arc.md (ashlsi3_cnt1): Rename define_insn *ashlsi2_cnt1.
	Change type attribute to "unary", as this doesn't have operands[2].
	Change length attribute to "*,4" to allow compact representation.
	(lshrsi3_cnt1): Rename define_insn from *lshrsi3_cnt1.  Change
	insn type attribute to "unary", as this doesn't have operands[2].
	(ashrsi3_cnt1): Rename define_insn from *ashrsi3_cnt1.  Change
	insn type attribute to "unary", as this doesn't have operands[2].

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index fe2e7fb366255d26410a337f54c517845e3680c1..4af7332d6fa05cae7400808f92767b57451107b4 100644 (file)
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -5943,15 +5943,15 @@ archs4x, archs4xd"
    (set_attr "predicable" "no")
    (set_attr "length" "4")])
 
-(define_insn "*ashlsi2_cnt1"
+(define_insn "ashlsi3_cnt1"
   [(set (match_operand:SI 0 "dest_reg_operand"           "=q,w")
        (ashift:SI (match_operand:SI 1 "register_operand" "q,c")
                   (const_int 1)))]
   ""
   "asl%? %0,%1%&"
-  [(set_attr "type" "shift")
+  [(set_attr "type" "unary")
    (set_attr "iscompact" "maybe,false")
-   (set_attr "length" "4")
+   (set_attr "length" "*,4")
    (set_attr "predicable" "no,no")])
 
 (define_insn "*ashlsi2_cnt8"
@@ -5976,23 +5976,23 @@ archs4x, archs4xd"
    (set_attr "length" "4")
    (set_attr "predicable" "no")])
 
-(define_insn "*lshrsi3_cnt1"
+(define_insn "lshrsi3_cnt1"
   [(set (match_operand:SI 0 "dest_reg_operand"             "=q,w")
        (lshiftrt:SI (match_operand:SI 1 "register_operand" "q,c")
                     (const_int 1)))]
   ""
   "lsr%? %0,%1%&"
-  [(set_attr "type" "shift")
+  [(set_attr "type" "unary")
    (set_attr "iscompact" "maybe,false")
    (set_attr "predicable" "no,no")])
 
-(define_insn "*ashrsi3_cnt1"
+(define_insn "ashrsi3_cnt1"
   [(set (match_operand:SI 0 "dest_reg_operand"             "=q,w")
        (ashiftrt:SI (match_operand:SI 1 "register_operand" "q,c")
                     (const_int 1)))]
   ""
   "asr%? %0,%1%&"
-  [(set_attr "type" "shift")
+  [(set_attr "type" "unary")
    (set_attr "iscompact" "maybe,false")
    (set_attr "predicable" "no,no")])