arm: dts: agilex5: Add firewall configure settings

These firewall configure settings are needed to disable firewall on
respective hardware component so both secure and non-secure transactions
are allowed.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index 4270dce38dfb50f7fbaad603d4a0ecd21a019f5c..08f568f56500b5f6b3de35a55889c9e1738ea250 100644 (file)
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -222,6 +222,172 @@
                                bootph-all;
                        };
                };
+
+               socfpga_firewall_config: socfpga-firewall-config {
+                       compatible = "intel,socfpga-dtreg";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       bootph-all;
+
+                       /* L4 peripherals firewall */
+                       noc_fw_l4_per@10d21000 {
+                               reg = <0x10d21000 0x0000008c>;
+                               intel,offset-settings =
+                                       /* NAND */
+                                       <0x00000000 0x01010001 0x01010001>,
+                                       /* USB0 */
+                                       <0x0000000c 0x01010001 0x01010001>,
+                                       /* USB1 */
+                                       <0x00000010 0x01010001 0x01010001>,
+                                       /* SPI_MAIN0 */
+                                       <0x0000001c 0x01010301 0x01010301>,
+                                       /* SPI_MAIN1 */
+                                       <0x00000020 0x01010301 0x01010301>,
+                                       /* SPI_SECONDARY0 */
+                                       <0x00000024 0x01010301 0x01010301>,
+                                       /* SPI_SECONDARY1 */
+                                       <0x00000028 0x01010301 0x01010301>,
+                                       /* EMAC0 */
+                                       <0x0000002c 0x01010001 0x01010001>,
+                                       /* EMAC1 */
+                                       <0x00000030 0x01010001 0x01010001>,
+                                       /* EMAC2 */
+                                       <0x00000034 0x01010001 0x01010001>,
+                                       /* SDMMC */
+                                       <0x00000040 0x01010001 0x01010001>,
+                                       /* GPIO0 */
+                                       <0x00000044 0x01010301 0x01010301>,
+                                       /* GPIO1 */
+                                       <0x00000048 0x01010301 0x01010301>,
+                                       /* I2C0 */
+                                       <0x00000050 0x01010301 0x01010301>,
+                                       /* I2C1 */
+                                       <0x00000054 0x01010301 0x01010301>,
+                                       /* I2C2 */
+                                       <0x00000058 0x01010301 0x01010301>,
+                                       /* I2C3 */
+                                       <0x0000005c 0x01010301 0x01010301>,
+                                       /* I2C4 */
+                                       <0x00000060 0x01010301 0x01010301>,
+                                       /* SP_TIMER0 */
+                                       <0x00000064 0x01010301 0x01010301>,
+                                       /* SP_TIMER1 */
+                                       <0x00000068 0x01010301 0x01010301>,
+                                       /* UART0 */
+                                       <0x0000006c 0x01010301 0x01010301>,
+                                       /* UART1 */
+                                       <0x00000070 0x01010301 0x01010301>,
+                                       /* I3C0 */
+                                       <0x00000074 0x01010301 0x01010301>,
+                                       /* I3C1 */
+                                       <0x00000078 0x01010301 0x01010301>,
+                                       /* DMA0 */
+                                       <0x0000007c 0x01010001 0x01010001>,
+                                       /* DMA1 */
+                                       <0x00000080 0x01010001 0x01010001>,
+                                       /* COMBO_PHY */
+                                       <0x00000084 0x01010001 0x01010001>,
+                                       /* NAND_SDMA */
+                                       <0x00000088 0x01010301 0x01010301>;
+                               bootph-all;
+                       };
+
+                       /* L4 system firewall */
+                       noc_fw_l4_sys@10d21100 {
+                               reg = <0x10d21100 0x00000098>;
+                               intel,offset-settings =
+                                       /* DMA_ECC */
+                                       <0x00000008 0x01010001 0x01010001>,
+                                       /* EMAC0RX_ECC */
+                                       <0x0000000c 0x01010001 0x01010001>,
+                                       /* EMAC0TX_ECC */
+                                       <0x00000010 0x01010001 0x01010001>,
+                                       /* EMAC1RX_ECC */
+                                       <0x00000014 0x01010001 0x01010001>,
+                                       /* EMAC1TX_ECC */
+                                       <0x00000018 0x01010001 0x01010001>,
+                                       /* EMAC2RX_ECC */
+                                       <0x0000001c 0x01010001 0x01010001>,
+                                       /* EMAC2TX_ECC */
+                                       <0x00000020 0x01010001 0x01010001>,
+                                       /* NAND_ECC */
+                                       <0x0000002c 0x01010001 0x01010001>,
+                                       /* NAND_READ_ECC */
+                                       <0x00000030 0x01010001 0x01010001>,
+                                       /* NAND_WRITE_ECC */
+                                       <0x00000034 0x01010001 0x01010001>,
+                                       /* OCRAM_ECC */
+                                       <0x00000038 0x01010001 0x01010001>,
+                                       /* SDMMC_ECC */
+                                       <0x00000040 0x01010001 0x01010001>,
+                                       /* USB0_ECC */
+                                       <0x00000044 0x01010001 0x01010001>,
+                                       /* USB1_CACHEECC */
+                                       <0x00000048 0x01010001 0x01010001>,
+                                       /* CLOCK_MANAGER */
+                                       <0x0000004c 0x01010001 0x01010001>,
+                                       /* IO_MANAGER */
+                                       <0x00000054 0x01010001 0x01010001>,
+                                       /* RESET_MANAGER */
+                                       <0x00000058 0x01010001 0x01010001>,
+                                       /* SYSTEM_MANAGER */
+                                       <0x0000005c 0x01010001 0x01010001>,
+                                       /* OSC0_TIMER */
+                                       <0x00000060 0x01010301 0x01010301>,
+                                       /* OSC1_TIMER0*/
+                                       <0x00000064 0x01010301 0x01010301>,
+                                       /* WATCHDOG0 */
+                                       <0x00000068 0x01010301 0x01010301>,
+                                       /* WATCHDOG1 */
+                                       <0x0000006c 0x01010301 0x01010301>,
+                                       /* WATCHDOG2 */
+                                       <0x00000070 0x01010301 0x01010301>,
+                                       /* WATCHDOG3 */
+                                       <0x00000074 0x01010301 0x01010301>,
+                                       /* DAP */
+                                       <0x00000078 0x03010001 0x03010001>,
+                                       /* WATCHDOG4 */
+                                       <0x0000007c 0x01010301 0x01010301>,
+                                       /* POWER_MANAGER */
+                                       <0x00000080 0x01010001 0x01010001>,
+                                       /* USB1_RXECC */
+                                       <0x00000084 0x01010001 0x01010001>,
+                                       /* USB1_TXECC */
+                                       <0x00000088 0x01010001 0x01010001>,
+                                       /* L4_NOC_PROBES */
+                                       <0x00000090 0x01010001 0x01010001>,
+                                       /* L4_NOC_QOS */
+                                       <0x00000094 0x01010001 0x01010001>;
+                               bootph-all;
+                       };
+
+                       /* Light weight SoC2FPGA */
+                       noc_fw_lwsoc2fpga@10d21300 {
+                               reg = <0x10d21300 0x0000004>;
+                               intel,offset-settings =
+                                       /* LWSOC2FPGA_CSR */
+                                       <0x00000000 0x0ffe0301 0x0ffe0301>;
+                               bootph-all;
+                       };
+
+                       /* SoC2FPGA */
+                       noc_fw_soc2fpga@10d21200 {
+                               reg = <0x10d21200 0x0000004>;
+                               intel,offset-settings =
+                                       /* SOC2FPGA_CSR */
+                                       <0x00000000 0x0ffe0301 0x0ffe0301>;
+                               bootph-all;
+                       };
+
+                       /* TCU */
+                       noc_fw_tcu@10d21400 {
+                               reg = <0x10d21400 0x0000004>;
+                               intel,offset-settings =
+                                       /* TCU_CSR */
+                                       <0x00000000 0x01010001 0x01010001>;
+                               bootph-all;
+                       };
+               };
        };
 };