aarch64: Fix sve2p1 extq instruction operands.

This patch fixes the syntax of sve2p1 "extq" instruction by modifying the operands
count to 4. A new operand AARCH64_OPND_SVE_UIMM4 is defined to handle the 4th
argument an 4-bit unsigned immediate of extq instruction. The instruction encoding
is updated to use constraint C_SCAN_MOVPRFX, to enable "extq" instruction to immediately
precede in program order by a MOVPRFX instruction. Also removed the unused operand
AARCH64_OPND_SVE_Zm_imm4.

This issues was reported here:
 https://sourceware.org/pipermail/binutils/2024-February/132408.html

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index cbae27f2a43e5c6f84bc0f6335e54a726fa56aad..84206e44f1f589465a01c696c28c7c6ae88bbc26 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6865,7 +6865,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
        case AARCH64_OPND_SVE_Zm4_11_INDEX:
        case AARCH64_OPND_SVE_Zm4_INDEX:
        case AARCH64_OPND_SVE_Zn_INDEX:
-       case AARCH64_OPND_SVE_Zm_imm4:
        case AARCH64_OPND_SVE_Zn_5_INDEX:
        case AARCH64_OPND_SME_Zm_INDEX1:
        case AARCH64_OPND_SME_Zm_INDEX2:
@@ -7099,6 +7098,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
        case AARCH64_OPND_SVE_SIMM6:
        case AARCH64_OPND_SVE_SIMM8:
        case AARCH64_OPND_SVE_UIMM3:
+       case AARCH64_OPND_SVE_UIMM4:
        case AARCH64_OPND_SVE_UIMM7:
        case AARCH64_OPND_SVE_UIMM8:
        case AARCH64_OPND_SVE_UIMM8_53:

diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
index 58f5b18ae829fe97874e76a3537652a645c1e2fd..90c54fdc90135aacb53f0dfedada0095c82a9087 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-bad.l
@@ -49,12 +49,12 @@
 .*: Error: selected processor does not support `eorqv v4.2d,p3,z2.d'
 .*: Error: selected processor does not support `eorqv v8.2d,p4,z1.d'
 .*: Error: selected processor does not support `eorqv v16.4s,p7,z0.s'
-.*: Error: selected processor does not support `extq z0.b,z0.b,z10.b\[15\]'
-.*: Error: selected processor does not support `extq z1.b,z1.b,z15.b\[7\]'
-.*: Error: selected processor does not support `extq z2.b,z2.b,z5.b\[3\]'
-.*: Error: selected processor does not support `extq z4.b,z4.b,z12.b\[1\]'
-.*: Error: selected processor does not support `extq z8.b,z8.b,z7.b\[4\]'
-.*: Error: selected processor does not support `extq z16.b,z16.b,z1.b\[8\]'
+.*: Error: selected processor does not support `extq z0.b,z0.b,z0.b,#0'
+.*: Error: selected processor does not support `extq z31.b,z31.b,z0.b,#0'
+.*: Error: selected processor does not support `extq z0.b,z0.b,z31.b,#0'
+.*: Error: selected processor does not support `extq z0.b,z0.b,z0.b,#15'
+.*: Error: selected processor does not support `extq z31.b,z31.b,z31.b,#15'
+.*: Error: selected processor does not support `extq z15.b,z15.b,z31.b,#7'
 .*: Error: selected processor does not support `faddqv v1.8h,p1,z8.h'
 .*: Error: selected processor does not support `faddqv v2.4s,p2,z4.s'
 .*: Error: selected processor does not support `faddqv v4.2d,p3,z2.d'

diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index c61c0438b0a6a5d35b67eb62c4fad2af24c9906b..8635d3344421b1143f5f09bbb82b2fcdb5bcfbbe 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -58,12 +58,12 @@
 .*:    04dd2c44        eorqv   v4.2d, p3, z2.d
 .*:    04dd3028        eorqv   v8.2d, p4, z1.d
 .*:    049d3c10        eorqv   v16.4s, p7, z0.s
-.*:    056a27c0        extq    z0.b, z0.b, z10.b\[15\]
-.*:    056f25c1        extq    z1.b, z1.b, z15.b\[7\]
-.*:    056524c2        extq    z2.b, z2.b, z5.b\[3\]
-.*:    056c2444        extq    z4.b, z4.b, z12.b\[1\]
-.*:    05672508        extq    z8.b, z8.b, z7.b\[4\]
-.*:    05612610        extq    z16.b, z16.b, z1.b\[8\]
+.*:    05602400        extq    z0.b, z0.b, z0.b, #0
+.*:    0560241f        extq    z31.b, z31.b, z0.b, #0
+.*:    056027e0        extq    z0.b, z0.b, z31.b, #0
+.*:    056f2400        extq    z0.b, z0.b, z0.b, #15
+.*:    056f27ff        extq    z31.b, z31.b, z31.b, #15
+.*:    056727ef        extq    z15.b, z15.b, z31.b, #7
 .*:    6450a501        faddqv  v1.8h, p1, z8.h
 .*:    6490a882        faddqv  v2.4s, p2, z4.s
 .*:    64d0ac44        faddqv  v4.2d, p3, z2.d

diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.s b/gas/testsuite/gas/aarch64/sve2p1-1.s
index 753f27f5ef244b204d50755a8cfc369395e4be7d..0e33c603361e3ea33bd59eb4f18b111fa503c40c 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve2p1-1.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.s
@@ -55,12 +55,12 @@ eorqv v4.2d, p3, z2.d
 eorqv v8.2d, p4, z1.d
 eorqv v16.4s, p7, z0.s
 
-extq z0.b, z0.b, z10.b[15]
-extq z1.b, z1.b, z15.b[7]
-extq z2.b, z2.b, z5.b[3]
-extq z4.b, z4.b, z12.b[1]
-extq z8.b, z8.b, z7.b[4]
-extq z16.b, z16.b, z1.b[8]
+extq z0.b, z0.b, z0.b, #0
+extq z31.b, z31.b, z0.b, #0
+extq z0.b, z0.b, z31.b, #0
+extq z0.b, z0.b, z0.b, #15
+extq z31.b, z31.b, z31.b, #15
+extq z15.b, z15.b, z31.b, #7
 faddqv v1.8h, p1, z8.h
 faddqv v2.4s, p2, z4.s
 faddqv v4.2d, p3, z2.d

diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.d
new file mode 100644 (file)
index 0000000..ff6ecb2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 extq instructions.
+#as: -march=armv9.4-a
+#error_output: sve2p1-3-invalid.l

diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.l
new file mode 100644 (file)
index 0000000..ca8f4cd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.l
@@ -0,0 +1,17 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `extq z0.b,z0.h,z0.b,#0'
+.*: Info:    did you mean this\?
+.*: Info:      extq z0.b, z0.b, z0.b, #0
+.*: Error: operand 2 must be the same register as operand 1 -- `extq z31.b,z15.b,z0.b,#0'
+.*: Error: operand mismatch -- `extq z0.b,z0.b,z31.h,#0'
+.*: Info:    did you mean this\?
+.*: Info:      extq z0.b, z0.b, z31.b, #0
+.*: Error: immediate value out of range 0 to 15 at operand 4 -- `extq z0.b,z0.b,z0.b,#16'
+.*: Error: operand mismatch -- `extq z0.h,z0.h,z0.h,#15'
+.*: Info:    did you mean this\?
+.*: Info:      extq z0.b, z0.b, z0.b, #15
+.*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `extq z3.b,z3.b,z0.b,#0'
+.*: Error: operand 2 must be the same register as operand 1 -- `extq z31.b,z2.b,z0.b,#15'
+.*: Warning: instruction opens new dependency sequence without ending previous one -- `movprfx z31.b,p1/m,z10.b'
+.*: Warning: predicated instruction expected after `movprfx' -- `extq z31.b,z31.b,z0.b,#15'
+.*: Warning: output register of preceding `movprfx' used as input at operand 3 -- `extq z0.b,z0.b,z0.b,#0'

diff --git a/gas/testsuite/gas/aarch64/sve2p1-3-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.s
new file mode 100644 (file)
index 0000000..a6211ee
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3-invalid.s
@@ -0,0 +1,16 @@
+extq z0.b, z0.h, z0.b, #0
+extq z31.b, z15.b, z0.b, #0
+extq z0.b, z0.b, z31.h, #0
+extq z0.b, z0.b, z0.b, #16
+extq z0.h, z0.h, z0.h, #15
+movprfx z1, z5
+extq z3.b, z3.b, z0.b, #0
+
+movprfx z31, z10
+extq z31.b, z2.b, z0.b, #15
+
+movprfx z31.b, p1/m, z10.b
+extq z31.b, z31.b, z0.b, #15
+
+movprfx z0, z2
+extq z0.b, z0.b, z0.b, #0

diff --git a/gas/testsuite/gas/aarch64/sve2p1-3.d b/gas/testsuite/gas/aarch64/sve2p1-3.d
new file mode 100644 (file)
index 0000000..bacb1b6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3.d
@@ -0,0 +1,20 @@
+#name: Test of SVE2.1 extq instructions.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:    05602400        extq    z0.b, z0.b, z0.b, #0
+.*:    0560241f        extq    z31.b, z31.b, z0.b, #0
+.*:    056027e0        extq    z0.b, z0.b, z31.b, #0
+.*:    056f2400        extq    z0.b, z0.b, z0.b, #15
+.*:    056f27ff        extq    z31.b, z31.b, z31.b, #15
+.*:    056727ef        extq    z15.b, z15.b, z31.b, #7
+.*:    0420bca3        movprfx z3, z5
+.*:    05602403        extq    z3.b, z3.b, z0.b, #0
+.*:    0420bd5f        movprfx z31, z10
+.*:    056f241f        extq    z31.b, z31.b, z0.b, #15

diff --git a/gas/testsuite/gas/aarch64/sve2p1-3.s b/gas/testsuite/gas/aarch64/sve2p1-3.s
new file mode 100644 (file)
index 0000000..38864b7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-3.s
@@ -0,0 +1,12 @@
+extq z0.b, z0.b, z0.b, #0
+extq z31.b, z31.b, z0.b, #0
+extq z0.b, z0.b, z31.b, #0
+extq z0.b, z0.b, z0.b, #15
+extq z31.b, z31.b, z31.b, #15
+extq z15.b, z15.b, z31.b, #7
+
+movprfx z3, z5
+extq z3.b, z3.b, z0.b, #0
+
+movprfx z31, z10
+extq z31.b, z31.b, z0.b, #15

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 78f19b65cb30873e877ac67ac104373cba5673de..a178e8c6e4c65be0cf1049c878f49836b9bd89ec 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -757,6 +757,7 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_UIMM7,      /* SVE unsigned 7-bit immediate.  */
   AARCH64_OPND_SVE_UIMM8,      /* SVE unsigned 8-bit immediate.  */
   AARCH64_OPND_SVE_UIMM8_53,   /* SVE split unsigned 8-bit immediate.  */
+  AARCH64_OPND_SVE_UIMM4,      /* SVE unsigned 4-bit immediate.  */
   AARCH64_OPND_SVE_VZn,                /* Scalar SIMD&FP register in Zn field.  */
   AARCH64_OPND_SVE_Vd,         /* Scalar SIMD&FP register in Vd.  */
   AARCH64_OPND_SVE_Vm,         /* Scalar SIMD&FP register in Vm.  */
@@ -783,7 +784,6 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
   AARCH64_OPND_SVE_Zm3_10_INDEX, /* z0-z7[0-15] in Zm3_INDEX plus bit 11:10.  */
   AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11.  */
-  AARCH64_OPND_SVE_Zm_imm4,     /* SVE vector register with 4bit index.  */
   AARCH64_OPND_SVE_Zm4_INDEX,  /* z0-z15[0-1] in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zn,         /* SVE vector register in Zn.  */
   AARCH64_OPND_SVE_Zn_INDEX,   /* Indexed SVE vector register, for DUP.  */

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 1838e04c8986e7f1909f20a232409e2d57a216d1..5eb21c242517280bb2d1d125746289835bd43218 100644 (file)
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -668,15 +668,15 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 194:
     case 195:
     case 196:
-    case 211:
     case 212:
     case 213:
     case 214:
-    case 223:
+    case 215:
     case 224:
     case 225:
     case 226:
     case 227:
+    case 228:
     case 239:
     case 243:
     case 248:
@@ -712,9 +712,9 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 40:
     case 41:
     case 42:
-    case 228:
     case 229:
-    case 232:
+    case 230:
+    case 233:
     case 269:
     case 270:
     case 285:
@@ -782,6 +782,7 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 208:
     case 209:
     case 210:
+    case 211:
     case 271:
     case 302:
     case 303:
@@ -939,19 +940,18 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 202:
     case 284:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 215:
     case 216:
     case 217:
     case 218:
-      return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
     case 219:
+      return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
     case 220:
     case 221:
     case 222:
+    case 223:
       return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
-    case 230:
     case 231:
-    case 233:
+    case 232:
     case 234:
     case 235:
     case 236:

diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 4d1271de18d0f712549e53cb2a2bf63d60069454..095272811781cb5422f5af758dc5a5d1f401582d 100644 (file)
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -34457,15 +34457,15 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 194:
     case 195:
     case 196:
-    case 211:
     case 212:
     case 213:
     case 214:
-    case 223:
+    case 215:
     case 224:
     case 225:
     case 226:
     case 227:
+    case 228:
     case 239:
     case 243:
     case 248:
@@ -34506,9 +34506,9 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 40:
     case 41:
     case 42:
-    case 228:
     case 229:
-    case 232:
+    case 230:
+    case 233:
     case 269:
     case 270:
     case 285:
@@ -34577,6 +34577,7 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 208:
     case 209:
     case 210:
+    case 211:
     case 271:
     case 302:
     case 303:
@@ -34736,19 +34737,18 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 202:
     case 284:
       return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
-    case 215:
     case 216:
     case 217:
     case 218:
-      return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
     case 219:
+      return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
     case 220:
     case 221:
     case 222:
+    case 223:
       return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors);
-    case 230:
     case 231:
-    case 233:
+    case 232:
     case 234:
     case 235:
     case 236:

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index c9580b3cc24f5149ff6e1077a92eb8496dab2c97..3d067d4ad94f5f57a5b8485289758009abe11700 100644 (file)
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -235,6 +235,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3_10}, "an 8-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a 4-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},
@@ -261,7 +262,6 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"},
-  {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5}, "an indexed SVE vector register"},

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 918d9880cfe87fc41bf83dec165e37934b9564e5..639347412d8fcb6d36578dcfefa7cb98ce440f5b 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1852,11 +1852,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
            return 0;
          break;
 
-       case AARCH64_OPND_SVE_Zm_imm4:
-         if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, 0, 15))
-           return 0;
-         break;
-
        case AARCH64_OPND_SVE_Zn_5_INDEX:
          size = aarch64_get_qualifier_esize (opnd->qualifier);
          if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
@@ -2742,6 +2737,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
        case AARCH64_OPND_SVE_UIMM3:
        case AARCH64_OPND_SVE_UIMM7:
        case AARCH64_OPND_SVE_UIMM8:
+       case AARCH64_OPND_SVE_UIMM4:
        case AARCH64_OPND_SVE_UIMM8_53:
        case AARCH64_OPND_CSSC_UIMM8:
          size = get_operand_fields_width (get_operand_from_code (type));
@@ -4296,7 +4292,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SME_Zn_INDEX3_14:
     case AARCH64_OPND_SME_Zn_INDEX3_15:
     case AARCH64_OPND_SME_Zn_INDEX4_14:
-    case AARCH64_OPND_SVE_Zm_imm4:
       snprintf (buf, size, "%s[%s]",
                (opnd->qualifier == AARCH64_OPND_QLF_NIL
                 ? style_reg (styler, "z%d", opnd->reglane.regno)
@@ -4463,6 +4458,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SVE_UIMM3:
     case AARCH64_OPND_SVE_UIMM7:
     case AARCH64_OPND_SVE_UIMM8:
+    case AARCH64_OPND_SVE_UIMM4:
     case AARCH64_OPND_SVE_UIMM8_53:
     case AARCH64_OPND_IMM_ROT1:
     case AARCH64_OPND_IMM_ROT2:
@@ -5590,7 +5586,8 @@ verify_constraints (const struct aarch64_inst *inst,
             instruction for better error messages.  */
          if (!opcode->avariant
              || (!AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE)
-                 && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2)))
+                 && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2)
+                 && !AARCH64_CPU_HAS_FEATURE (*opcode->avariant, SVE2p1)))
            {
              mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
              mismatch_detail->error = _("SVE instruction expected after "

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7270dd10aaf75ebacaacfa9727c54b9ad79be7f0..88921662775719d08b0511077ac148e18a11e76b 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6641,7 +6641,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
 
   SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
-  SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1),
+  SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
   SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0),
   SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
   SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
@@ -7256,6 +7256,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
       "an 8-bit unsigned immediate")                                   \
     Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3_10),              \
       "an 8-bit unsigned immediate")                                   \
+    Y(IMMEDIATE, imm, "SVE_UIMM4", 0, F(FLD_SVE_imm4),                 \
+      "a 4-bit unsigned immediate")                                    \
     Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \
     Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register")  \
     Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD_SVE_Vm), "a SIMD register")  \
@@ -7313,9 +7315,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
     Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX",                     \
       4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4),     \
       "an indexed SVE vector register")                                        \
-    Y(SVE_REG, sve_quad_index, "SVE_Zm_imm4",                          \
-      5 << OPD_F_OD_LSB, F(FLD_SVE_Zm_5, FLD_SVE_imm4),                        \
-      "an 4bit indexed SVE vector register")                           \
     Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX",                        \
       4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16),                             \
       "an indexed SVE vector register")                                        \