.36 patches

diff --git a/queue-2.6.36/drm-i915-always-set-the-dp-transcoder-config-to-8bpc.patch b/queue-2.6.36/drm-i915-always-set-the-dp-transcoder-config-to-8bpc.patch
new file mode 100644 (file)
index 0000000..fe4a0f3
--- /dev/null
+++ b/queue-2.6.36/drm-i915-always-set-the-dp-transcoder-config-to-8bpc.patch
@@ -0,0 +1,47 @@
+From 220cad3cbf553f893432919b458da36489373fc6 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Thu, 18 Nov 2010 09:32:58 +0800
+Subject: drm/i915: Always set the DP transcoder config to 8BPC.
+
+From: Eric Anholt <eric@anholt.net>
+
+commit 220cad3cbf553f893432919b458da36489373fc6 upstream.
+
+The pipe is always set to 8BPC, but here we were leaving whatever
+previous bits were set by the BIOS in place.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Tested-by: Keith Packard <keithp@keithp.com>
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_reg.h      |    1 +
+ drivers/gpu/drm/i915/intel_display.c |    4 +++-
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -2953,6 +2953,7 @@
+ #define  TRANS_DP_10BPC               (1<<9)
+ #define  TRANS_DP_6BPC                (2<<9)
+ #define  TRANS_DP_12BPC               (3<<9)
++#define  TRANS_DP_BPC_MASK    (3<<9)
+ #define  TRANS_DP_VSYNC_ACTIVE_HIGH   (1<<4)
+ #define  TRANS_DP_VSYNC_ACTIVE_LOW    0
+ #define  TRANS_DP_HSYNC_ACTIVE_HIGH   (1<<3)
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -2044,9 +2044,11 @@ static void ironlake_crtc_dpms(struct dr
+ 
+                               reg = I915_READ(trans_dp_ctl);
+                               reg &= ~(TRANS_DP_PORT_SEL_MASK |
+-                                       TRANS_DP_SYNC_MASK);
++                                       TRANS_DP_SYNC_MASK |
++                                       TRANS_DP_BPC_MASK);
+                               reg |= (TRANS_DP_OUTPUT_ENABLE |
+                                       TRANS_DP_ENH_FRAMING);
++                              reg |= TRANS_DP_8BPC;
+ 
+                               if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
+                                     reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;

diff --git a/queue-2.6.36/series b/queue-2.6.36/series
index 807f3eeca2b93f61844c32f59aeada81982fe396..86ffaa28efb8d3ab1c91f6f8cedb61bfff8525ec 100644 (file)
--- a/queue-2.6.36/series
+++ b/queue-2.6.36/series
@@ -9,3 +9,4 @@ alsa-hda-use-model-lg-quirk-for-lg-p1-express-to-enable-playback-and-capture.pat
 drm-radeon-kms-don-t-apply-7xx-hdp-flush-workaround-on-agp.patch
 drm-kms-remove-spaces-from-connector-names-v2.patch
 drm-radeon-kms-fix-vram-base-calculation-on-rs780-rs880.patch
+drm-i915-always-set-the-dp-transcoder-config-to-8bpc.patch