arm64: dts: allwinner: h616: add NAND controller

The H616 has a NAND controller quite similar to the A10/A23 ones, but
with some register differences, more clocks (for ECC and MBUS), more ECC
strengths, so this requires a new compatible string.

Add the NAND controller node and pins in the device tree.

Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Link: https://patch.msgid.link/20251028073534.526992-17-richard.genoud@bootlin.com
[wens@kernel.org: Fixed alignment of clocks in nand-controller node]
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index ceedae9e399b6e975f7f5ca362b528eeb0dd4491..8d1110c14bad2fd6142fd950ab7ebefce29068c0 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -304,6 +304,42 @@
                                bias-pull-up;
                        };
 
+                       /omit-if-no-ref/
+                       nand_pins: nand-pins {
+                               pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9",
+                                      "PC10", "PC11", "PC12", "PC13", "PC14",
+                                      "PC15", "PC16";
+                               function = "nand0";
+                       };
+
+                       /omit-if-no-ref/
+                       nand_cs0_pin: nand-cs0-pin {
+                               pins = "PC4";
+                               function = "nand0";
+                               bias-pull-up;
+                       };
+
+                       /omit-if-no-ref/
+                       nand_cs1_pin: nand-cs1-pin {
+                               pins = "PC3";
+                               function = "nand0";
+                               bias-pull-up;
+                       };
+
+                       /omit-if-no-ref/
+                       nand_rb0_pin: nand-rb0-pin {
+                               pins = "PC6";
+                               function = "nand0";
+                               bias-pull-up;
+                       };
+
+                       /omit-if-no-ref/
+                       nand_rb1_pin: nand-rb1-pin {
+                               pins = "PC7";
+                               function = "nand0";
+                               bias-pull-up;
+                       };
+
                        /omit-if-no-ref/
                        spi0_pins: spi0-pins {
                                pins = "PC0", "PC2", "PC4";
@@ -377,6 +413,22 @@
                        #iommu-cells = <1>;
                };
 
+               nfc: nand-controller@4011000 {
+                       compatible = "allwinner,sun50i-h616-nand-controller";
+                       reg = <0x04011000 0x1000>;
+                       interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>,
+                                <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>;
+                       clock-names = "ahb", "mod", "ecc", "mbus";
+                       resets = <&ccu RST_BUS_NAND>;
+                       reset-names = "ahb";
+                       dmas = <&dma 10>;
+                       dma-names = "rxtx";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                mmc0: mmc@4020000 {
                        compatible = "allwinner,sun50i-h616-mmc",
                                     "allwinner,sun50i-a100-mmc";