aarch64: Fix sve2p1 dupq instruction operands.

This patch fixes the syntax of sve2p1 "dupq" instruction by modifying the way
2nd operand does the encoding and decoding using the [<imm>] value.

dupq makes use of already existing aarch64_ins_sve_index and aarch64_ext_sve_index
inserter and extractor functions. The definitions of aarch64_ins_sve_index_imm (inserter)
and aarch64_ext_sve_index_imm (extractor) is removed in this patch.

This issues was reported here:
 https://sourceware.org/pipermail/binutils/2024-February/132408.html

diff --git a/gas/testsuite/gas/aarch64/sve2p1-1.d b/gas/testsuite/gas/aarch64/sve2p1-1.d
index f562985b5691398b8c08393012a78f31d3e30430..c61c0438b0a6a5d35b67eb62c4fad2af24c9906b 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -44,14 +44,14 @@
 .*:    04cf2c44        uminqv  v4.2d, p3, z2.d
 .*:    04cf3028        uminqv  v8.2d, p4, z1.d
 .*:    048f3c10        uminqv  v16.4s, p7, z0.s
-.*:    0530268a        dupq    z10.b, z20.b\[0\]
+.*:    0521268a        dupq    z10.b, z20.b\[0\]
 .*:    053f268a        dupq    z10.b, z20.b\[15\]
-.*:    0521268a        dupq    z10.h, z20.h\[0\]
-.*:    052f268a        dupq    z10.h, z20.h\[7\]
-.*:    0522268a        dupq    z10.s, z20.s\[0\]
-.*:    052e268a        dupq    z10.s, z20.s\[3\]
-.*:    0524268a        dupq    z10.d, z20.d\[0\]
-.*:    052c268a        dupq    z10.d, z20.d\[1\]
+.*:    0522268a        dupq    z10.h, z20.h\[0\]
+.*:    053e268a        dupq    z10.h, z20.h\[7\]
+.*:    0524268a        dupq    z10.s, z20.s\[0\]
+.*:    053c268a        dupq    z10.s, z20.s\[3\]
+.*:    0528268a        dupq    z10.d, z20.d\[0\]
+.*:    0538268a        dupq    z10.d, z20.d\[1\]
 .*:    041d2200        eorqv   v0.16b, p0, z16.b
 .*:    045d2501        eorqv   v1.8h, p1, z8.h
 .*:    049d2882        eorqv   v2.4s, p2, z4.s

diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.d
new file mode 100644 (file)
index 0000000..3953ca5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 dupq instructions.
+#as: -march=armv9.4-a
+#error_output: sve2p1-2-invalid.l

diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.l
new file mode 100644 (file)
index 0000000..26c2488
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.l
@@ -0,0 +1,47 @@
+.*: Assembler messages:
+.*: Error: register element index out of range 0 to 15 at operand 2 -- `dupq z0.b,z0.b\[16\]'
+.*: Error: operand mismatch -- `dupq z0.h,z0.b\[16\]'
+.*: Info:    did you mean this\?
+.*: Info:      dupq z0.b, z0.b\[16\]
+.*: Info:    other valid variant\(s\):
+.*: Info:      dupq z0.h, z0.h\[16\]
+.*: Info:      dupq z0.s, z0.s\[16\]
+.*: Info:      dupq z0.d, z0.d\[16\]
+.*: Error: operand mismatch -- `dupq z0.h,z0.s\[16\]'
+.*: Info:    did you mean this\?
+.*: Info:      dupq z0.h, z0.h\[16\]
+.*: Info:    other valid variant\(s\):
+.*: Info:      dupq z0.b, z0.b\[16\]
+.*: Info:      dupq z0.s, z0.s\[16\]
+.*: Info:      dupq z0.d, z0.d\[16\]
+.*: Error: operand mismatch -- `dupq z0.s,z0.d\[16\]'
+.*: Info:    did you mean this\?
+.*: Info:      dupq z0.s, z0.s\[16\]
+.*: Info:    other valid variant\(s\):
+.*: Info:      dupq z0.b, z0.b\[16\]
+.*: Info:      dupq z0.h, z0.h\[16\]
+.*: Info:      dupq z0.d, z0.d\[16\]
+.*: Error: register element index out of range 0 to 7 at operand 2 -- `dupq z0.h,z0.h\[8\]'
+.*: Error: register element index out of range 0 to 3 at operand 2 -- `dupq z0.s,z0.s\[4\]'
+.*: Error: register element index out of range 0 to 1 at operand 2 -- `dupq z0.d,z0.d\[2\]'
+.*: Error: operand mismatch -- `dupq z0.q,z0.d\[16\]'
+.*: Info:    did you mean this\?
+.*: Info:      dupq z0.d, z0.d\[16\]
+.*: Info:    other valid variant\(s\):
+.*: Info:      dupq z0.b, z0.b\[16\]
+.*: Info:      dupq z0.h, z0.h\[16\]
+.*: Info:      dupq z0.s, z0.s\[16\]
+.*: Error: operand mismatch -- `dupq z0.s,z0.q\[16\]'
+.*: Info:    did you mean this\?
+.*: Info:      dupq z0.s, z0.s\[16\]
+.*: Info:    other valid variant\(s\):
+.*: Info:      dupq z0.b, z0.b\[16\]
+.*: Info:      dupq z0.h, z0.h\[16\]
+.*: Info:      dupq z0.d, z0.d\[16\]
+.*: Error: operand mismatch -- `dupq z10.q,z20.q\[0\]'
+.*: Info:    did you mean this\?
+.*: Info:      dupq z10.b, z20.b\[0\]
+.*: Info:    other valid variant\(s\):
+.*: Info:      dupq z10.h, z20.h\[0\]
+.*: Info:      dupq z10.s, z20.s\[0\]
+.*: Info:      dupq z10.d, z20.d\[0\]

diff --git a/gas/testsuite/gas/aarch64/sve2p1-2-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.s
new file mode 100644 (file)
index 0000000..8f5fd52
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2-invalid.s
@@ -0,0 +1,10 @@
+       dupq z0.b, z0.b[16]
+       dupq z0.h, z0.b[16]
+       dupq z0.h, z0.s[16]
+       dupq z0.s, z0.d[16]
+       dupq z0.h, z0.h[8]
+       dupq z0.s, z0.s[4]
+       dupq z0.d, z0.d[2]
+       dupq z0.q, z0.d[16]
+       dupq z0.s, z0.q[16]
+       dupq z10.q, z20.q[0]

diff --git a/gas/testsuite/gas/aarch64/sve2p1-2.d b/gas/testsuite/gas/aarch64/sve2p1-2.d
new file mode 100644 (file)
index 0000000..cd9900d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2.d
@@ -0,0 +1,34 @@
+#name: Test of SVE2.1 dupq instructions.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:    05212400        dupq    z0.b, z0.b\[0\]
+.*:    0521241f        dupq    z31.b, z0.b\[0\]
+.*:    052127e0        dupq    z0.b, z31.b\[0\]
+.*:    053f2400        dupq    z0.b, z0.b\[15\]
+.*:    053f27ff        dupq    z31.b, z31.b\[15\]
+.*:    052925e7        dupq    z7.b, z15.b\[4\]
+.*:    05222400        dupq    z0.h, z0.h\[0\]
+.*:    0522241f        dupq    z31.h, z0.h\[0\]
+.*:    052227e0        dupq    z0.h, z31.h\[0\]
+.*:    053e2400        dupq    z0.h, z0.h\[7\]
+.*:    053e27ff        dupq    z31.h, z31.h\[7\]
+.*:    053225e7        dupq    z7.h, z15.h\[4\]
+.*:    05242400        dupq    z0.s, z0.s\[0\]
+.*:    0524241f        dupq    z31.s, z0.s\[0\]
+.*:    052427e0        dupq    z0.s, z31.s\[0\]
+.*:    053c2400        dupq    z0.s, z0.s\[3\]
+.*:    053c27ff        dupq    z31.s, z31.s\[3\]
+.*:    053425e7        dupq    z7.s, z15.s\[2\]
+.*:    05282400        dupq    z0.d, z0.d\[0\]
+.*:    0528241f        dupq    z31.d, z0.d\[0\]
+.*:    052827e0        dupq    z0.d, z31.d\[0\]
+.*:    05382400        dupq    z0.d, z0.d\[1\]
+.*:    053827ff        dupq    z31.d, z31.d\[1\]
+.*:    052825e7        dupq    z7.d, z15.d\[0\]

diff --git a/gas/testsuite/gas/aarch64/sve2p1-2.s b/gas/testsuite/gas/aarch64/sve2p1-2.s
new file mode 100644 (file)
index 0000000..4fc3cdc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-2.s
@@ -0,0 +1,28 @@
+       .text
+       dupq    z0.b, z0.b[0]
+       dupq    z31.b, z0.b[0]
+       dupq    z0.b, z31.b[0]
+       dupq    z0.b, z0.b[15]
+       dupq    z31.b, z31.b[15]
+       dupq    z7.b, z15.b[4]
+
+       dupq    z0.h, z0.h[0]
+       dupq    z31.h, z0.h[0]
+       dupq    z0.h, z31.h[0]
+       dupq    z0.h, z0.h[7]
+       dupq    z31.h, z31.h[7]
+       dupq    z7.h, z15.h[4]
+
+       dupq    z0.s, z0.s[0]
+       dupq    z31.s, z0.s[0]
+       dupq    z0.s, z31.s[0]
+       dupq    z0.s, z0.s[3]
+       dupq    z31.s, z31.s[3]
+       dupq    z7.s, z15.s[2]
+
+       dupq    z0.d, z0.d[0]
+       dupq    z31.d, z0.d[0]
+       dupq    z0.d, z31.d[0]
+       dupq    z0.d, z0.d[1]
+       dupq    z31.d, z31.d[1]
+       dupq    z7.d, z15.d[0]

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 3410a76a56174066cfb9ed49349cd8b4cbbf37a0..78f19b65cb30873e877ac67ac104373cba5673de 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -786,8 +786,8 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_Zm_imm4,     /* SVE vector register with 4bit index.  */
   AARCH64_OPND_SVE_Zm4_INDEX,  /* z0-z15[0-1] in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zn,         /* SVE vector register in Zn.  */
-  AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ.  */
   AARCH64_OPND_SVE_Zn_INDEX,   /* Indexed SVE vector register, for DUP.  */
+  AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ.  */
   AARCH64_OPND_SVE_ZnxN,       /* SVE vector register list in Zn.  */
   AARCH64_OPND_SVE_Zt,         /* SVE vector register in Zt.  */
   AARCH64_OPND_SVE_ZtxN,       /* SVE vector register list in Zt.  */

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 7578093b938f6b1ccea241e910d84dc5528be00d..1838e04c8986e7f1909f20a232409e2d57a216d1 100644 (file)
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -959,7 +959,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 238:
       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
     case 240:
-      return aarch64_ins_sve_index_imm (self, info, code, inst, errors);
     case 241:
       return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 242:

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index e738bb431252cc23c018553ec6e1fbe1018f92a9..0867c08940c180076691682a1e591d5bc40235be 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1291,23 +1291,8 @@ aarch64_ins_sve_index (const aarch64_operand *self,
 {
   unsigned int esize = aarch64_get_qualifier_esize (info->qualifier);
   insert_field (self->fields[0], code, info->reglane.regno, 0);
-  insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0,
-                2, FLD_imm5, FLD_SVE_tszh);
-  return true;
-}
-
-/* Encode Zn.<T>[<imm>], where <imm> is an immediate with range of 0 to one less
-   than the number of elements in 128 bit, which can encode il:tsz.  */
-bool
-aarch64_ins_sve_index_imm (const aarch64_operand *self,
-                          const aarch64_opnd_info *info, aarch64_insn *code,
-                          const aarch64_inst *inst ATTRIBUTE_UNUSED,
-                          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
-{
-  insert_field (self->fields[0], code, info->reglane.regno, 0);
-  unsigned int esize = aarch64_get_qualifier_esize (info->qualifier);
-  insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0,
-                2, self->fields[1],self->fields[2]);
+  insert_all_fields_after (self, 1, code,
+                          (info->reglane.index * 2 + 1) * esize);
   return true;
 }
 

diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index edeb6d8de7e2c3e117e0ad91a02b93c0e040a061..88143eecfcd8ba5efb74858417fafd7c3d99759f 100644 (file)
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -95,7 +95,6 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one);
 AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
 AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one);
 AARCH64_DECL_OPD_INSERTER (ins_sve_index);
-AARCH64_DECL_OPD_INSERTER (ins_sve_index_imm);
 AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
 AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
 AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);

diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index d16a43bbdf9be55817b7a19a7d11974471a73118..4d1271de18d0f712549e53cb2a2bf63d60069454 100644 (file)
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -34756,7 +34756,6 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 238:
       return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
     case 240:
-      return aarch64_ext_sve_index_imm (self, info, code, inst, errors);
     case 241:
       return aarch64_ext_sve_index (self, info, code, inst, errors);
     case 242:

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 6098204f3d742b05962f933bb76cf237d760c468..d3f38c3cda57d734e80499724f88237632fcb804 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2237,7 +2237,7 @@ aarch64_ext_sve_index (const aarch64_operand *self,
   int val;
 
   info->reglane.regno = extract_field (self->fields[0], code, 0);
-  val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5);
+  val = extract_all_fields_after (self, 1, code);
   if ((val & 31) == 0)
     return 0;
   while ((val & 1) == 0)
@@ -2246,26 +2246,6 @@ aarch64_ext_sve_index (const aarch64_operand *self,
   return true;
 }
 
-/* Decode Zn.<T>[<imm>], where <imm> is an immediate with range of 0 to one less
-   than the number of elements in 128 bit, which can encode il:tsz.  */
-bool
-aarch64_ext_sve_index_imm (const aarch64_operand *self,
-                          aarch64_opnd_info *info, aarch64_insn code,
-                          const aarch64_inst *inst ATTRIBUTE_UNUSED,
-                          aarch64_operand_error *errors ATTRIBUTE_UNUSED)
-{
-  int val;
-
-  info->reglane.regno = extract_field (self->fields[0], code, 0);
-  val = extract_fields (code, 0, 2, self->fields[2], self->fields[1]);
-  if ((val & 15) == 0)
-    return 0;
-  while ((val & 1) == 0)
-    val /= 2;
-  info->reglane.index = val / 2;
-  return true;
-}
-
 /* Decode a logical immediate for the MOV alias of SVE DUPM.  */
 bool
 aarch64_ext_sve_limm_mov (const aarch64_operand *self,
@@ -3456,19 +3436,9 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
       break;
 
     case sve_index:
-      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
-      if ((i & 31) == 0)
-       return false;
-      while ((i & 1) == 0)
-       {
-         i >>= 1;
-         variant += 1;
-       }
-      break;
+      i = extract_field (FLD_imm5, inst->value, 0);
 
-    case sve_index1:
-      i = extract_fields (inst->value, 0, 2, FLD_SVE_tsz, FLD_SVE_i2h);
-      if ((i & 15) == 0)
+      if ((i & 31) == 0)
        return false;
       while ((i & 1) == 0)
        {

diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index 9e8f7c214d70390a72f93e38655a5ac0f562d085..a71524f9c642013a5b890a7067fde933cd5cca41 100644 (file)
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -119,7 +119,6 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one);
 AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two);
 AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_zero_one);
 AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
-AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index_imm);
 AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
 AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
 AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 1eb6dc3a23daf832ca6ccbb5a135dcf5d5222b2d..c9580b3cc24f5149ff6e1077a92eb8496dab2c97 100644 (file)
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -264,8 +264,8 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
-  {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_i2h, FLD_SVE_tsz}, "a 5 bit idexed SVE vector register"},
-  {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
+  {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5}, "an indexed SVE vector register"},
+  {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm5}, "a 5 bit indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 35d9e5cf44aeccf02917b9f3e5554c81cfb0708d..7270dd10aaf75ebacaacfa9727c54b9ad79be7f0 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6640,7 +6640,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   SVE2p1_INSNC("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
   SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
 
-  SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
+  SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
   SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1),
   SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0),
   SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
@@ -7321,11 +7321,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
       "an indexed SVE vector register")                                        \
     Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn),                      \
       "an SVE vector register")                                                \
-    Y(SVE_REG, sve_index_imm, "SVE_Zn_5_INDEX", 0,                     \
-      F(FLD_SVE_Zn, FLD_SVE_i2h, FLD_SVE_tsz),                         \
-      "a 5 bit idexed SVE vector register")                            \
-    Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn),            \
+    Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0,                           \
+      F(FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5),                           \
       "an indexed SVE vector register")                                        \
+    Y(SVE_REG, sve_index, "SVE_Zn_5_INDEX", 0,                         \
+      F(FLD_SVE_Zn, FLD_imm5),                                         \
+      "a 5 bit indexed SVE vector register")                           \
     Y(SVE_REGLIST, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn),          \
       "a list of SVE vector registers")                                        \
     Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt),                      \