]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
Generate vmovapd instead of vmovsd for moving DFmode between SSE_REGS.
authorliuhongt <hongtao.liu@intel.com>
Thu, 20 Jul 2023 01:38:09 +0000 (09:38 +0800)
committerliuhongt <hongtao.liu@intel.com>
Wed, 16 Aug 2023 01:01:47 +0000 (09:01 +0800)
vmovapd can enable register renaming and have same code size as
vmovsd. Similar for vmovsh vs vmovaps, vmovaps is 1 byte less than
vmovsh.

When TARGET_AVX512VL is not available, still generate
vmovsd/vmovss/vmovsh to avoid vmovapd/vmovaps zmm16-31.

gcc/ChangeLog:

* config/i386/i386.md (movdf_internal): Generate vmovapd instead of
vmovsd when moving DFmode between SSE_REGS.
(movhi_internal): Generate vmovdqa instead of vmovsh when
moving HImode between SSE_REGS.
(mov<mode>_internal): Use vmovaps instead of vmovsh when
moving HF/BFmode between SSE_REGS.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr89229-4a.c: Adjust testcase.

gcc/config/i386/i386.md
gcc/testsuite/gcc.target/i386/pr89229-4a.c

index c906d75b13e97debaaca4898a567aaeb1a7611dc..77182e34fe1f819f94f7980cbcb65bf0e740a8ab 100644 (file)
                    ]
                    (const_string "TI"))
            (eq_attr "alternative" "12")
-             (cond [(match_test "TARGET_AVX512FP16")
+             (cond [(match_test "TARGET_AVX512VL")
+                      (const_string "TI")
+                    (match_test "TARGET_AVX512FP16")
                       (const_string "HF")
+                    (match_test "TARGET_AVX512F")
+                      (const_string "SF")
                     (match_test "TARGET_AVX")
                       (const_string "TI")
                     (ior (not (match_test "TARGET_SSE2"))
 
               /* movaps is one byte shorter for non-AVX targets.  */
               (eq_attr "alternative" "13,17")
-                (cond [(match_test "TARGET_AVX")
+                (cond [(match_test "TARGET_AVX512VL")
+                         (const_string "V2DF")
+                       (match_test "TARGET_AVX512F")
                          (const_string "DF")
+                       (match_test "TARGET_AVX")
+                         (const_string "V2DF")
                        (ior (not (match_test "TARGET_SSE2"))
                             (match_test "optimize_function_for_size_p (cfun)"))
                          (const_string "V4SF")
                   (const_string "HI")
                   (const_string "TI"))
               (eq_attr "alternative" "5")
-                (cond [(match_test "TARGET_AVX512FP16")
+                (cond [(match_test "TARGET_AVX512VL")
+                       (const_string "V4SF")
+                       (match_test "TARGET_AVX512FP16")
                          (const_string "HF")
+                       (match_test "TARGET_AVX512F")
+                         (const_string "SF")
+                       (match_test "TARGET_AVX")
+                         (const_string "V4SF")
                        (ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
                             (match_test "TARGET_SSE_SPLIT_REGS"))
                          (const_string "V4SF")
index 5bc10d256193ebe57957a0e9250e7c2a394bbe03..8869650b0ad02adce04fa092d2591c6d1a1c4a1f 100644 (file)
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-do assemble { target { ! ia32 } } } */
 /* { dg-options "-O2 -march=skylake-avx512" } */
 
 extern double d;
@@ -12,5 +12,3 @@ foo1 (double x)
   asm volatile ("" : "+v" (xmm17));
   d = xmm17;
 }
-
-/* { dg-final { scan-assembler-not "vmovapd" } } */