RISC-V: Add test for vec_duplicate + vwmulu.vv signed combine with GR2VR cost 0,...

Add asm dump check and run test for vec_duplicate + vwmulu.vv
combine to vwmulu.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vwmulu.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Add test helper
	macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test
	data for vwmulu.vx run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 25bb93c8ce501b480f0066e8129a6c8f48224ebf..c86461beadf295fb774ad70c8a9902ee2f2f3617 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
+/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 475b74b10f0d44cbfbc1b782d660cc062eb0c29f..90de1974ab1f1be23a6c5c710dd5059a5b356720 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
+/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index c7f3f2b25d4d48c6cedc3e365c38d3baa98f2328..522ddd19ccd490d52e8527932d06102bb05a5b46 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -34,3 +34,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vwaddu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vwsubu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vwmulu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 1c0024c273ef007abb0aef1033d73144ddcb921f..6ea17bb83d9b441f3f6475fb1f2277b6a0c33be1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
+/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 3e88fc0623f7a2f6a9cf47ddb57bb448fe9153c3..8b8fba54b72a33a7dd6be671e70fb0b9565639a5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
+/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 541b6e678b9a892ac5fa943e60e808b1ce0109df..6f66de906a29825e77ab09264742370235a88447 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
+/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 6d25e26d83b62e933c1793779439c060471b8079..cd129f1f50ea3a5ef29bea7b1e39744b1cb7d79e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
+/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index f0c6624a536c88a17137f7a1d9140e9bb91b962e..48aeed71eb9cfb243872769e54d4c00d6e429e1c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
+/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 8de1d6fd8070fdc79b4ff58e33f7e912abbc532a..b88c350acf3e16ad4bb8f37bc61920f3bd1d5615 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
 /* { dg-final { scan-assembler-not {vwaddu.vx} } } */
 /* { dg-final { scan-assembler-not {vwsubu.vx} } } */
+/* { dg-final { scan-assembler-not {vwmulu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c
new file mode 100644 (file)
index 0000000..11c11ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c
@@ -0,0 +1,18 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_widen.h"
+#include "vx_widen_data.h"
+
+#define WT        uint64_t
+#define NT        uint32_t
+#define NAME      mul
+#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME)
+#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME)
+
+DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, NAME)
+
+#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \
+  RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N)
+
+#include "vx_widen_vx_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
index 290d8a4b5d4385e8f6c4e4390464679aea29c522..998c05961ab0bfc2362d272e2a032e5f2bb30d18 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
@@ -30,6 +30,7 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd,   \
 
 #define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT)     \
   DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) \
-  DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub)
+  DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) \
+  DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, mul) \
 
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
index 7359f0bc85d3888394163166bcb7a7a7e5a45e5a..5b49083abe72799e53798fb27a8af2473090d25c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
@@ -37,6 +37,7 @@
 
 DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add)
 DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, sub)
+DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, mul)
 
 DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = {
   {
@@ -116,4 +117,43 @@ DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, sub)[] = {
   },
 };
 
+DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, mul)[] = {
+  {
+    /* vs2 */
+    {
+      1, 1, 1, 1,
+      0, 0, 0, 0,
+      2, 2, 2, 2,
+      9, 9, 9, 9,
+    },
+    /* rs1 */
+    2147483647,
+    /* expect */
+    {
+          2147483647,     2147483647,     2147483647,     2147483647,
+                   0,              0,              0,              0,
+          4294967294,     4294967294,     4294967294,     4294967294,
+      19327352823ull, 19327352823ull, 19327352823ull, 19327352823ull,
+    },
+  },
+  {
+    /* vs2 */
+    {
+                  1,             1,             1,             1,
+                  0,             0,             0,             0,
+      4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull,
+      4294967294ull, 4294967294ull, 4294967294ull, 4294967294ull,
+    },
+    /* rs1 */
+    4294967295,
+    /* expect */
+    {
+                4294967295ull,           4294967295ull,           4294967295ull,           4294967295ull,
+                            0,                       0,                       0,                       0,
+      18446744065119617025ull, 18446744065119617025ull, 18446744065119617025ull, 18446744065119617025ull,
+      18446744060824649730ull, 18446744060824649730ull, 18446744060824649730ull, 18446744060824649730ull,
+    },
+  },
+};
+
 #endif