drm/i915: Enable Wa_16019325821

Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240223205632.1621019-2-John.C.Harrison@Intel.com

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1bf13e3d307073956379da22d2d8e989b56cff6..bb8e4c151a026ac079700879199da22fdaaa135c 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -743,21 +743,23 @@ static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs)
 }
 
 /* Wa_14014475959:dg2 */
-#define CCS_SEMAPHORE_PPHWSP_OFFSET    0x540
-static u32 ccs_semaphore_offset(struct i915_request *rq)
+/* Wa_16019325821 */
+#define HOLD_SWITCHOUT_SEMAPHORE_PPHWSP_OFFSET 0x540
+static u32 hold_switchout_semaphore_offset(struct i915_request *rq)
 {
        return i915_ggtt_offset(rq->context->state) +
-               (LRC_PPHWSP_PN * PAGE_SIZE) + CCS_SEMAPHORE_PPHWSP_OFFSET;
+               (LRC_PPHWSP_PN * PAGE_SIZE) + HOLD_SWITCHOUT_SEMAPHORE_PPHWSP_OFFSET;
 }
 
 /* Wa_14014475959:dg2 */
-static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs)
+/* Wa_16019325821 */
+static u32 *hold_switchout_emit_wa_busywait(struct i915_request *rq, u32 *cs)
 {
        int i;
 
        *cs++ = MI_ATOMIC_INLINE | MI_ATOMIC_GLOBAL_GTT | MI_ATOMIC_CS_STALL |
                MI_ATOMIC_MOVE;
-       *cs++ = ccs_semaphore_offset(rq);
+       *cs++ = hold_switchout_semaphore_offset(rq);
        *cs++ = 0;
        *cs++ = 1;
 
@@ -773,7 +775,7 @@ static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs)
                MI_SEMAPHORE_POLL |
                MI_SEMAPHORE_SAD_EQ_SDD;
        *cs++ = 0;
-       *cs++ = ccs_semaphore_offset(rq);
+       *cs++ = hold_switchout_semaphore_offset(rq);
        *cs++ = 0;
 
        return cs;
@@ -790,8 +792,9 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
                cs = gen12_emit_preempt_busywait(rq, cs);
 
        /* Wa_14014475959:dg2 */
-       if (intel_engine_uses_wa_hold_ccs_switchout(rq->engine))
-               cs = ccs_emit_wa_busywait(rq, cs);
+       /* Wa_16019325821 */
+       if (intel_engine_uses_wa_hold_switchout(rq->engine))
+               cs = hold_switchout_emit_wa_busywait(rq, cs);
 
        rq->tail = intel_ring_offset(rq, cs);
        assert_ring_tail_valid(rq->ring, rq->tail);

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 960e6be2042fe0c185fd4a2d73d9d010d743b9cd..b519812ba120d85162223a8d157888ce72d2b12a 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -586,7 +586,7 @@ struct intel_engine_cs {
 #define I915_ENGINE_HAS_RCS_REG_STATE  BIT(9)
 #define I915_ENGINE_HAS_EU_PRIORITY    BIT(10)
 #define I915_ENGINE_FIRST_RENDER_COMPUTE BIT(11)
-#define I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT BIT(12)
+#define I915_ENGINE_USES_WA_HOLD_SWITCHOUT BIT(12)
        unsigned int flags;
 
        /*
@@ -696,10 +696,11 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
 }
 
 /* Wa_14014475959:dg2 */
+/* Wa_16019325821 */
 static inline bool
-intel_engine_uses_wa_hold_ccs_switchout(struct intel_engine_cs *engine)
+intel_engine_uses_wa_hold_switchout(struct intel_engine_cs *engine)
 {
-       return engine->flags & I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
+       return engine->flags & I915_ENGINE_USES_WA_HOLD_SWITCHOUT;
 }
 
 #endif /* __INTEL_ENGINE_TYPES_H__ */

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index d2b7425bbdcc2bc94ec0d183cb27b0acc143d615..6b1abefa7909fca81a0a3db02a51188f7eb86ac0 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -294,6 +294,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
            IS_DG2(gt->i915))
                flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 
+       /* Wa_16019325821 */
+       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
+               flags |= GUC_WA_RCS_CCS_SWITCHOUT;
+
        /*
         * Wa_14012197797
         * Wa_22011391025

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 8ae1846431da74be39e60ee6b639bafbb7f98acf..48863188a130e17c0eb9c23813bbb1a2a60f528f 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -96,8 +96,9 @@
 #define   GUC_WA_GAM_CREDITS           BIT(10)
 #define   GUC_WA_DUAL_QUEUE            BIT(11)
 #define   GUC_WA_RCS_RESET_BEFORE_RC6  BIT(13)
-#define   GUC_WA_CONTEXT_ISOLATION     BIT(15)
 #define   GUC_WA_PRE_PARSER            BIT(14)
+#define   GUC_WA_CONTEXT_ISOLATION     BIT(15)
+#define   GUC_WA_RCS_CCS_SWITCHOUT     BIT(16)
 #define   GUC_WA_HOLD_CCS_SWITCHOUT    BIT(17)
 #define   GUC_WA_POLLCS                        BIT(18)
 #define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST     BIT(21)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e5c645137cfe721c63b833c32b4233b5eb725b0a..f0fe6f967651763de51873d256c8d9123e79cdb4 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4502,7 +4502,12 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
        if (engine->class == COMPUTE_CLASS)
                if (IS_GFX_GT_IP_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
                    IS_DG2(engine->i915))
-                       engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
+                       engine->flags |= I915_ENGINE_USES_WA_HOLD_SWITCHOUT;
+
+       /* Wa_16019325821 */
+       if ((engine->class == COMPUTE_CLASS || engine->class == RENDER_CLASS) &&
+           IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+               engine->flags |= I915_ENGINE_USES_WA_HOLD_SWITCHOUT;
 
        /*
         * TODO: GuC supports timeslicing and semaphores as well, but they're