--- /dev/null
+From emmanuel.grumbach@intel.com Tue Jan 3 12:52:53 2012
+From: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
+Date: Mon, 26 Dec 2011 08:47:34 +0200
+Subject: iwlwifi: update SCD BC table for all SCD queues
+To: stable@vger.kernel.org
+Cc: Emmanuel Grumbach <emmanuel.grumbach@intel.com>, Wey-Yi Guy <wey-yi.w.guy@intel.com>, "John W. Linville" <linville@tuxdriver.com>
+Message-ID: <1324882054-15030-2-git-send-email-emmanuel.grumbach@intel.com>
+
+From: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
+
+commit 96f1f05af76b601ab21a7dc603ae0a1cea4efc3d upstream.
+
+Since we configure all the queues as CHAINABLE, we need to update the
+byte count for all the queues, not only the AGGREGATABLE ones.
+
+Not doing so can confuse the SCD and make the fw assert.
+
+Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
+Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
+Signed-off-by: John W. Linville <linville@tuxdriver.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/net/wireless/iwlwifi/iwl-trans.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/net/wireless/iwlwifi/iwl-trans.c
++++ b/drivers/net/wireless/iwlwifi/iwl-trans.c
+@@ -1068,9 +1068,7 @@ static int iwl_trans_tx(struct iwl_priv
+ iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
+
+ /* Set up entry for this TFD in Tx byte-count array */
+- if (ampdu)
+- iwl_trans_txq_update_byte_cnt_tbl(priv, txq,
+- le16_to_cpu(tx_cmd->len));
++ iwl_trans_txq_update_byte_cnt_tbl(priv, txq, le16_to_cpu(tx_cmd->len));
+
+ dma_sync_single_for_device(priv->bus->dev, txcmd_phys, firstlen,
+ DMA_BIDIRECTIONAL);
--- /dev/null
+From 3d6271f92e98094584fd1e609a9969cd33e61122 Mon Sep 17 00:00:00 2001
+From: Kyle Manna <kyle@kylemanna.com>
+Date: Thu, 11 Aug 2011 22:33:13 -0500
+Subject: mfd: Turn on the twl4030-madc MADC clock
+
+From: Kyle Manna <kyle@kylemanna.com>
+
+commit 3d6271f92e98094584fd1e609a9969cd33e61122 upstream.
+
+Without turning the MADC clock on, no MADC conversions occur.
+
+$ cat /sys/class/hwmon/hwmon0/device/in8_input
+[ 53.428436] twl4030_madc twl4030_madc: conversion timeout!
+cat: read error: Resource temporarily unavailable
+
+Signed-off-by: Kyle Manna <kyle@kylemanna.com>
+Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/mfd/twl4030-madc.c | 22 ++++++++++++++++++++++
+ include/linux/i2c/twl4030-madc.h | 4 ++++
+ 2 files changed, 26 insertions(+)
+
+--- a/drivers/mfd/twl4030-madc.c
++++ b/drivers/mfd/twl4030-madc.c
+@@ -740,6 +740,28 @@ static int __devinit twl4030_madc_probe(
+ TWL4030_BCI_BCICTL1);
+ goto err_i2c;
+ }
++
++ /* Check that MADC clock is on */
++ ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, ®val, TWL4030_REG_GPBR1);
++ if (ret) {
++ dev_err(&pdev->dev, "unable to read reg GPBR1 0x%X\n",
++ TWL4030_REG_GPBR1);
++ goto err_i2c;
++ }
++
++ /* If MADC clk is not on, turn it on */
++ if (!(regval & TWL4030_GPBR1_MADC_HFCLK_EN)) {
++ dev_info(&pdev->dev, "clk disabled, enabling\n");
++ regval |= TWL4030_GPBR1_MADC_HFCLK_EN;
++ ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, regval,
++ TWL4030_REG_GPBR1);
++ if (ret) {
++ dev_err(&pdev->dev, "unable to write reg GPBR1 0x%X\n",
++ TWL4030_REG_GPBR1);
++ goto err_i2c;
++ }
++ }
++
+ platform_set_drvdata(pdev, madc);
+ mutex_init(&madc->lock);
+ ret = request_threaded_irq(platform_get_irq(pdev, 0), NULL,
+--- a/include/linux/i2c/twl4030-madc.h
++++ b/include/linux/i2c/twl4030-madc.h
+@@ -129,6 +129,10 @@ enum sample_type {
+ #define REG_BCICTL2 0x024
+ #define TWL4030_BCI_ITHSENS 0x007
+
++/* Register and bits for GPBR1 register */
++#define TWL4030_REG_GPBR1 0x0c
++#define TWL4030_GPBR1_MADC_HFCLK_EN (1 << 7)
++
+ struct twl4030_madc_user_parms {
+ int channel;
+ int average;