u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
- mutex_lock(&chip->i2c_lock);
/* Select the correct bank */
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
if (ret < 0)
* Read the register through direct access regmap. The target range
* is marked volatile.
*/
- ret = regmap_read(chip->regmap, reg, val);
-out:
- mutex_unlock(&chip->i2c_lock);
-
- return ret;
+ return regmap_read(chip->regmap, reg, val);
}
static int
u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off);
int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off);
- mutex_lock(&chip->i2c_lock);
/* Select the correct bank */
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
if (ret < 0)
* Write the register through direct access regmap. The target range
* is marked volatile.
*/
- ret = regmap_write(chip->regmap, reg, val);
-out:
- mutex_unlock(&chip->i2c_lock);
-
- return ret;
+ return regmap_write(chip->regmap, reg, val);
}
static bool cy8c95x0_mux_accessible_register(struct device *dev, unsigned int off)
.num_reg_defaults_raw = MUXED_STRIDE * BANK_SZ,
.readable_reg = cy8c95x0_mux_accessible_register,
.writeable_reg = cy8c95x0_mux_accessible_register,
+ .disable_locking = true,
};
/* Direct access regmap */
.cache_type = REGCACHE_FLAT,
.max_register = CY8C95X0_COMMAND,
+ .disable_locking = true,
};
static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip,
if (reg == CY8C95X0_PORTSEL)
return -EINVAL;
+ mutex_lock(&chip->i2c_lock);
+
/* Registers behind the PORTSEL mux have their own regmap */
if (cy8c95x0_muxed_register(reg)) {
regmap = chip->muxed_regmap;
ret = regmap_update_bits_base(regmap, off, mask, val, change, async, force);
if (ret < 0)
- return ret;
+ goto out;
/* Update the cache when a WC bit is written */
if (cy8c95x0_wc_register(reg) && (mask & val)) {
regcache_cache_only(regmap, false);
}
}
+out:
+ mutex_unlock(&chip->i2c_lock);
return ret;
}
unsigned int port, unsigned int *read_val)
{
struct regmap *regmap;
- int off;
+ int off, ret;
+
+ mutex_lock(&chip->i2c_lock);
/* Registers behind the PORTSEL mux have their own regmap */
if (cy8c95x0_muxed_register(reg)) {
off = reg;
}
- return regmap_read(regmap, off, read_val);
+ ret = regmap_read(regmap, off, read_val);
+
+ mutex_unlock(&chip->i2c_lock);
+
+ return ret;
}
static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,