RISC-V: Add test for vec_duplicate + vmseq.vv combine case 0 with GR2VR cost 0, 1...

Add asm dump check and run test for vec_duplicate + vmseq.vv
combine to vmseq.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
	for vmseq.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index 8879af34650d03ac177c80ba8cd32f9151d6053f..8c8d5c560e999f0cb831ce2e4d39c72620c8f4c5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 1b7b7401ada7cccc01c893b14d0e325c37a5eefe..16490f14c56c593a0693e9a83d2567da8a35252d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 00d8ef7d85beab9902dd00b15d1a4abf8f720f72..b76646dde075c4af848a00a71fa52d76aa9b39b8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -30,3 +30,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index 4480635033aa52833ca88734fa4aa2400bd48e56..f9aba35dcf2e8f45ee9f8e8567a99d1e577400d4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index d02aaa347dff262b6b6889417b77bdabd038bf60..16881478594c4e94ab92f40fa7ff324fbd94410a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 5921fe66baef3ad27aae1fbbbadec155e9d80b6d..042bc1adc8fec4ad53b8fd50a3fdfed3709fab52 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 3b5331914692ca4ec6632324dc4a41d862743fa3..0f7d23894fb3d7c0e27e6333df938c3cffc648a1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index ca9fa4a30711519d4776c41a54b2ec42edef6605..4b1faafc1fb9a4364746fa784c1129f8d8585ad9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 573ae91bd1fe54032e6e073a29d7fd2edc3b5c90..8b4ec62d0ed2d9d03df13d4b6109ee5328b0c22a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 5fab6befc2392fd6be25260da7b855e7bd939f75..0a1bd06993552a41a61dbfd422f43384e6a4464a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 5d67e47c4d9bc0a200fddedece4d0be33febb760..0d0b688edff4b5bd98b68eccf6da600171f2c3ac 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index d889a841c4dce85ebf15fd406aa7fe70fa31da01..18d86cb7954372c210125b9ffeaba27fdf67a1d2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsub.vx} } } */
+/* { dg-final { scan-assembler-not {vmseq.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index 353ee167c3764e6866d847031afbcae3568d2fea..194f304c4293a3a41b2039fcfe09d617ce682dff 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -402,6 +402,7 @@ DEF_AVG_CEIL(int32_t, int64_t)
   DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)                            \
   DEF_VX_BINARY_CASE_0_WRAP(T, /, div)                            \
   DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)                            \
+  DEF_VX_BINARY_CASE_0_WRAP(T, ==, eq)                            \
   DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max)           \
   DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max)           \
   DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min)           \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index e385bf21ec7ab7ef044ecb4c5a204663f9cf2ee8..aace7ca8457d7d5458a294b7e0e06761c056d4e0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -3338,6 +3338,142 @@ uint64_t TEST_BINARY_DATA(uint64_t, rem)[][3][N] =
   },
 };
 
+int8_t TEST_BINARY_DATA(int8_t, eq)[][3][N] =
+{
+  {
+    { 1 },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+    },
+  },
+  {
+    { 127 },
+    {
+         0,    0,    0,    0,
+       127,  127,  127,  127,
+      -128, -128, -128, -128,
+        -2,   -2,   -2,   -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+    },
+  },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, eq)[][3][N] =
+{
+  {
+    { 1 },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+    },
+  },
+  {
+    { -32768 },
+    {
+           0,      0,      0,      0,
+          -1,     -1,     -1,     -1,
+      -32768, -32768, -32768, -32768,
+          -2,     -2,     -2,     -2,
+    },
+    {
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+    },
+  },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, eq)[][3][N] =
+{
+  {
+    { 1 },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+    },
+  },
+  {
+    { -2147483648 },
+    {
+                0,           0,           0,           0,
+               -1,          -1,          -1,          -1,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+               -2,          -2,          -2,          -2,
+    },
+    {
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+    },
+  },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, eq)[][3][N] =
+{
+  {
+    { 1 },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+    },
+  },
+  {
+    { -9223372036854775808ull },
+    {
+                            0,                       0,                       0,                       0,
+                           -1,                      -1,                      -1,                      -1,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+                           -2,                      -2,                      -2,                      -2,
+    },
+    {
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+    },
+  },
+};
+
 int8_t TEST_BINARY_DATA(int8_t, max)[][3][N] =
 {
   {

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i16.c
new file mode 100644 (file)
index 0000000..43404c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int16_t
+#define NAME eq
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ==, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i32.c
new file mode 100644 (file)
index 0000000..c2d59a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int32_t
+#define NAME eq
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ==, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i64.c
new file mode 100644 (file)
index 0000000..b680dd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int64_t
+#define NAME eq
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ==, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i8.c
new file mode 100644 (file)
index 0000000..b9219b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmseq-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int8_t
+#define NAME eq
+
+DEF_VX_BINARY_CASE_0_WRAP(T, ==, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"