drm/amdgpu: Add sdma_v5_2 ip dump for devcoredump

Add ip dump for sdma_v5_2 for devcoredump for all
instances of sdma.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index d3706a48487022105cb2e6511b089174696687c5..087ce0f6fa0763a188dbc0fcad803563f26267a9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -115,6 +115,7 @@ struct amdgpu_sdma {
        bool                    has_page_queue;
        struct ras_common_if    *ras_if;
        struct amdgpu_sdma_ras  *ras;
+       uint32_t                *ip_dump;
 };
 
 /*

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index cc9e961f007877d9d9c29d89f231b3959898acbc..0cc969689946b61a7a2ff3af0a130a89c5f497a5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -60,6 +60,55 @@ MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
 #define SDMA0_HYP_DEC_REG_END 0x5893
 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
 
+static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_2[] = {
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS2_REG),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS3_REG),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UCODE_CHECKSUM),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH_HI),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RB_RPTR_FETCH),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_STATUS),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_STATUS),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK0),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_RD_XNACK1),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK1),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_CNTL),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_WPTR_HI),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_OFFSET),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_LO),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_BASE_HI),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_SUB_REMAIN),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_DUMMY_REG),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_CNTL),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_RPTR_HI),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_RB_WPTR_HI),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_OFFSET),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_LO),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_IB_BASE_HI),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_PAGE_DUMMY_REG),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_CNTL),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR_HI),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR_HI),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_OFFSET),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_HI),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_DUMMY_REG),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_INT_STATUS),
+       SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_VM_CNTL),
+       SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2)
+};
+
 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
@@ -1214,6 +1263,8 @@ static int sdma_v5_2_sw_init(void *handle)
        struct amdgpu_ring *ring;
        int r, i;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);
+       uint32_t *ptr;
 
        /* SDMA trap event */
        for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -1245,6 +1296,13 @@ static int sdma_v5_2_sw_init(void *handle)
                        return r;
        }
 
+       /* Allocate memory for SDMA IP Dump buffer */
+       ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
+       if (ptr)
+               adev->sdma.ip_dump = ptr;
+       else
+               DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
+
        return r;
 }
 
@@ -1258,6 +1316,8 @@ static int sdma_v5_2_sw_fini(void *handle)
 
        amdgpu_sdma_destroy_inst_ctx(adev, true);
 
+       kfree(adev->sdma.ip_dump);
+
        return 0;
 }
 
@@ -1662,6 +1722,27 @@ static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring)
        amdgpu_gfx_off_ctrl(adev, true);
 }
 
+static void sdma_v5_2_dump_ip_state(void *handle)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       int i, j;
+       uint32_t instance_offset;
+       uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2);
+
+       if (!adev->sdma.ip_dump)
+               return;
+
+       amdgpu_gfx_off_ctrl(adev, false);
+       for (i = 0; i < adev->sdma.num_instances; i++) {
+               instance_offset = i * reg_count;
+               for (j = 0; j < reg_count; j++)
+                       adev->sdma.ip_dump[instance_offset + j] =
+                               RREG32(sdma_v5_2_get_reg_offset(adev, i,
+                                      sdma_reg_list_5_2[j].reg_offset));
+       }
+       amdgpu_gfx_off_ctrl(adev, true);
+}
+
 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
        .name = "sdma_v5_2",
        .early_init = sdma_v5_2_early_init,
@@ -1678,6 +1759,7 @@ const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
        .set_clockgating_state = sdma_v5_2_set_clockgating_state,
        .set_powergating_state = sdma_v5_2_set_powergating_state,
        .get_clockgating_state = sdma_v5_2_get_clockgating_state,
+       .dump_ip_state = sdma_v5_2_dump_ip_state,
 };
 
 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {