drm/msm/a6xx: Add A642L speedbin (0x81)

According to downstream, A642L's speedbin is 129 and uses 4 as index

Signed-off-by: Eugene Lepshy <fekz115@gmail.com>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/606722/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 68ba9aed5506ea2f367ff0282a73fdd1122f2526..99f0ee1a2edea6a79f9337c98fcdc8a172a34210 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -869,6 +869,7 @@ static const struct adreno_info a6xx_gpus[] = {
                .speedbins = ADRENO_SPEEDBINS(
                        { 0,   0 },
                        { 117, 0 },
+                       { 129, 4 },
                        { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */
                        { 190, 1 },
                ),