--- /dev/null
+From e323d56eb06b266b77c2b430cb5f1977ba549e03 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <k.kozlowski@samsung.com>
+Date: Fri, 12 Jun 2015 10:53:25 +0900
+Subject: clk: exynos4: Fix wrong clock for Exynos4x12 ADC
+
+From: Krzysztof Kozlowski <k.kozlowski@samsung.com>
+
+commit e323d56eb06b266b77c2b430cb5f1977ba549e03 upstream.
+
+The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
+However TSADC is present only on Exynos4210 so on Trats2 board (with
+Exynos4412 SoC) the exynos-adc driver could not be probed:
+ ERROR: could not get clock /adc@126C0000:adc(0)
+ exynos-adc 126c0000.adc: failed getting clock, err = -2
+ exynos-adc: probe of 126c0000.adc failed with error -2
+
+Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
+Converter is located in different register and it is named in datasheet
+as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
+is the same as purpose of TSADC from Exynos4210.
+
+The patch adds gate clock for Exynos4x12 using the proper register so
+backward compatibility is preserved. This fixes the probe of exynos-adc
+driver on Exynos4x12 boards and allows accessing sensors connected to it
+on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
+
+Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
+Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
+Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
+Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/samsung/clk-exynos4.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/clk/samsung/clk-exynos4.c
++++ b/drivers/clk/samsung/clk-exynos4.c
+@@ -86,6 +86,7 @@
+ #define DIV_PERIL4 0xc560
+ #define DIV_PERIL5 0xc564
+ #define E4X12_DIV_CAM1 0xc568
++#define E4X12_GATE_BUS_FSYS1 0xc744
+ #define GATE_SCLK_CAM 0xc820
+ #define GATE_IP_CAM 0xc920
+ #define GATE_IP_TV 0xc924
+@@ -1097,6 +1098,7 @@ static struct samsung_gate_clock exynos4
+ 0),
+ GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
+ 0),
++ GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
+ GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
+ GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
+ GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
--- /dev/null
+From d31ff5f7f3b142b8d1ebb3da89187c54cdf2bc71 Mon Sep 17 00:00:00 2001
+From: "Damien.Horsley" <Damien.Horsley@imgtec.com>
+Date: Wed, 26 Aug 2015 17:11:40 +0100
+Subject: clk: pistachio: correct critical clock list
+
+From: "Damien.Horsley" <Damien.Horsley@imgtec.com>
+
+commit d31ff5f7f3b142b8d1ebb3da89187c54cdf2bc71 upstream.
+
+Current critical clock list for pistachio enables
+only mips and sys clocks by default but there are
+also other clocks that are not claimed by anyone and
+needs to be enabled by default.
+
+This patch updates the critical clocks that need
+to be enabled by default.
+
+Add a separate struct to distinguish the critical clocks
+as listed:
+1.) core clocks:
+ a.) mips clock
+2.) peripheral system clocks:
+ a.) sys clock
+ b.) sys_bus clock
+ c.) DDR clock
+ d.) ROM clock
+
+Fixes: b35d7c33419c("CLK: Pistachio: Register core clocks")
+Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
+Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
+Signed-off-by: Damien.Horsley <Damien.Horsley@imgtec.com>
+Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/pistachio/clk-pistachio.c | 19 ++++++++++++++-----
+ 1 file changed, 14 insertions(+), 5 deletions(-)
+
+--- a/drivers/clk/pistachio/clk-pistachio.c
++++ b/drivers/clk/pistachio/clk-pistachio.c
+@@ -159,9 +159,15 @@ PNAME(mux_debug) = { "mips_pll_mux", "rp
+ "wifi_pll_mux", "bt_pll_mux" };
+ static u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };
+
+-static unsigned int pistachio_critical_clks[] __initdata = {
+- CLK_MIPS,
+- CLK_PERIPH_SYS,
++static unsigned int pistachio_critical_clks_core[] __initdata = {
++ CLK_MIPS
++};
++
++static unsigned int pistachio_critical_clks_sys[] __initdata = {
++ PERIPH_CLK_SYS,
++ PERIPH_CLK_SYS_BUS,
++ PERIPH_CLK_DDR,
++ PERIPH_CLK_ROM,
+ };
+
+ static void __init pistachio_clk_init(struct device_node *np)
+@@ -193,8 +199,8 @@ static void __init pistachio_clk_init(st
+
+ pistachio_clk_register_provider(p);
+
+- pistachio_clk_force_enable(p, pistachio_critical_clks,
+- ARRAY_SIZE(pistachio_critical_clks));
++ pistachio_clk_force_enable(p, pistachio_critical_clks_core,
++ ARRAY_SIZE(pistachio_critical_clks_core));
+ }
+ CLK_OF_DECLARE(pistachio_clk, "img,pistachio-clk", pistachio_clk_init);
+
+@@ -261,6 +267,9 @@ static void __init pistachio_clk_periph_
+ ARRAY_SIZE(pistachio_periph_gates));
+
+ pistachio_clk_register_provider(p);
++
++ pistachio_clk_force_enable(p, pistachio_critical_clks_sys,
++ ARRAY_SIZE(pistachio_critical_clks_sys));
+ }
+ CLK_OF_DECLARE(pistachio_clk_periph, "img,pistachio-clk-periph",
+ pistachio_clk_periph_init);
--- /dev/null
+From 093affb009a3d87848e51217cd1a06ce1135633f Mon Sep 17 00:00:00 2001
+From: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
+Date: Wed, 26 Aug 2015 17:11:37 +0100
+Subject: clk: pistachio: Fix 32bit integer overflows
+
+From: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
+
+commit 093affb009a3d87848e51217cd1a06ce1135633f upstream.
+
+This commit fixes 32bit integer overflows throughout the pll driver
+(i.e. wherever the result of integer multiplication may exceed the
+range of u32).
+
+One of the functions affected by this problem is .recalc_rate. It
+returns incorrect rate for some pll settings (not for all though)
+which in turn results in the incorrect rate setup of pll's child
+clocks.
+
+Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
+Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
+Signed-off-by: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
+Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/pistachio/clk-pll.c | 26 ++++++++++++--------------
+ drivers/clk/pistachio/clk.h | 14 +++++++-------
+ 2 files changed, 19 insertions(+), 21 deletions(-)
+
+--- a/drivers/clk/pistachio/clk-pll.c
++++ b/drivers/clk/pistachio/clk-pll.c
+@@ -88,12 +88,10 @@ static inline void pll_lock(struct pista
+ cpu_relax();
+ }
+
+-static inline u32 do_div_round_closest(u64 dividend, u32 divisor)
++static inline u64 do_div_round_closest(u64 dividend, u64 divisor)
+ {
+ dividend += divisor / 2;
+- do_div(dividend, divisor);
+-
+- return dividend;
++ return div64_u64(dividend, divisor);
+ }
+
+ static inline struct pistachio_clk_pll *to_pistachio_pll(struct clk_hw *hw)
+@@ -173,7 +171,7 @@ static int pll_gf40lp_frac_set_rate(stru
+ struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
+ struct pistachio_pll_rate_table *params;
+ int enabled = pll_gf40lp_frac_is_enabled(hw);
+- u32 val, vco, old_postdiv1, old_postdiv2;
++ u64 val, vco, old_postdiv1, old_postdiv2;
+ const char *name = __clk_get_name(hw->clk);
+
+ if (rate < MIN_OUTPUT_FRAC || rate > MAX_OUTPUT_FRAC)
+@@ -183,17 +181,17 @@ static int pll_gf40lp_frac_set_rate(stru
+ if (!params || !params->refdiv)
+ return -EINVAL;
+
+- vco = params->fref * params->fbdiv / params->refdiv;
++ vco = div64_u64(params->fref * params->fbdiv, params->refdiv);
+ if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC)
+- pr_warn("%s: VCO %u is out of range %lu..%lu\n", name, vco,
++ pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco,
+ MIN_VCO_FRAC_FRAC, MAX_VCO_FRAC_FRAC);
+
+- val = params->fref / params->refdiv;
++ val = div64_u64(params->fref, params->refdiv);
+ if (val < MIN_PFD)
+- pr_warn("%s: PFD %u is too low (min %lu)\n",
++ pr_warn("%s: PFD %llu is too low (min %lu)\n",
+ name, val, MIN_PFD);
+ if (val > vco / 16)
+- pr_warn("%s: PFD %u is too high (max %u)\n",
++ pr_warn("%s: PFD %llu is too high (max %llu)\n",
+ name, val, vco / 16);
+
+ val = pll_readl(pll, PLL_CTRL1);
+@@ -237,8 +235,7 @@ static unsigned long pll_gf40lp_frac_rec
+ unsigned long parent_rate)
+ {
+ struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
+- u32 val, prediv, fbdiv, frac, postdiv1, postdiv2;
+- u64 rate = parent_rate;
++ u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate;
+
+ val = pll_readl(pll, PLL_CTRL1);
+ prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK;
+@@ -251,6 +248,7 @@ static unsigned long pll_gf40lp_frac_rec
+ PLL_FRAC_CTRL2_POSTDIV2_MASK;
+ frac = (val >> PLL_FRAC_CTRL2_FRAC_SHIFT) & PLL_FRAC_CTRL2_FRAC_MASK;
+
++ rate = parent_rate;
+ rate *= (fbdiv << 24) + frac;
+ rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24);
+
+@@ -325,12 +323,12 @@ static int pll_gf40lp_laint_set_rate(str
+ if (!params || !params->refdiv)
+ return -EINVAL;
+
+- vco = params->fref * params->fbdiv / params->refdiv;
++ vco = div_u64(params->fref * params->fbdiv, params->refdiv);
+ if (vco < MIN_VCO_LA || vco > MAX_VCO_LA)
+ pr_warn("%s: VCO %u is out of range %lu..%lu\n", name, vco,
+ MIN_VCO_LA, MAX_VCO_LA);
+
+- val = params->fref / params->refdiv;
++ val = div_u64(params->fref, params->refdiv);
+ if (val < MIN_PFD)
+ pr_warn("%s: PFD %u is too low (min %lu)\n",
+ name, val, MIN_PFD);
+--- a/drivers/clk/pistachio/clk.h
++++ b/drivers/clk/pistachio/clk.h
+@@ -95,13 +95,13 @@ struct pistachio_fixed_factor {
+ }
+
+ struct pistachio_pll_rate_table {
+- unsigned long fref;
+- unsigned long fout;
+- unsigned int refdiv;
+- unsigned int fbdiv;
+- unsigned int postdiv1;
+- unsigned int postdiv2;
+- unsigned int frac;
++ unsigned long long fref;
++ unsigned long long fout;
++ unsigned long long refdiv;
++ unsigned long long fbdiv;
++ unsigned long long postdiv1;
++ unsigned long long postdiv2;
++ unsigned long long frac;
+ };
+
+ enum pistachio_pll_type {
--- /dev/null
+From e53f21c761d141bbcbce06e9ddab3b4e0a828f2c Mon Sep 17 00:00:00 2001
+From: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
+Date: Wed, 26 Aug 2015 17:11:38 +0100
+Subject: clk: pistachio: Fix override of clk-pll settings from boot loader
+
+From: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
+
+commit e53f21c761d141bbcbce06e9ddab3b4e0a828f2c upstream.
+
+PLL enable callbacks are overriding PLL mode (int/frac) and
+Noise reduction (on/off) settings set by the boot loader which
+results in the incorrect clock rate.
+
+PLL mode and noise reduction are defined by the DSMPD and DACPD bits
+of the PLL control register. PLL .enable() callbacks enable PLL
+by deasserting all power-down bits of the PLL control register,
+including DSMPD and DACPD bits, which is not necessary since
+these bits don't actually enable/disable PLL.
+
+This commit fixes the problem by removing DSMPD and DACPD bits
+from the "PLL enable" mask.
+
+Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
+Reviewed-by: Andrew Bresitcker <abrestic@chromium.org>
+Signed-off-by: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
+Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/pistachio/clk-pll.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/pistachio/clk-pll.c
++++ b/drivers/clk/pistachio/clk-pll.c
+@@ -134,8 +134,7 @@ static int pll_gf40lp_frac_enable(struct
+ u32 val;
+
+ val = pll_readl(pll, PLL_CTRL3);
+- val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_DACPD |
+- PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD |
++ val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD |
+ PLL_FRAC_CTRL3_FOUT4PHASEPD | PLL_FRAC_CTRL3_FOUTVCOPD);
+ pll_writel(pll, val, PLL_CTRL3);
+
+@@ -277,7 +276,7 @@ static int pll_gf40lp_laint_enable(struc
+ u32 val;
+
+ val = pll_readl(pll, PLL_CTRL1);
+- val &= ~(PLL_INT_CTRL1_PD | PLL_INT_CTRL1_DSMPD |
++ val &= ~(PLL_INT_CTRL1_PD |
+ PLL_INT_CTRL1_FOUTPOSTDIVPD | PLL_INT_CTRL1_FOUTVCOPD);
+ pll_writel(pll, val, PLL_CTRL1);
+
--- /dev/null
+From 7937c6c57e0da7bffa7b10bac23f230c77523e35 Mon Sep 17 00:00:00 2001
+From: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
+Date: Wed, 26 Aug 2015 17:11:39 +0100
+Subject: clk: pistachio: Fix PLL rate calculation in integer mode
+
+From: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
+
+commit 7937c6c57e0da7bffa7b10bac23f230c77523e35 upstream.
+
+.recalc_rate callback for the fractional PLL doesn't take operating
+mode into account when calculating PLL rate. This results in
+the incorrect PLL rates when PLL is operating in integer mode.
+
+Operating mode of fractional PLL is based on the value of the
+fractional divider. Currently it assumes that the PLL will always
+be configured in fractional mode which may not be
+the case. This may result in the wrong output frequency.
+
+Also vco was calculated based on the current operating mode which
+makes no sense because .set_rate is setting operating mode. Instead,
+vco should be calculated using PLL settings that are about to be set.
+
+Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver")
+Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
+Signed-off-by: Zdenko Pulitika <zdenko.pulitika@imgtec.com>
+Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/pistachio/clk-pll.c | 48 ++++++++++++++++++++++++++++++++++++++--
+ 1 file changed, 46 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/pistachio/clk-pll.c
++++ b/drivers/clk/pistachio/clk-pll.c
+@@ -65,6 +65,12 @@
+ #define MIN_OUTPUT_FRAC 12000000UL
+ #define MAX_OUTPUT_FRAC 1600000000UL
+
++/* Fractional PLL operating modes */
++enum pll_mode {
++ PLL_MODE_FRAC,
++ PLL_MODE_INT,
++};
++
+ struct pistachio_clk_pll {
+ struct clk_hw hw;
+ void __iomem *base;
+@@ -99,6 +105,29 @@ static inline struct pistachio_clk_pll *
+ return container_of(hw, struct pistachio_clk_pll, hw);
+ }
+
++static inline enum pll_mode pll_frac_get_mode(struct clk_hw *hw)
++{
++ struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
++ u32 val;
++
++ val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD;
++ return val ? PLL_MODE_INT : PLL_MODE_FRAC;
++}
++
++static inline void pll_frac_set_mode(struct clk_hw *hw, enum pll_mode mode)
++{
++ struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
++ u32 val;
++
++ val = pll_readl(pll, PLL_CTRL3);
++ if (mode == PLL_MODE_INT)
++ val |= PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD;
++ else
++ val &= ~(PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD);
++
++ pll_writel(pll, val, PLL_CTRL3);
++}
++
+ static struct pistachio_pll_rate_table *
+ pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,
+ unsigned long fout)
+@@ -180,7 +209,11 @@ static int pll_gf40lp_frac_set_rate(stru
+ if (!params || !params->refdiv)
+ return -EINVAL;
+
+- vco = div64_u64(params->fref * params->fbdiv, params->refdiv);
++ /* calculate vco */
++ vco = params->fref;
++ vco *= (params->fbdiv << 24) + params->frac;
++ vco = div64_u64(vco, params->refdiv << 24);
++
+ if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC)
+ pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco,
+ MIN_VCO_FRAC_FRAC, MAX_VCO_FRAC_FRAC);
+@@ -224,6 +257,12 @@ static int pll_gf40lp_frac_set_rate(stru
+ (params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT);
+ pll_writel(pll, val, PLL_CTRL2);
+
++ /* set operating mode */
++ if (params->frac)
++ pll_frac_set_mode(hw, PLL_MODE_FRAC);
++ else
++ pll_frac_set_mode(hw, PLL_MODE_INT);
++
+ if (enabled)
+ pll_lock(pll);
+
+@@ -247,8 +286,13 @@ static unsigned long pll_gf40lp_frac_rec
+ PLL_FRAC_CTRL2_POSTDIV2_MASK;
+ frac = (val >> PLL_FRAC_CTRL2_FRAC_SHIFT) & PLL_FRAC_CTRL2_FRAC_MASK;
+
++ /* get operating mode (int/frac) and calculate rate accordingly */
+ rate = parent_rate;
+- rate *= (fbdiv << 24) + frac;
++ if (pll_frac_get_mode(hw) == PLL_MODE_FRAC)
++ rate *= (fbdiv << 24) + frac;
++ else
++ rate *= (fbdiv << 24);
++
+ rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24);
+
+ return rate;
--- /dev/null
+From 4b5fb7dc9096d949a22651370bb6bf11f21edb30 Mon Sep 17 00:00:00 2001
+From: Robert Jarzmik <robert.jarzmik@free.fr>
+Date: Sun, 12 Jul 2015 22:49:53 +0200
+Subject: clk: pxa: fix core frequency reporting unit
+
+From: Robert Jarzmik <robert.jarzmik@free.fr>
+
+commit 4b5fb7dc9096d949a22651370bb6bf11f21edb30 upstream.
+
+Legacy drivers which are not yet ported, such as cpufreq-pxa[23]xx, rely
+on pxaXXx_get_clk_frequency_khz() to find the CPU core frequency.
+
+This reporting was broken because the expected unit is kHz and not
+Hz. Fix the reporting for pxa25x, pxa27x and pxa3xx.
+
+Fixes: fe7710fae477 ("clk: add pxa25x clock drivers")
+Fixes: d40670dc6169 ("clk: add pxa27x clock drivers")
+Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver")
+Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/pxa/clk-pxa25x.c | 2 +-
+ drivers/clk/pxa/clk-pxa27x.c | 2 +-
+ drivers/clk/pxa/clk-pxa3xx.c | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/pxa/clk-pxa25x.c
++++ b/drivers/clk/pxa/clk-pxa25x.c
+@@ -79,7 +79,7 @@ unsigned int pxa25x_get_clk_frequency_kh
+ clks[3] / 1000000, (clks[3] % 1000000) / 10000);
+ }
+
+- return (unsigned int)clks[0];
++ return (unsigned int)clks[0] / KHz;
+ }
+
+ static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
+--- a/drivers/clk/pxa/clk-pxa27x.c
++++ b/drivers/clk/pxa/clk-pxa27x.c
+@@ -80,7 +80,7 @@ unsigned int pxa27x_get_clk_frequency_kh
+ pr_info("System bus clock: %ld.%02ldMHz\n",
+ clks[4] / 1000000, (clks[4] % 1000000) / 10000);
+ }
+- return (unsigned int)clks[0];
++ return (unsigned int)clks[0] / KHz;
+ }
+
+ bool pxa27x_is_ppll_disabled(void)
+--- a/drivers/clk/pxa/clk-pxa3xx.c
++++ b/drivers/clk/pxa/clk-pxa3xx.c
+@@ -78,7 +78,7 @@ unsigned int pxa3xx_get_clk_frequency_kh
+ pr_info("System bus clock: %ld.%02ldMHz\n",
+ clks[4] / 1000000, (clks[4] % 1000000) / 10000);
+ }
+- return (unsigned int)clks[0];
++ return (unsigned int)clks[0] / KHz;
+ }
+
+ static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw,
--- /dev/null
+From 1c4b4b0eb1909010b8ebda1ef208bf3ed62e7487 Mon Sep 17 00:00:00 2001
+From: Georgi Djakov <georgi.djakov@linaro.org>
+Date: Tue, 25 Aug 2015 15:27:43 +0300
+Subject: clk: qcom: Fix MSM8916 prng clock enable bit
+
+From: Georgi Djakov <georgi.djakov@linaro.org>
+
+commit 1c4b4b0eb1909010b8ebda1ef208bf3ed62e7487 upstream.
+
+Fix the enable bit of the pseudorandom number generator clock.
+
+Reported-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
+Fixes: 3966fab8b6ab "clk: qcom: Add MSM8916 Global Clock Controller support"
+Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/qcom/gcc-msm8916.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/gcc-msm8916.c
++++ b/drivers/clk/qcom/gcc-msm8916.c
+@@ -2278,7 +2278,7 @@ static struct clk_branch gcc_prng_ahb_cl
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x45004,
+- .enable_mask = BIT(0),
++ .enable_mask = BIT(8),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .parent_names = (const char *[]){
--- /dev/null
+From d7a304e9d018c99dda80f4c16ec0fe817b5be4a1 Mon Sep 17 00:00:00 2001
+From: Stephen Boyd <sboyd@codeaurora.org>
+Date: Tue, 14 Jul 2015 16:57:29 -0700
+Subject: clk: qcom: Set CLK_SET_RATE_PARENT on ce1 clocks
+
+From: Stephen Boyd <sboyd@codeaurora.org>
+
+commit d7a304e9d018c99dda80f4c16ec0fe817b5be4a1 upstream.
+
+The other ce clocks have the flag set, but ce1 doesn't, so
+clk_set_rate() doesn't propagate up the tree to the ce1_src_clk.
+Set the flag as this is supported.
+
+Reported-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
+Tested-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
+Fixes: 02824653200b ("clk: qcom: Add APQ8084 Global Clock Controller support")
+Fixes: d33faa9ead8d ("clk: qcom: Add support for MSM8974's global clock controller (GCC)")
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/qcom/gcc-apq8084.c | 1 +
+ drivers/clk/qcom/gcc-msm8974.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-apq8084.c
++++ b/drivers/clk/qcom/gcc-apq8084.c
+@@ -2105,6 +2105,7 @@ static struct clk_branch gcc_ce1_clk = {
+ "ce1_clk_src",
+ },
+ .num_parents = 1,
++ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+--- a/drivers/clk/qcom/gcc-msm8974.c
++++ b/drivers/clk/qcom/gcc-msm8974.c
+@@ -1783,6 +1783,7 @@ static struct clk_branch gcc_ce1_clk = {
+ "ce1_clk_src",
+ },
+ .num_parents = 1,
++ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
--- /dev/null
+From 4791eb61dbe8100ccac59fecfac9d93a15db1447 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Thu, 18 Jun 2015 16:18:28 +0200
+Subject: clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac
+
+From: Heiko Stuebner <heiko@sntech.de>
+
+commit 4791eb61dbe8100ccac59fecfac9d93a15db1447 upstream.
+
+The dwmac ethernet controller on the rk3288 supports phys connected
+via rgmii and rmii. With rgmii phys it is expected that the mac clock
+is provided externally while with rmii phys the clock can be external
+but also generated from the plls. In the later case it of course needs
+be at 50MHz, which gets set from the dwmac_rk driver.
+As most devices use a rgmii phy it never surfaced so far that the mac
+clk mux, doesn't go up one lever to the pll clock in the rmii case with
+internal clock generation, as it is missing the CLK_SET_RATE_PARENT flag,
+and thus will not set the correct frequency in most cases.
+
+Fixes: b9e4ba541607 ("clk: rockchip: add clock controller for rk3288")
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/rockchip/clk-rk3288.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/rockchip/clk-rk3288.c
++++ b/drivers/clk/rockchip/clk-rk3288.c
+@@ -578,7 +578,7 @@ static struct rockchip_clk_branch rk3288
+ COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
+ RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3288_CLKGATE_CON(2), 5, GFLAGS),
+- MUX(SCLK_MAC, "mac_clk", mux_mac_p, 0,
++ MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
+ RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
+ GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
+ RK3288_CLKGATE_CON(5), 3, GFLAGS),
--- /dev/null
+From ba30011577330b7e29ecb5916d89c6db9fbc5b3d Mon Sep 17 00:00:00 2001
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+Date: Wed, 12 Aug 2015 10:58:22 +0200
+Subject: clk: s5pv210: add missing call to
+ samsung_clk_of_add_provider()
+
+From: Marek Szyprowski <m.szyprowski@samsung.com>
+
+commit ba30011577330b7e29ecb5916d89c6db9fbc5b3d upstream.
+
+Commit d5e136a21b2028fb1f45143ea7112d5869bfc6c7 ("clk: samsung: Register
+clk provider only after registering its all clocks", merged to v3.17-rc1)
+modified a way that driver registers registers to core framework. This
+change has not been applied to s5pv210 clocks driver, which has been
+merged in parallel to that commit. This patch adds a missing call to
+samsung_clk_of_add_provider(), so the driver is operational again.
+
+Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
+Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
+Signed-off-by: Michael Turquette <mturquette@baylibre.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/samsung/clk-s5pv210.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/clk/samsung/clk-s5pv210.c
++++ b/drivers/clk/samsung/clk-s5pv210.c
+@@ -828,6 +828,8 @@ static void __init __s5pv210_clk_init(st
+
+ s5pv210_clk_sleep_init();
+
++ samsung_clk_of_add_provider(np, ctx);
++
+ pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
+ "\tmout_epll = %ld, mout_vpll = %ld\n",
+ is_s5p6442 ? "S5P6442" : "S5PV210",
--- /dev/null
+From 3294bee87091be5f179474f6c39d1d87769635e2 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Wed, 29 Jul 2015 13:17:06 +0300
+Subject: clk: versatile: off by one in clk_sp810_timerclken_of_get()
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+commit 3294bee87091be5f179474f6c39d1d87769635e2 upstream.
+
+The ">" should be ">=" or we end up reading beyond the end of the array.
+
+Fixes: 6e973d2c4385 ('clk: vexpress: Add separate SP810 driver')
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Acked-by: Pawel Moll <pawel.moll@arm.com>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/versatile/clk-sp810.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/versatile/clk-sp810.c
++++ b/drivers/clk/versatile/clk-sp810.c
+@@ -128,8 +128,8 @@ static struct clk *clk_sp810_timerclken_
+ {
+ struct clk_sp810 *sp810 = data;
+
+- if (WARN_ON(clkspec->args_count != 1 || clkspec->args[0] >
+- ARRAY_SIZE(sp810->timerclken)))
++ if (WARN_ON(clkspec->args_count != 1 ||
++ clkspec->args[0] >= ARRAY_SIZE(sp810->timerclken)))
+ return NULL;
+
+ return sp810->timerclken[clkspec->args[0]].clk;
--- /dev/null
+From 932c435caba8a2ce473a91753bad0173269ef334 Mon Sep 17 00:00:00 2001
+From: Mark Rustad <mark.d.rustad@intel.com>
+Date: Mon, 13 Jul 2015 11:40:02 -0700
+Subject: PCI: Add dev_flags bit to access VPD through function 0
+
+From: Mark Rustad <mark.d.rustad@intel.com>
+
+commit 932c435caba8a2ce473a91753bad0173269ef334 upstream.
+
+Add a dev_flags bit, PCI_DEV_FLAGS_VPD_REF_F0, to access VPD through
+function 0 to provide VPD access on other functions. This is for hardware
+devices that provide copies of the same VPD capability registers in
+multiple functions. Because the kernel expects that each function has its
+own registers, both the locking and the state tracking are affected by VPD
+accesses to different functions.
+
+On such devices for example, if a VPD write is performed on function 0,
+*any* later attempt to read VPD from any other function of that device will
+hang. This has to do with how the kernel tracks the expected value of the
+F bit per function.
+
+Concurrent accesses to different functions of the same device can not only
+hang but also corrupt both read and write VPD data.
+
+When hangs occur, typically the error message:
+
+ vpd r/w failed. This is likely a firmware bug on this device.
+
+will be seen.
+
+Never set this bit on function 0 or there will be an infinite recursion.
+
+Signed-off-by: Mark Rustad <mark.d.rustad@intel.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Alexander Duyck <alexander.h.duyck@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/access.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++-
+ include/linux/pci.h | 2 +
+ 2 files changed, 62 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/access.c
++++ b/drivers/pci/access.c
+@@ -439,6 +439,56 @@ static const struct pci_vpd_ops pci_vpd_
+ .release = pci_vpd_pci22_release,
+ };
+
++static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
++ void *arg)
++{
++ struct pci_dev *tdev = pci_get_slot(dev->bus, PCI_SLOT(dev->devfn));
++ ssize_t ret;
++
++ if (!tdev)
++ return -ENODEV;
++
++ ret = pci_read_vpd(tdev, pos, count, arg);
++ pci_dev_put(tdev);
++ return ret;
++}
++
++static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
++ const void *arg)
++{
++ struct pci_dev *tdev = pci_get_slot(dev->bus, PCI_SLOT(dev->devfn));
++ ssize_t ret;
++
++ if (!tdev)
++ return -ENODEV;
++
++ ret = pci_write_vpd(tdev, pos, count, arg);
++ pci_dev_put(tdev);
++ return ret;
++}
++
++static const struct pci_vpd_ops pci_vpd_f0_ops = {
++ .read = pci_vpd_f0_read,
++ .write = pci_vpd_f0_write,
++ .release = pci_vpd_pci22_release,
++};
++
++static int pci_vpd_f0_dev_check(struct pci_dev *dev)
++{
++ struct pci_dev *tdev = pci_get_slot(dev->bus, PCI_SLOT(dev->devfn));
++ int ret = 0;
++
++ if (!tdev)
++ return -ENODEV;
++ if (!tdev->vpd || !tdev->multifunction ||
++ dev->class != tdev->class || dev->vendor != tdev->vendor ||
++ dev->device != tdev->device)
++ ret = -ENODEV;
++
++ pci_dev_put(tdev);
++ return ret;
++}
++
+ int pci_vpd_pci22_init(struct pci_dev *dev)
+ {
+ struct pci_vpd_pci22 *vpd;
+@@ -447,12 +497,21 @@ int pci_vpd_pci22_init(struct pci_dev *d
+ cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
+ if (!cap)
+ return -ENODEV;
++ if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
++ int ret = pci_vpd_f0_dev_check(dev);
++
++ if (ret)
++ return ret;
++ }
+ vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
+ if (!vpd)
+ return -ENOMEM;
+
+ vpd->base.len = PCI_VPD_PCI22_SIZE;
+- vpd->base.ops = &pci_vpd_pci22_ops;
++ if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
++ vpd->base.ops = &pci_vpd_f0_ops;
++ else
++ vpd->base.ops = &pci_vpd_pci22_ops;
+ mutex_init(&vpd->lock);
+ vpd->cap = cap;
+ vpd->busy = false;
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -180,6 +180,8 @@ enum pci_dev_flags {
+ PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
+ /* Do not use PM reset even if device advertises NoSoftRst- */
+ PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
++ /* Get VPD from function 0 VPD */
++ PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
+ };
+
+ enum pci_irq_reroute_variant {
--- /dev/null
+From 7aa6ca4d39edf01f997b9e02cf6d2fdeb224f351 Mon Sep 17 00:00:00 2001
+From: Mark Rustad <mark.d.rustad@intel.com>
+Date: Mon, 13 Jul 2015 11:40:07 -0700
+Subject: PCI: Add VPD function 0 quirk for Intel Ethernet devices
+
+From: Mark Rustad <mark.d.rustad@intel.com>
+
+commit 7aa6ca4d39edf01f997b9e02cf6d2fdeb224f351 upstream.
+
+Set the PCI_DEV_FLAGS_VPD_REF_F0 flag on all Intel Ethernet device
+functions other than function 0, so that on multi-function devices, we will
+always read VPD from function 0 instead of from the other functions.
+
+[bhelgaas: changelog]
+Signed-off-by: Mark Rustad <mark.d.rustad@intel.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Alexander Duyck <alexander.h.duyck@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -1894,6 +1894,15 @@ static void quirk_netmos(struct pci_dev
+ DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
+ PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
+
++static void quirk_f0_vpd_link(struct pci_dev *dev)
++{
++ if (!dev->multifunction || !PCI_FUNC(dev->devfn))
++ return;
++ dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
++}
++DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
++ PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
++
+ static void quirk_e100_interrupt(struct pci_dev *dev)
+ {
+ u16 command, pmcsr;
--- /dev/null
+From 91f15fb30c77d4a0d0d9b97e5cec647650853145 Mon Sep 17 00:00:00 2001
+From: Zhang Rui <rui.zhang@intel.com>
+Date: Mon, 24 Aug 2015 15:27:11 -0500
+Subject: PCI: Disable async suspend/resume for JMicron multi-function SATA/AHCI
+
+From: Zhang Rui <rui.zhang@intel.com>
+
+commit 91f15fb30c77d4a0d0d9b97e5cec647650853145 upstream.
+
+On multi-function JMicron SATA/PATA/AHCI devices, the PATA controller at
+function 1 doesn't work if it is powered on before the SATA controller at
+function 0. The result is that PATA doesn't work after resume, and we
+print messages like this:
+
+ pata_jmicron 0000:02:00.1: Refused to change power state, currently in D3
+ irq 17: nobody cared (try booting with the "irqpoll" option)
+
+Async resume was introduced in v3.15 by 76569faa62c4 ("PM / sleep:
+Asynchronous threads for resume_noirq"). Prior to that, we powered on
+the functions in order, so this problem shouldn't happen.
+
+e6b7e41cdd8c ("ata: Disabling the async PM for JMicron chip 363/361")
+solved the problem for JMicron 361 and 363 devices. With async suspend
+disabled, we always power on function 0 before function 1.
+
+Barto then reported the same problem with a JMicron 368 (see comment #57 in
+the bugzilla).
+
+Rather than extending the blacklist piecemeal, disable async suspend for
+all JMicron multi-function SATA/PATA/AHCI devices.
+
+This quirk could stay in the ahci and pata_jmicron drivers, but it's likely
+the problem will occur even if pata_jmicron isn't loaded until after the
+suspend/resume. Making it a PCI quirk ensures that we'll preserve the
+power-on order even if the drivers aren't loaded.
+
+[bhelgaas: changelog, limit to multi-function, limit to IDE/ATA]
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=81551
+Reported-and-tested-by: Barto <mister.freeman@laposte.net>
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/ata/ahci.c | 13 +------------
+ drivers/ata/pata_jmicron.c | 12 ------------
+ drivers/pci/quirks.c | 12 ++++++++++++
+ 3 files changed, 13 insertions(+), 24 deletions(-)
+
+--- a/drivers/ata/ahci.c
++++ b/drivers/ata/ahci.c
+@@ -351,6 +351,7 @@ static const struct pci_device_id ahci_p
+ /* JMicron 362B and 362C have an AHCI function with IDE class code */
+ { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
+ { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
++ /* May need to update quirk_jmicron_async_suspend() for additions */
+
+ /* ATI */
+ { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
+@@ -1451,18 +1452,6 @@ static int ahci_init_one(struct pci_dev
+ else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
+ ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
+
+- /*
+- * The JMicron chip 361/363 contains one SATA controller and one
+- * PATA controller,for powering on these both controllers, we must
+- * follow the sequence one by one, otherwise one of them can not be
+- * powered on successfully, so here we disable the async suspend
+- * method for these chips.
+- */
+- if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
+- (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
+- pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
+- device_disable_async_suspend(&pdev->dev);
+-
+ /* acquire resources */
+ rc = pcim_enable_device(pdev);
+ if (rc)
+--- a/drivers/ata/pata_jmicron.c
++++ b/drivers/ata/pata_jmicron.c
+@@ -143,18 +143,6 @@ static int jmicron_init_one (struct pci_
+ };
+ const struct ata_port_info *ppi[] = { &info, NULL };
+
+- /*
+- * The JMicron chip 361/363 contains one SATA controller and one
+- * PATA controller,for powering on these both controllers, we must
+- * follow the sequence one by one, otherwise one of them can not be
+- * powered on successfully, so here we disable the async suspend
+- * method for these chips.
+- */
+- if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
+- (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
+- pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
+- device_disable_async_suspend(&pdev->dev);
+-
+ return ata_pci_bmdma_init_one(pdev, ppi, &jmicron_sht, NULL, 0);
+ }
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -1569,6 +1569,18 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDO
+
+ #endif
+
++static void quirk_jmicron_async_suspend(struct pci_dev *dev)
++{
++ if (dev->multifunction) {
++ device_disable_async_suspend(&dev->dev);
++ dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
++ }
++}
++DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
++DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
++
+ #ifdef CONFIG_X86_IO_APIC
+ static void quirk_alder_ioapic(struct pci_dev *pdev)
+ {
--- /dev/null
+From d1541dc977d376406f4584d8eb055488655c98ec Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Fri, 19 Jun 2015 15:58:24 -0500
+Subject: PCI: Fix TI816X class code quirk
+
+From: Bjorn Helgaas <bhelgaas@google.com>
+
+commit d1541dc977d376406f4584d8eb055488655c98ec upstream.
+
+In fixup_ti816x_class(), we assigned "class = PCI_CLASS_MULTIMEDIA_VIDEO".
+But PCI_CLASS_MULTIMEDIA_VIDEO is only the two-byte base class/sub-class
+and needs to be shifted to make space for the low-order interface byte.
+
+Shift PCI_CLASS_MULTIMEDIA_VIDEO to set the correct class code.
+
+Fixes: 63c4408074cb ("PCI: Add quirk for setting valid class for TI816X Endpoint")
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+CC: Hemant Pedanekar <hemantp@ti.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -2829,12 +2829,15 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IN
+
+ static void fixup_ti816x_class(struct pci_dev *dev)
+ {
++ u32 class = dev->class;
++
+ /* TI 816x devices do not have class code set when in PCIe boot mode */
+- dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
+- dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
++ dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
++ dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
++ class, dev->class);
+ }
+ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
+- PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
++ PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
+
+ /* Some PCIe devices do not work reliably with the claimed maximum
+ * payload size supported.
--- /dev/null
+From f4745a92781b872455f32feb01d1dce92aefcb6c Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Mon, 29 Jun 2015 22:13:38 +0100
+Subject: PM / clk: don't return int on __pm_clk_enable()
+
+From: Colin Ian King <colin.king@canonical.com>
+
+commit f4745a92781b872455f32feb01d1dce92aefcb6c upstream.
+
+Static analysis by cppcheck found an issue that was recently introduced by
+commit 471f7707b6f0b1 ("PM / clock_ops: make __pm_clk_enable more generic")
+where a return status in ret was not being initialised and garbage
+being returned when ce->status >= PCE_STATUS_ERROR.
+
+The fact that ret is not being checked by the caller and that
+ret is only used internally __pm_clk_enable() to check if clk_enable()
+was OK means we can ignore returning it instead turn
+__pm_clk_enable() into function with a void return.
+
+Fixes: 471f7707b6f0b1 ("PM / clock_ops: make __pm_clk_enable more generic")
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/base/power/clock_ops.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/base/power/clock_ops.c
++++ b/drivers/base/power/clock_ops.c
+@@ -38,7 +38,7 @@ struct pm_clock_entry {
+ * @dev: The device for the given clock
+ * @ce: PM clock entry corresponding to the clock.
+ */
+-static inline int __pm_clk_enable(struct device *dev, struct pm_clock_entry *ce)
++static inline void __pm_clk_enable(struct device *dev, struct pm_clock_entry *ce)
+ {
+ int ret;
+
+@@ -50,8 +50,6 @@ static inline int __pm_clk_enable(struct
+ dev_err(dev, "%s: failed to enable clk %p, error %d\n",
+ __func__, ce->clk, ret);
+ }
+-
+- return ret;
+ }
+
+ /**
--- /dev/null
+From e70e69bf205e6d1f742f1cf1935b155417c9e29a Mon Sep 17 00:00:00 2001
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+Date: Fri, 24 Jul 2015 15:58:28 +0900
+Subject: serial: 8250_uniphier: call clk_disable_unprepare() on failure path
+
+From: Masahiro Yamada <yamada.masahiro@socionext.com>
+
+commit e70e69bf205e6d1f742f1cf1935b155417c9e29a upstream.
+
+If serial8250_register_8250_port() fails, disable and unprepare the
+clock before exiting.
+
+Fixes: 1a8d2903cb6a ("serial: 8250_uniphier: add UniPhier serial driver")
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/tty/serial/8250/8250_uniphier.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/tty/serial/8250/8250_uniphier.c
++++ b/drivers/tty/serial/8250/8250_uniphier.c
+@@ -218,6 +218,7 @@ static int uniphier_uart_probe(struct pl
+ ret = serial8250_register_8250_port(&up);
+ if (ret < 0) {
+ dev_err(dev, "failed to register 8250 port\n");
++ clk_disable_unprepare(priv->clk);
+ return ret;
+ }
+
staging-comedi-usbduxsigma-don-t-clobber-ai_timer-in-command-test.patch
staging-comedi-usbduxsigma-don-t-clobber-ao_timer-in-command-test.patch
staging-unisys-allow-visorbus-to-autoload.patch
+pm-clk-don-t-return-int-on-__pm_clk_enable.patch
+clk-rockchip-rk3288-add-clk_set_rate_parent-to-sclk_mac.patch
+clk-exynos4-fix-wrong-clock-for-exynos4x12-adc.patch
+clk-s5pv210-add-missing-call-to.patch
+clk-pistachio-fix-32bit-integer-overflows.patch
+clk-pistachio-fix-override-of-clk-pll-settings-from-boot-loader.patch
+clk-pistachio-fix-pll-rate-calculation-in-integer-mode.patch
+clk-pistachio-correct-critical-clock-list.patch
+clk-versatile-off-by-one-in-clk_sp810_timerclken_of_get.patch
+clk-pxa-fix-core-frequency-reporting-unit.patch
+clk-qcom-set-clk_set_rate_parent-on-ce1-clocks.patch
+clk-qcom-fix-msm8916-prng-clock-enable-bit.patch
+pci-fix-ti816x-class-code-quirk.patch
+pci-add-dev_flags-bit-to-access-vpd-through-function-0.patch
+pci-add-vpd-function-0-quirk-for-intel-ethernet-devices.patch
+pci-disable-async-suspend-resume-for-jmicron-multi-function-sata-ahci.patch
+serial-8250_uniphier-call-clk_disable_unprepare-on-failure-path.patch
+tty-serial-8250_omap-do-not-use-rx-dma-if-pause-is-not-supported.patch
--- /dev/null
+From 830acf9e3044d4644f91b4418ef35a2094089946 Mon Sep 17 00:00:00 2001
+From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+Date: Fri, 14 Aug 2015 17:52:07 +0200
+Subject: tty: serial: 8250_omap: do not use RX DMA if pause is not supported
+
+From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+
+commit 830acf9e3044d4644f91b4418ef35a2094089946 upstream.
+
+The 8250-omap driver requires the DMA-engine driver to support the pause
+command in order to properly turn off programmed RX transfer before the
+driver stars manually reading from the FIFO.
+The lacking support of the requirement has been discovered recently. In
+order to stay safe here we disable RX-DMA completly on probe.
+The rx_dma_broken assignment on probe could be removed once we working
+pause function in omap-dma.
+
+Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/tty/serial/8250/8250_omap.c | 14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+--- a/drivers/tty/serial/8250/8250_omap.c
++++ b/drivers/tty/serial/8250/8250_omap.c
+@@ -100,6 +100,7 @@ struct omap8250_priv {
+ struct work_struct qos_work;
+ struct uart_8250_dma omap8250_dma;
+ spinlock_t rx_dma_lock;
++ bool rx_dma_broken;
+ };
+
+ static u32 uart_read(struct uart_8250_port *up, u32 reg)
+@@ -754,6 +755,7 @@ static void omap_8250_rx_dma_flush(struc
+ struct omap8250_priv *priv = p->port.private_data;
+ struct uart_8250_dma *dma = p->dma;
+ unsigned long flags;
++ int ret;
+
+ spin_lock_irqsave(&priv->rx_dma_lock, flags);
+
+@@ -762,7 +764,9 @@ static void omap_8250_rx_dma_flush(struc
+ return;
+ }
+
+- dmaengine_pause(dma->rxchan);
++ ret = dmaengine_pause(dma->rxchan);
++ if (WARN_ON_ONCE(ret))
++ priv->rx_dma_broken = true;
+
+ spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
+
+@@ -806,6 +810,9 @@ static int omap_8250_rx_dma(struct uart_
+ break;
+ }
+
++ if (priv->rx_dma_broken)
++ return -EINVAL;
++
+ spin_lock_irqsave(&priv->rx_dma_lock, flags);
+
+ if (dma->rx_running)
+@@ -1180,6 +1187,11 @@ static int omap8250_probe(struct platfor
+
+ if (of_machine_is_compatible("ti,am33xx"))
+ priv->habit |= OMAP_DMA_TX_KICK;
++ /*
++ * pause is currently not supported atleast on omap-sdma
++ * and edma on most earlier kernels.
++ */
++ priv->rx_dma_broken = true;
+ }
+ }
+ #endif
projects / thirdparty / kernel / stable-queue.git / commitdiff
