RISC-V: Add Shlcofideleg extension.

This patch add the RISC-V Shlcofideleg extension. It supports delegating
LCOFI interrupts(the count-overflow interrupts) to VS-mode.[1]

[1] https://riscv.github.io/riscv-isa-manual/snapshot/privileged

gcc/ChangeLog:

	* config/riscv/riscv-ext.def: New extension defs.
	* config/riscv/riscv-ext.opt: Ditto.
	* doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-shlocofideleg.c: New test.

Signed-off-by: Jiawei <jiawei@iscas.ac.cn>

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index d0adc2b6569bebd6df2f49871da41937604154ee..2d052c15206829c47b0a0ffecfd1b255324692ff 100644 (file)
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1610,6 +1610,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ shlcofideleg,
+  /* UPPERCASE_NAME */ SHLCOFIDELEG,
+  /* FULL_NAME */ "Delegating LCOFI interrupts to VS-mode",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"h"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sh,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ shtvala,
   /* UPPERCAE_NAME */ SHTVALA,

diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index c0dcde6529308cad79353c474e44785d22e695ab..e0314430ffb11dbf557140676b4e191fd6f7214d 100644 (file)
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -325,6 +325,8 @@ Mask(SHCOUNTERENW) Var(riscv_sh_subext)
 
 Mask(SHGATPA) Var(riscv_sh_subext)
 
+Mask(SHLCOFIDELEG) Var(riscv_sh_subext)
+
 Mask(SHTVALA) Var(riscv_sh_subext)
 
 Mask(SHVSTVALA) Var(riscv_sh_subext)

diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index e64c0d653a9f28eba2bfc2b6a7af2ad75d8bc219..e7e1f75cca6dba80f76ca299c0b77fd0ae0ae962 100644 (file)
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -474,6 +474,10 @@
 @tab 1.0
 @tab SvNNx4 mode supported for all modes supported by satp
 
+@item shlcofideleg
+@tab 1.0
+@tab Delegating LCOFI interrupts to VS-mode
+
 @item shtvala
 @tab 1.0
 @tab The htval register provides all needed values

diff --git a/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c b/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c
new file mode 100644 (file)
index 0000000..de9f9fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_shlcofideleg -mabi=lp64" } */
+int foo()
+{
+}