if SIM_ENABLE_ARCH_aarch64
include aarch64/local.mk
endif
-if SIM_ENABLE_ARCH_arm
-include arm/local.mk
-endif
if SIM_ENABLE_ARCH_avr
include avr/local.mk
endif
$(am__EXEEXT_32) $(am__EXEEXT_33) $(am__EXEEXT_34) \
$(am__EXEEXT_35) $(am__EXEEXT_36) $(am__EXEEXT_37) \
$(am__EXEEXT_38) $(am__EXEEXT_39) $(am__EXEEXT_40) \
- $(am__EXEEXT_41) $(am__EXEEXT_42)
+ $(am__EXEEXT_41)
EXTRA_PROGRAMS = $(am__EXEEXT_1) testsuite/common/bits-gen$(EXEEXT) \
testsuite/common/fpu-tst$(EXEEXT) $(am__EXEEXT_2) \
$(am__EXEEXT_3) $(am__EXEEXT_4) $(am__EXEEXT_5) \
testsuite/common/alu-tst$(EXEEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_3 = aarch64/libsim.a
@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_4 = aarch64/run
-@SIM_ENABLE_ARCH_arm_TRUE@am__append_5 = arm/libsim.a
-@SIM_ENABLE_ARCH_arm_TRUE@am__append_6 = arm/run
-@SIM_ENABLE_ARCH_avr_TRUE@am__append_7 = avr/libsim.a
-@SIM_ENABLE_ARCH_avr_TRUE@am__append_8 = avr/run
-@SIM_ENABLE_ARCH_bfin_TRUE@am__append_9 = bfin/libsim.a
-@SIM_ENABLE_ARCH_bfin_TRUE@am__append_10 = bfin/run
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_11 = bpf/libsim.a
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_12 = bpf/run
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_13 = cr16/libsim.a
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_14 = cr16/run
+@SIM_ENABLE_ARCH_avr_TRUE@am__append_5 = avr/libsim.a
+@SIM_ENABLE_ARCH_avr_TRUE@am__append_6 = avr/run
+@SIM_ENABLE_ARCH_bfin_TRUE@am__append_7 = bfin/libsim.a
+@SIM_ENABLE_ARCH_bfin_TRUE@am__append_8 = bfin/run
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_9 = bpf/libsim.a
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_10 = bpf/run
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_11 = cr16/libsim.a
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_12 = cr16/run
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_13 = cr16/simops.h
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_14 = cr16/gencode
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_15 = cr16/simops.h
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 = cr16/gencode
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_17 = cr16/simops.h
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 = $(cr16_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_19 = cris/libsim.a
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 = cris/run
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 = cris/rvdummy
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 = \
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 = $(cr16_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_17 = cris/libsim.a
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_18 = cris/run
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_19 = cris/rvdummy
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv10.h \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv32.h
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 = cris/engv10.h cris/engv32.h
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 = $(cris_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/libsim.a
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 = d10v/run
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 = cris/engv10.h cris/engv32.h
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 = $(cris_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_23 = d10v/libsim.a
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_24 = d10v/run
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/simops.h
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 = d10v/gencode
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_27 = d10v/simops.h
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = d10v/gencode
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 = d10v/simops.h
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_30 = $(d10v_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 = erc32/libsim.a
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_32 = erc32/run erc32/sis
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_33 = sim-%D-install-exec-local
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_34 = sim-erc32-uninstall-local
-@SIM_ENABLE_ARCH_examples_TRUE@am__append_35 = example-synacor/libsim.a
-@SIM_ENABLE_ARCH_examples_TRUE@am__append_36 = example-synacor/run
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 = frv/libsim.a
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_38 = frv/run
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 = frv/eng.h
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_40 = frv/eng.h
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_41 = $(frv_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_42 = ft32/libsim.a
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_43 = ft32/run
-@SIM_ENABLE_ARCH_h8300_TRUE@am__append_44 = h8300/libsim.a
-@SIM_ENABLE_ARCH_h8300_TRUE@am__append_45 = h8300/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 = iq2000/libsim.a
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = iq2000/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_48 = iq2000/eng.h
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_49 = iq2000/eng.h
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_50 = $(iq2000_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 = lm32/libsim.a
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_52 = lm32/run
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_53 = lm32/eng.h
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_54 = lm32/eng.h
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_55 = $(lm32_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 = m32c/libsim.a
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_57 = m32c/run
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_58 = m32c/opc2c
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_59 = \
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = $(d10v_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_29 = erc32/libsim.a
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_30 = erc32/run erc32/sis
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 = sim-%D-install-exec-local
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_32 = sim-erc32-uninstall-local
+@SIM_ENABLE_ARCH_examples_TRUE@am__append_33 = example-synacor/libsim.a
+@SIM_ENABLE_ARCH_examples_TRUE@am__append_34 = example-synacor/run
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_35 = frv/libsim.a
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_36 = frv/run
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 = frv/eng.h
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_38 = frv/eng.h
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 = $(frv_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_40 = ft32/libsim.a
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_41 = ft32/run
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_42 = h8300/libsim.a
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_43 = h8300/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_44 = iq2000/libsim.a
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_45 = iq2000/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 = iq2000/eng.h
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = iq2000/eng.h
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_48 = $(iq2000_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_49 = lm32/libsim.a
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_50 = lm32/run
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 = lm32/eng.h
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_52 = lm32/eng.h
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_53 = $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_54 = m32c/libsim.a
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_55 = m32c/run
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 = m32c/opc2c
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_57 = \
@SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 = m32r/libsim.a
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 = m32r/run
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_62 = \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_58 = m32r/libsim.a
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_59 = m32r/run
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_63 = m32r/eng.h m32r/engx.h m32r/eng2.h
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_64 = $(m32r_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 = m68hc11/libsim.a
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 = m68hc11/run
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_67 = m68hc11/gencode
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_68 = $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__append_69 = mcore/libsim.a
-@SIM_ENABLE_ARCH_mcore_TRUE@am__append_70 = mcore/run
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_71 = microblaze/libsim.a
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_72 = microblaze/run
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_73 = \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 = m32r/eng.h m32r/engx.h m32r/eng2.h
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_62 = $(m32r_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_63 = m68hc11/libsim.a
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_64 = m68hc11/run
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 = m68hc11/gencode
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 = $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_67 = mcore/libsim.a
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_68 = mcore/run
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_69 = microblaze/libsim.a
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_70 = microblaze/run
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_71 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/engine.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/irun.o
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_74 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_72 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_idecode.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16run.o
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_75 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_73 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_OBJ) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = mips/libsim.a
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 = mips/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 = mips/itable.h \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_74 = mips/libsim.a
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_75 = mips/run
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC)
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_79 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_77 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-mode-single
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_80 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_78 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m16 \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m32
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_81 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_79 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_SRC) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-igen \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_82 = $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_83 = mips/multi-include.h mips/multi-run.c
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 = mn10300/libsim.a
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 = mn10300/run
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_86 = \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_80 = $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_81 = mips/multi-include.h mips/multi-run.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_82 = mn10300/libsim.a
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_83 = mn10300/run
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 = $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_88 = moxie/libsim.a
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_89 = moxie/run
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_90 = msp430/libsim.a
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_91 = msp430/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 = or1k/libsim.a
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 = or1k/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 = or1k/eng.h
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 = or1k/eng.h
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 = $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_97 = ppc/libsim.a
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_98 = ppc/run
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_99 = ppc/defines.h ppc/icache.h \
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_86 = moxie/libsim.a
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_87 = moxie/run
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_88 = msp430/libsim.a
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_89 = msp430/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_90 = or1k/libsim.a
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_91 = or1k/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 = or1k/eng.h
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 = or1k/eng.h
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_95 = ppc/libsim.a
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_96 = ppc/run
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_97 = ppc/defines.h ppc/icache.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.h ppc/semantics.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.h ppc/support.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.h ppc/hw.h
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_100 = ppc/defines.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_98 = ppc/defines.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-defines \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_IGEN_TOOLS) ppc/libigen.a
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_101 = ppc/libigen.a
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_102 = $(ppc_IGEN_TOOLS)
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_103 = pru/libsim.a
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_104 = pru/run
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_105 = riscv/libsim.a
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_106 = riscv/run
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_107 = rl78/libsim.a
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_108 = rl78/run
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_109 = rx/libsim.a
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_110 = rx/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 = sh/libsim.a
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 = sh/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 = \
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_99 = ppc/libigen.a
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_100 = $(ppc_IGEN_TOOLS)
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_101 = pru/libsim.a
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_102 = pru/run
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_103 = riscv/libsim.a
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_104 = riscv/run
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_105 = rl78/libsim.a
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_106 = rl78/run
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_107 = rx/libsim.a
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_108 = rx/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_109 = sh/libsim.a
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_110 = sh/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_114 = sh/gencode
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_115 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_116 = v850/libsim.a
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_117 = v850/run
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_118 = \
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 = sh/gencode
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_114 = v850/libsim.a
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_115 = v850/run
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_116 = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_119 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_117 = $(v850_BUILD_OUTPUTS)
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
configure.lineno config.status.lineno
mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs
CONFIG_HEADER = config.h
-CONFIG_CLEAN_FILES = aarch64/.gdbinit arm/.gdbinit avr/.gdbinit \
- bfin/.gdbinit bpf/.gdbinit cr16/.gdbinit cris/.gdbinit \
- d10v/.gdbinit frv/.gdbinit ft32/.gdbinit h8300/.gdbinit \
- iq2000/.gdbinit lm32/.gdbinit m32c/.gdbinit m32r/.gdbinit \
- m68hc11/.gdbinit mcore/.gdbinit microblaze/.gdbinit \
- mips/.gdbinit mn10300/.gdbinit moxie/.gdbinit msp430/.gdbinit \
- or1k/.gdbinit ppc/.gdbinit pru/.gdbinit riscv/.gdbinit \
- rl78/.gdbinit rx/.gdbinit sh/.gdbinit erc32/.gdbinit \
- v850/.gdbinit example-synacor/.gdbinit .gdbinit
+CONFIG_CLEAN_FILES = aarch64/.gdbinit avr/.gdbinit bfin/.gdbinit \
+ bpf/.gdbinit cr16/.gdbinit cris/.gdbinit d10v/.gdbinit \
+ frv/.gdbinit ft32/.gdbinit h8300/.gdbinit iq2000/.gdbinit \
+ lm32/.gdbinit m32c/.gdbinit m32r/.gdbinit m68hc11/.gdbinit \
+ mcore/.gdbinit microblaze/.gdbinit mips/.gdbinit \
+ mn10300/.gdbinit moxie/.gdbinit msp430/.gdbinit or1k/.gdbinit \
+ ppc/.gdbinit pru/.gdbinit riscv/.gdbinit rl78/.gdbinit \
+ rx/.gdbinit sh/.gdbinit erc32/.gdbinit v850/.gdbinit \
+ example-synacor/.gdbinit .gdbinit
CONFIG_CLEAN_VPATH_FILES =
LIBRARIES = $(noinst_LIBRARIES)
ARFLAGS = cru
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/modules.$(OBJEXT)
aarch64_libsim_a_OBJECTS = $(am_aarch64_libsim_a_OBJECTS) \
$(nodist_aarch64_libsim_a_OBJECTS)
-arm_libsim_a_AR = $(AR) $(ARFLAGS)
-@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_DEPENDENCIES = arm/wrapper.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst \
-@SIM_ENABLE_ARCH_arm_TRUE@ %,arm/%,$(SIM_NEW_COMMON_OBJS)) \
-@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst \
-@SIM_ENABLE_ARCH_arm_TRUE@ %,arm/dv-%.o,$(SIM_HW_DEVICES)) \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu.o arm/armemu32.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/arminit.o arm/armos.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/armsupp.o arm/armvirt.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/thumbemu.o arm/armcopro.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/maverick.o arm/iwmmxt.o
-@SIM_ENABLE_ARCH_arm_TRUE@am_arm_libsim_a_OBJECTS = $(am__objects_1)
-@SIM_ENABLE_ARCH_arm_TRUE@nodist_arm_libsim_a_OBJECTS = \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/modules.$(OBJEXT)
-arm_libsim_a_OBJECTS = $(am_arm_libsim_a_OBJECTS) \
- $(nodist_arm_libsim_a_OBJECTS)
avr_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_DEPENDENCIES = avr/interp.o \
@SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
-@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_73) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) \
+@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_71) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_2)
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES = mips/interp.o \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_3) $(patsubst \
testsuite/common/alu-tst$(EXEEXT)
@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_10 = cris/rvdummy$(EXEEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_11 = aarch64/run$(EXEEXT)
-@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_12 = arm/run$(EXEEXT)
-@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_13 = avr/run$(EXEEXT)
-@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_14 = bfin/run$(EXEEXT)
-@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_15 = bpf/run$(EXEEXT)
-@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_16 = cr16/run$(EXEEXT)
-@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_17 = cris/run$(EXEEXT)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_18 = d10v/run$(EXEEXT)
-@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_19 = erc32/run$(EXEEXT) \
+@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_12 = avr/run$(EXEEXT)
+@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_13 = bfin/run$(EXEEXT)
+@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_14 = bpf/run$(EXEEXT)
+@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_15 = cr16/run$(EXEEXT)
+@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_16 = cris/run$(EXEEXT)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_17 = d10v/run$(EXEEXT)
+@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_18 = erc32/run$(EXEEXT) \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis$(EXEEXT)
-@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_20 = \
+@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_19 = \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/run$(EXEEXT)
-@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_21 = frv/run$(EXEEXT)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_22 = ft32/run$(EXEEXT)
-@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_23 = h8300/run$(EXEEXT)
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_24 = iq2000/run$(EXEEXT)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_25 = lm32/run$(EXEEXT)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_26 = m32c/run$(EXEEXT)
-@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_27 = m32r/run$(EXEEXT)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_28 = m68hc11/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_29 = mcore/run$(EXEEXT)
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_30 = \
+@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_20 = frv/run$(EXEEXT)
+@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_21 = ft32/run$(EXEEXT)
+@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_22 = h8300/run$(EXEEXT)
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_23 = iq2000/run$(EXEEXT)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_24 = lm32/run$(EXEEXT)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_25 = m32c/run$(EXEEXT)
+@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_26 = m32r/run$(EXEEXT)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_27 = m68hc11/run$(EXEEXT)
+@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_28 = mcore/run$(EXEEXT)
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_29 = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_31 = mips/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_32 = mn10300/run$(EXEEXT)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_33 = moxie/run$(EXEEXT)
-@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_34 = msp430/run$(EXEEXT)
-@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_35 = or1k/run$(EXEEXT)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_36 = ppc/run$(EXEEXT)
-@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_37 = pru/run$(EXEEXT)
-@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_38 = riscv/run$(EXEEXT)
-@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_39 = rl78/run$(EXEEXT)
-@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_40 = rx/run$(EXEEXT)
-@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_41 = sh/run$(EXEEXT)
-@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_42 = v850/run$(EXEEXT)
+@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_30 = mips/run$(EXEEXT)
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_31 = mn10300/run$(EXEEXT)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_32 = moxie/run$(EXEEXT)
+@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_33 = msp430/run$(EXEEXT)
+@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_34 = or1k/run$(EXEEXT)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_35 = ppc/run$(EXEEXT)
+@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_36 = pru/run$(EXEEXT)
+@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_37 = riscv/run$(EXEEXT)
+@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_38 = rl78/run$(EXEEXT)
+@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_39 = rx/run$(EXEEXT)
+@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_40 = sh/run$(EXEEXT)
+@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_41 = v850/run$(EXEEXT)
PROGRAMS = $(noinst_PROGRAMS)
am_aarch64_run_OBJECTS =
aarch64_run_OBJECTS = $(am_aarch64_run_OBJECTS)
am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
am__v_lt_0 = --silent
am__v_lt_1 =
-am_arm_run_OBJECTS =
-arm_run_OBJECTS = $(am_arm_run_OBJECTS)
-@SIM_ENABLE_ARCH_arm_TRUE@arm_run_DEPENDENCIES = arm/nrun.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/libsim.a $(am__DEPENDENCIES_4)
am_avr_run_OBJECTS =
avr_run_OBJECTS = $(am_avr_run_OBJECTS)
@SIM_ENABLE_ARCH_avr_TRUE@avr_run_DEPENDENCIES = avr/nrun.o \
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
SOURCES = $(aarch64_libsim_a_SOURCES) \
- $(nodist_aarch64_libsim_a_SOURCES) $(arm_libsim_a_SOURCES) \
- $(nodist_arm_libsim_a_SOURCES) $(avr_libsim_a_SOURCES) \
+ $(nodist_aarch64_libsim_a_SOURCES) $(avr_libsim_a_SOURCES) \
$(nodist_avr_libsim_a_SOURCES) $(bfin_libsim_a_SOURCES) \
$(nodist_bfin_libsim_a_SOURCES) $(bpf_libsim_a_SOURCES) \
$(nodist_bpf_libsim_a_SOURCES) $(common_libcommon_a_SOURCES) \
$(nodist_rx_libsim_a_SOURCES) $(sh_libsim_a_SOURCES) \
$(nodist_sh_libsim_a_SOURCES) $(v850_libsim_a_SOURCES) \
$(nodist_v850_libsim_a_SOURCES) $(aarch64_run_SOURCES) \
- $(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \
- $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \
+ $(avr_run_SOURCES) $(bfin_run_SOURCES) $(bpf_run_SOURCES) \
+ $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \
$(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \
$(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \
$(erc32_run_SOURCES) erc32/sis.c \
|| { echo " ( cd '$$dir' && rm -f" $$files ")"; \
$(am__cd) "$$dir" && rm -f $$files; }; \
}
-am__installdirs = "$(DESTDIR)$(armdocdir)" "$(DESTDIR)$(dtbdir)" \
- "$(DESTDIR)$(erc32docdir)" "$(DESTDIR)$(frvdocdir)" \
- "$(DESTDIR)$(or1kdocdir)" "$(DESTDIR)$(ppcdocdir)" \
- "$(DESTDIR)$(rxdocdir)" "$(DESTDIR)$(pkgincludedir)"
-DATA = $(armdoc_DATA) $(dtb_DATA) $(erc32doc_DATA) $(frvdoc_DATA) \
- $(or1kdoc_DATA) $(ppcdoc_DATA) $(rxdoc_DATA)
+am__installdirs = "$(DESTDIR)$(dtbdir)" "$(DESTDIR)$(erc32docdir)" \
+ "$(DESTDIR)$(frvdocdir)" "$(DESTDIR)$(or1kdocdir)" \
+ "$(DESTDIR)$(ppcdocdir)" "$(DESTDIR)$(rxdocdir)" \
+ "$(DESTDIR)$(pkgincludedir)"
+DATA = $(dtb_DATA) $(erc32doc_DATA) $(frvdoc_DATA) $(or1kdoc_DATA) \
+ $(ppcdoc_DATA) $(rxdoc_DATA)
am__pkginclude_HEADERS_DIST = $(srcroot)/include/sim/callback.h \
$(srcroot)/include/sim/sim.h
HEADERS = $(pkginclude_HEADERS)
AR_FOR_BUILD = @AR_FOR_BUILD@
AS_FOR_TARGET = @AS_FOR_TARGET@
AS_FOR_TARGET_AARCH64 = @AS_FOR_TARGET_AARCH64@
-AS_FOR_TARGET_ARM = @AS_FOR_TARGET_ARM@
AS_FOR_TARGET_AVR = @AS_FOR_TARGET_AVR@
AS_FOR_TARGET_BFIN = @AS_FOR_TARGET_BFIN@
AS_FOR_TARGET_BPF = @AS_FOR_TARGET_BPF@
CC_FOR_BUILD = @CC_FOR_BUILD@
CC_FOR_TARGET = @CC_FOR_TARGET@
CC_FOR_TARGET_AARCH64 = @CC_FOR_TARGET_AARCH64@
-CC_FOR_TARGET_ARM = @CC_FOR_TARGET_ARM@
CC_FOR_TARGET_AVR = @CC_FOR_TARGET_AVR@
CC_FOR_TARGET_BFIN = @CC_FOR_TARGET_BFIN@
CC_FOR_TARGET_BPF = @CC_FOR_TARGET_BPF@
LDFLAGS_FOR_BUILD = @LDFLAGS_FOR_BUILD@
LD_FOR_TARGET = @LD_FOR_TARGET@
LD_FOR_TARGET_AARCH64 = @LD_FOR_TARGET_AARCH64@
-LD_FOR_TARGET_ARM = @LD_FOR_TARGET_ARM@
LD_FOR_TARGET_AVR = @LD_FOR_TARGET_AVR@
LD_FOR_TARGET_BFIN = @LD_FOR_TARGET_BFIN@
LD_FOR_TARGET_BPF = @LD_FOR_TARGET_BPF@
srccom = $(srcdir)/common
srcroot = $(srcdir)/..
pkginclude_HEADERS = $(am__append_1)
-EXTRA_LIBRARIES = igen/libigen.a $(am__append_101)
+EXTRA_LIBRARIES = igen/libigen.a $(am__append_99)
noinst_LIBRARIES = common/libcommon.a $(am__append_3) $(am__append_5) \
$(am__append_7) $(am__append_9) $(am__append_11) \
- $(am__append_13) $(am__append_19) $(am__append_25) \
- $(am__append_31) $(am__append_35) $(am__append_37) \
- $(am__append_42) $(am__append_44) $(am__append_46) \
- $(am__append_51) $(am__append_56) $(am__append_60) \
- $(am__append_65) $(am__append_69) $(am__append_71) \
- $(am__append_76) $(am__append_84) $(am__append_88) \
- $(am__append_90) $(am__append_92) $(am__append_97) \
+ $(am__append_17) $(am__append_23) $(am__append_29) \
+ $(am__append_33) $(am__append_35) $(am__append_40) \
+ $(am__append_42) $(am__append_44) $(am__append_49) \
+ $(am__append_54) $(am__append_58) $(am__append_63) \
+ $(am__append_67) $(am__append_69) $(am__append_74) \
+ $(am__append_82) $(am__append_86) $(am__append_88) \
+ $(am__append_90) $(am__append_95) $(am__append_101) \
$(am__append_103) $(am__append_105) $(am__append_107) \
- $(am__append_109) $(am__append_111) $(am__append_116)
-BUILT_SOURCES = $(am__append_15) $(am__append_22) $(am__append_27) \
- $(am__append_39) $(am__append_48) $(am__append_53) \
- $(am__append_62) $(am__append_78) $(am__append_86) \
- $(am__append_94) $(am__append_99) $(am__append_113) \
- $(am__append_118)
+ $(am__append_109) $(am__append_114)
+BUILT_SOURCES = $(am__append_13) $(am__append_20) $(am__append_25) \
+ $(am__append_37) $(am__append_46) $(am__append_51) \
+ $(am__append_60) $(am__append_76) $(am__append_84) \
+ $(am__append_92) $(am__append_97) $(am__append_111) \
+ $(am__append_116)
CLEANFILES = common/version.c common/version.c-stamp \
testsuite/common/bits-gen testsuite/common/bits32m0.c \
testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
- testsuite/common/bits64m63.c $(am__append_17) $(am__append_23) \
- $(am__append_29) $(am__append_40) $(am__append_49) \
- $(am__append_54) $(am__append_63) $(am__append_95)
-DISTCLEANFILES = $(am__append_83)
+ testsuite/common/bits64m63.c $(am__append_15) $(am__append_21) \
+ $(am__append_27) $(am__append_38) $(am__append_47) \
+ $(am__append_52) $(am__append_61) $(am__append_93)
+DISTCLEANFILES = $(am__append_81)
MOSTLYCLEANFILES = core $(SIM_ENABLED_ARCHES:%=%/*.o) \
$(SIM_ENABLED_ARCHES:%=%/hw-config.h) \
$(SIM_ENABLED_ARCHES:%=%/stamp-hw) \
$(SIM_ENABLED_ARCHES:%=%/modules.c) \
$(SIM_ENABLED_ARCHES:%=%/stamp-modules) $(igen_IGEN_TOOLS) \
igen/libigen.a site-sim-config.exp testrun.log testrun.sum \
- $(am__append_18) $(am__append_24) $(am__append_30) \
- $(am__append_41) $(am__append_50) $(am__append_55) \
- $(am__append_59) $(am__append_64) $(am__append_68) \
- $(am__append_82) $(am__append_87) $(am__append_96) \
- $(am__append_100) $(am__append_115) $(am__append_119)
+ $(am__append_16) $(am__append_22) $(am__append_28) \
+ $(am__append_39) $(am__append_48) $(am__append_53) \
+ $(am__append_57) $(am__append_62) $(am__append_66) \
+ $(am__append_80) $(am__append_85) $(am__append_94) \
+ $(am__append_98) $(am__append_113) $(am__append_117)
CONFIG_STATUS_DEPENDENCIES = $(srcroot)/bfd/development.sh
AM_CFLAGS = \
$(WERROR_CFLAGS) \
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(BUILD_WERROR_CFLAGS) $(BUILD_WARN_CFLAGS)
LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
SIM_INSTALL_DATA_LOCAL_DEPS =
-SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_33)
-SIM_UNINSTALL_LOCAL_DEPS = $(am__append_34)
+SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_31)
+SIM_UNINSTALL_LOCAL_DEPS = $(am__append_32)
SIM_DEPBASE = $(@D)/$(DEPDIR)/$(@F:.o=)
SIM_COMPILE = \
$(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< && \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/libsim.a \
@SIM_ENABLE_ARCH_aarch64_TRUE@ $(SIM_COMMON_LIBS)
-@SIM_ENABLE_ARCH_arm_TRUE@AM_CPPFLAGS_arm = -DMODET
-@SIM_ENABLE_ARCH_arm_TRUE@nodist_arm_libsim_a_SOURCES = \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/modules.c
-
-@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_SOURCES = \
-@SIM_ENABLE_ARCH_arm_TRUE@ $(common_libcommon_a_SOURCES)
-
-@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_LIBADD = \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/wrapper.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/%,$(SIM_NEW_COMMON_OBJS)) \
-@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/dv-%.o,$(SIM_HW_DEVICES)) \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu32.o arm/arminit.o arm/armos.o arm/armsupp.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/armvirt.o arm/thumbemu.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/armcopro.o arm/maverick.o arm/iwmmxt.o
-
-@SIM_ENABLE_ARCH_arm_TRUE@arm_run_SOURCES =
-@SIM_ENABLE_ARCH_arm_TRUE@arm_run_LDADD = \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/nrun.o \
-@SIM_ENABLE_ARCH_arm_TRUE@ arm/libsim.a \
-@SIM_ENABLE_ARCH_arm_TRUE@ $(SIM_COMMON_LIBS)
-
-@SIM_ENABLE_ARCH_arm_TRUE@armdocdir = $(docdir)/arm
-@SIM_ENABLE_ARCH_arm_TRUE@armdoc_DATA = arm/README
@SIM_ENABLE_ARCH_avr_TRUE@nodist_avr_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_avr_TRUE@ avr/modules.c
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@
-@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_73) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) $(am__append_75)
+@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_71) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) $(am__append_73)
@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.c
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79) $(am__append_80) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_81)
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_77) $(am__append_78) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
.SUFFIXES: .c .lo .log .o .obj .test .test$(EXEEXT) .trs
am--refresh: Makefile
@:
-$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/arm/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__configure_deps)
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__configure_deps)
@for dep in $?; do \
case '$(am__configure_deps)' in \
*$$dep*) \
echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \
cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \
esac;
-$(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/arm/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__empty):
+$(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__empty):
$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
$(SHELL) ./config.status --recheck
-rm -f config.h stamp-h1
aarch64/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
-arm/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
- cd $(top_builddir) && $(SHELL) ./config.status $@
avr/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
bfin/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
$(AM_V_at)-rm -f aarch64/libsim.a
$(AM_V_AR)$(aarch64_libsim_a_AR) aarch64/libsim.a $(aarch64_libsim_a_OBJECTS) $(aarch64_libsim_a_LIBADD)
$(AM_V_at)$(RANLIB) aarch64/libsim.a
-arm/$(am__dirstamp):
- @$(MKDIR_P) arm
- @: > arm/$(am__dirstamp)
-arm/$(DEPDIR)/$(am__dirstamp):
- @$(MKDIR_P) arm/$(DEPDIR)
- @: > arm/$(DEPDIR)/$(am__dirstamp)
-arm/modules.$(OBJEXT): arm/$(am__dirstamp) \
- arm/$(DEPDIR)/$(am__dirstamp)
-
-arm/libsim.a: $(arm_libsim_a_OBJECTS) $(arm_libsim_a_DEPENDENCIES) $(EXTRA_arm_libsim_a_DEPENDENCIES) arm/$(am__dirstamp)
- $(AM_V_at)-rm -f arm/libsim.a
- $(AM_V_AR)$(arm_libsim_a_AR) arm/libsim.a $(arm_libsim_a_OBJECTS) $(arm_libsim_a_LIBADD)
- $(AM_V_at)$(RANLIB) arm/libsim.a
avr/$(am__dirstamp):
@$(MKDIR_P) avr
@: > avr/$(am__dirstamp)
@rm -f aarch64/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(aarch64_run_OBJECTS) $(aarch64_run_LDADD) $(LIBS)
-arm/run$(EXEEXT): $(arm_run_OBJECTS) $(arm_run_DEPENDENCIES) $(EXTRA_arm_run_DEPENDENCIES) arm/$(am__dirstamp)
- @rm -f arm/run$(EXEEXT)
- $(AM_V_CCLD)$(LINK) $(arm_run_OBJECTS) $(arm_run_LDADD) $(LIBS)
-
avr/run$(EXEEXT): $(avr_run_OBJECTS) $(avr_run_DEPENDENCIES) $(EXTRA_avr_run_DEPENDENCIES) avr/$(am__dirstamp)
@rm -f avr/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(avr_run_OBJECTS) $(avr_run_LDADD) $(LIBS)
mostlyclean-compile:
-rm -f *.$(OBJEXT)
-rm -f aarch64/*.$(OBJEXT)
- -rm -f arm/*.$(OBJEXT)
-rm -f avr/*.$(OBJEXT)
-rm -f bfin/*.$(OBJEXT)
-rm -f bpf/*.$(OBJEXT)
-rm -f *.tab.c
@AMDEP_TRUE@@am__include@ @am__quote@aarch64/$(DEPDIR)/modules.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@arm/$(DEPDIR)/modules.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@avr/$(DEPDIR)/modules.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@bfin/$(DEPDIR)/modules.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@bpf/$(DEPDIR)/modules.Po@am__quote@
clean-libtool:
-rm -rf .libs _libs
-rm -rf aarch64/.libs aarch64/_libs
- -rm -rf arm/.libs arm/_libs
-rm -rf avr/.libs avr/_libs
-rm -rf bfin/.libs bfin/_libs
-rm -rf bpf/.libs bpf/_libs
distclean-libtool:
-rm -f libtool config.lt
-install-armdocDATA: $(armdoc_DATA)
- @$(NORMAL_INSTALL)
- @list='$(armdoc_DATA)'; test -n "$(armdocdir)" || list=; \
- if test -n "$$list"; then \
- echo " $(MKDIR_P) '$(DESTDIR)$(armdocdir)'"; \
- $(MKDIR_P) "$(DESTDIR)$(armdocdir)" || exit 1; \
- fi; \
- for p in $$list; do \
- if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
- echo "$$d$$p"; \
- done | $(am__base_list) | \
- while read files; do \
- echo " $(INSTALL_DATA) $$files '$(DESTDIR)$(armdocdir)'"; \
- $(INSTALL_DATA) $$files "$(DESTDIR)$(armdocdir)" || exit $$?; \
- done
-
-uninstall-armdocDATA:
- @$(NORMAL_UNINSTALL)
- @list='$(armdoc_DATA)'; test -n "$(armdocdir)" || list=; \
- files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \
- dir='$(DESTDIR)$(armdocdir)'; $(am__uninstall_files_from_dir)
install-dtbDATA: $(dtb_DATA)
@$(NORMAL_INSTALL)
@list='$(dtb_DATA)'; test -n "$(dtbdir)" || list=; \
$(MAKE) $(AM_MAKEFLAGS) check-am
all-am: Makefile $(LIBRARIES) $(PROGRAMS) $(DATA) $(HEADERS) config.h
installdirs:
- for dir in "$(DESTDIR)$(armdocdir)" "$(DESTDIR)$(dtbdir)" "$(DESTDIR)$(erc32docdir)" "$(DESTDIR)$(frvdocdir)" "$(DESTDIR)$(or1kdocdir)" "$(DESTDIR)$(ppcdocdir)" "$(DESTDIR)$(rxdocdir)" "$(DESTDIR)$(pkgincludedir)"; do \
+ for dir in "$(DESTDIR)$(dtbdir)" "$(DESTDIR)$(erc32docdir)" "$(DESTDIR)$(frvdocdir)" "$(DESTDIR)$(or1kdocdir)" "$(DESTDIR)$(ppcdocdir)" "$(DESTDIR)$(rxdocdir)" "$(DESTDIR)$(pkgincludedir)"; do \
test -z "$$dir" || $(MKDIR_P) "$$dir"; \
done
install: $(BUILT_SOURCES)
-test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
-rm -f aarch64/$(DEPDIR)/$(am__dirstamp)
-rm -f aarch64/$(am__dirstamp)
- -rm -f arm/$(DEPDIR)/$(am__dirstamp)
- -rm -f arm/$(am__dirstamp)
-rm -f avr/$(DEPDIR)/$(am__dirstamp)
-rm -f avr/$(am__dirstamp)
-rm -f bfin/$(DEPDIR)/$(am__dirstamp)
distclean: distclean-am
-rm -f $(am__CONFIG_DISTCLEAN_FILES)
- -rm -rf aarch64/$(DEPDIR) arm/$(DEPDIR) avr/$(DEPDIR) bfin/$(DEPDIR) bpf/$(DEPDIR) common/$(DEPDIR) cr16/$(DEPDIR) cris/$(DEPDIR) d10v/$(DEPDIR) erc32/$(DEPDIR) example-synacor/$(DEPDIR) frv/$(DEPDIR) ft32/$(DEPDIR) h8300/$(DEPDIR) igen/$(DEPDIR) iq2000/$(DEPDIR) lm32/$(DEPDIR) m32c/$(DEPDIR) m32r/$(DEPDIR) m68hc11/$(DEPDIR) mcore/$(DEPDIR) microblaze/$(DEPDIR) mips/$(DEPDIR) mn10300/$(DEPDIR) moxie/$(DEPDIR) msp430/$(DEPDIR) or1k/$(DEPDIR) ppc/$(DEPDIR) pru/$(DEPDIR) riscv/$(DEPDIR) rl78/$(DEPDIR) rx/$(DEPDIR) sh/$(DEPDIR) testsuite/common/$(DEPDIR) v850/$(DEPDIR)
+ -rm -rf aarch64/$(DEPDIR) avr/$(DEPDIR) bfin/$(DEPDIR) bpf/$(DEPDIR) common/$(DEPDIR) cr16/$(DEPDIR) cris/$(DEPDIR) d10v/$(DEPDIR) erc32/$(DEPDIR) example-synacor/$(DEPDIR) frv/$(DEPDIR) ft32/$(DEPDIR) h8300/$(DEPDIR) igen/$(DEPDIR) iq2000/$(DEPDIR) lm32/$(DEPDIR) m32c/$(DEPDIR) m32r/$(DEPDIR) m68hc11/$(DEPDIR) mcore/$(DEPDIR) microblaze/$(DEPDIR) mips/$(DEPDIR) mn10300/$(DEPDIR) moxie/$(DEPDIR) msp430/$(DEPDIR) or1k/$(DEPDIR) ppc/$(DEPDIR) pru/$(DEPDIR) riscv/$(DEPDIR) rl78/$(DEPDIR) rx/$(DEPDIR) sh/$(DEPDIR) testsuite/common/$(DEPDIR) v850/$(DEPDIR)
-rm -f Makefile
distclean-am: clean-am distclean-DEJAGNU distclean-compile \
distclean-generic distclean-hdr distclean-libtool \
info-am:
-install-data-am: install-armdocDATA install-data-local install-dtbDATA \
+install-data-am: install-data-local install-dtbDATA \
install-erc32docDATA install-frvdocDATA install-or1kdocDATA \
install-pkgincludeHEADERS install-ppcdocDATA install-rxdocDATA
maintainer-clean: maintainer-clean-am
-rm -f $(am__CONFIG_DISTCLEAN_FILES)
-rm -rf $(top_srcdir)/autom4te.cache
- -rm -rf aarch64/$(DEPDIR) arm/$(DEPDIR) avr/$(DEPDIR) bfin/$(DEPDIR) bpf/$(DEPDIR) common/$(DEPDIR) cr16/$(DEPDIR) cris/$(DEPDIR) d10v/$(DEPDIR) erc32/$(DEPDIR) example-synacor/$(DEPDIR) frv/$(DEPDIR) ft32/$(DEPDIR) h8300/$(DEPDIR) igen/$(DEPDIR) iq2000/$(DEPDIR) lm32/$(DEPDIR) m32c/$(DEPDIR) m32r/$(DEPDIR) m68hc11/$(DEPDIR) mcore/$(DEPDIR) microblaze/$(DEPDIR) mips/$(DEPDIR) mn10300/$(DEPDIR) moxie/$(DEPDIR) msp430/$(DEPDIR) or1k/$(DEPDIR) ppc/$(DEPDIR) pru/$(DEPDIR) riscv/$(DEPDIR) rl78/$(DEPDIR) rx/$(DEPDIR) sh/$(DEPDIR) testsuite/common/$(DEPDIR) v850/$(DEPDIR)
+ -rm -rf aarch64/$(DEPDIR) avr/$(DEPDIR) bfin/$(DEPDIR) bpf/$(DEPDIR) common/$(DEPDIR) cr16/$(DEPDIR) cris/$(DEPDIR) d10v/$(DEPDIR) erc32/$(DEPDIR) example-synacor/$(DEPDIR) frv/$(DEPDIR) ft32/$(DEPDIR) h8300/$(DEPDIR) igen/$(DEPDIR) iq2000/$(DEPDIR) lm32/$(DEPDIR) m32c/$(DEPDIR) m32r/$(DEPDIR) m68hc11/$(DEPDIR) mcore/$(DEPDIR) microblaze/$(DEPDIR) mips/$(DEPDIR) mn10300/$(DEPDIR) moxie/$(DEPDIR) msp430/$(DEPDIR) or1k/$(DEPDIR) ppc/$(DEPDIR) pru/$(DEPDIR) riscv/$(DEPDIR) rl78/$(DEPDIR) rx/$(DEPDIR) sh/$(DEPDIR) testsuite/common/$(DEPDIR) v850/$(DEPDIR)
-rm -f Makefile
maintainer-clean-am: distclean-am maintainer-clean-generic
ps-am:
-uninstall-am: uninstall-armdocDATA uninstall-dtbDATA \
- uninstall-erc32docDATA uninstall-frvdocDATA uninstall-local \
- uninstall-or1kdocDATA uninstall-pkgincludeHEADERS \
- uninstall-ppcdocDATA uninstall-rxdocDATA
+uninstall-am: uninstall-dtbDATA uninstall-erc32docDATA \
+ uninstall-frvdocDATA uninstall-local uninstall-or1kdocDATA \
+ uninstall-pkgincludeHEADERS uninstall-ppcdocDATA \
+ uninstall-rxdocDATA
.MAKE: all check check-am install install-am install-strip
distclean distclean-DEJAGNU distclean-compile \
distclean-generic distclean-hdr distclean-libtool \
distclean-tags dvi dvi-am html html-am info info-am install \
- install-am install-armdocDATA install-data install-data-am \
- install-data-local install-dtbDATA install-dvi install-dvi-am \
+ install-am install-data install-data-am install-data-local \
+ install-dtbDATA install-dvi install-dvi-am \
install-erc32docDATA install-exec install-exec-am \
install-exec-local install-frvdocDATA install-html \
install-html-am install-info install-info-am install-man \
installcheck-am installdirs maintainer-clean \
maintainer-clean-generic mostlyclean mostlyclean-compile \
mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
- recheck tags tags-am uninstall uninstall-am \
- uninstall-armdocDATA uninstall-dtbDATA uninstall-erc32docDATA \
- uninstall-frvdocDATA uninstall-local uninstall-or1kdocDATA \
- uninstall-pkgincludeHEADERS uninstall-ppcdocDATA \
- uninstall-rxdocDATA
+ recheck tags tags-am uninstall uninstall-am uninstall-dtbDATA \
+ uninstall-erc32docDATA uninstall-frvdocDATA uninstall-local \
+ uninstall-or1kdocDATA uninstall-pkgincludeHEADERS \
+ uninstall-ppcdocDATA uninstall-rxdocDATA
.PRECIOUS: Makefile
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_aarch64_TRUE@-@am__include@ aarch64/$(DEPDIR)/*.Po
-@SIM_ENABLE_ARCH_arm_TRUE@$(arm_libsim_a_OBJECTS) $(arm_libsim_a_LIBADD): arm/hw-config.h
-
-@SIM_ENABLE_ARCH_arm_TRUE@arm/modules.o: arm/modules.c
-
-@SIM_ENABLE_ARCH_arm_TRUE@arm/%.o: common/%.c ; $(SIM_COMPILE)
-@SIM_ENABLE_ARCH_arm_TRUE@-@am__include@ arm/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_avr_TRUE@$(avr_libsim_a_OBJECTS) $(avr_libsim_a_LIBADD): avr/hw-config.h
@SIM_ENABLE_ARCH_avr_TRUE@avr/modules.o: avr/modules.c
+++ /dev/null
-2021-06-22 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac: Removed.
- * aclocal.m4: Removed.
- * configure: Removed.
-
-2021-06-21 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4: Regenerate.
- * configure: Regenerate.
-
-2021-06-21 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2021-06-20 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac (SIM_AC_COMMON): Delete.
- * aclocal.m4, configure: Regenerate.
-
-2021-06-20 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4: Regenerate.
- * configure: Regenerate.
-
-2021-06-19 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4: Regenerate.
- * configure: Regenerate.
-
-2021-06-19 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2021-06-18 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4, configure: Regenerate.
-
-2021-06-18 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2021-06-17 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
- * aclocal.m4, configure: Regenerate.
-
-2021-06-16 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2021-06-16 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
- * config.in: Removed.
-
-2021-06-15 Mike Frysinger <vapier@gentoo.org>
-
- * config.in, configure: Regenerate.
-
-2021-06-14 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
- * configure: Regenerate.
-
-2021-06-12 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
- * wrapper.c (sim_open): Set current_alignment.
-
-2021-06-12 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4, config.in, configure: Regenerate.
-
-2021-06-12 Mike Frysinger <vapier@gentoo.org>
-
- * config.in, configure: Regenerate.
-
-2021-05-17 Mike Frysinger <vapier@gentoo.org>
-
- * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
-
-2021-05-17 Mike Frysinger <vapier@gentoo.org>
-
- * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
- (struct sim_state): Delete.
-
-2021-05-16 Mike Frysinger <vapier@gentoo.org>
-
- * armcopro.c, armemu.c, arminit.c, armsupp.c, armvirt.c, iwmmxt.c,
- maverick.c, thumbemu.c: Include defs.h.
- * armos.c, wrapper.c: Replace config.h include with defs.h.
- * armdefs.h: Delete config.h include.
-
-2021-05-16 Mike Frysinger <vapier@gentoo.org>
-
- * config.in, configure: Regenerate.
-
-2021-05-14 Mike Frysinger <vapier@gentoo.org>
-
- * armos.c (ARMul_OSHandleSWI): Delete 2nd arg to time callback.
-
-2021-05-14 Mike Frysinger <vapier@gentoo.org>
-
- * armos.c: Update include path.
- * wrapper.c: Likewise.
-
-2021-05-04 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2021-05-03 Simon Marchi <simon.marchi@polymtl.ca>
-
- * armdefs.h (ARMul_ConsolePrint): Use format attribute.
- * wrapper.c (op_printf): Likewise.
-
-2021-05-01 Mike Frysinger <vapier@gentoo.org>
-
- * config.in, configure: Regenerate.
-
-2021-05-01 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (SIM_OBJS): Change armemu26.o to armemu.o.
- (armemu26.o, armemu32.o): Delete targets.
- * armemu32.c: New file.
-
-2021-04-26 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4, config.in, configure: Regenerate.
-
-2021-04-26 Nick Clifton <nickc@redhat.com>
-
- PR 22790
- * armemu.c (Handle_Store_Double): Allow 4 byte alignment when
- running in v6 mode.
-
-2021-04-22 Tom Tromey <tom@tromey.com>
-
- * configure, config.in: Rebuild.
-
-2021-04-22 Tom Tromey <tom@tromey.com>
-
- * Makefile.in (armemu26.o, armemu32.o): Use COMPILE and
- POSTCOMPILE.
-
-2021-04-22 Tom Tromey <tom@tromey.com>
-
- * configure: Rebuild.
-
-2021-04-21 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4: Regenerate.
-
-2021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
-
- * configure: Regenerate.
-
-2021-04-18 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2021-04-12 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
-
-2021-04-02 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4, configure: Regenerate.
-
-2021-02-28 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2021-02-21 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
- * aclocal.m4, configure: Regenerate.
-
-2021-02-13 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
- * aclocal.m4, configure: Regenerate.
-
-2021-02-06 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2021-01-11 Mike Frysinger <vapier@gentoo.org>
-
- * config.in, configure: Regenerate.
-
-2021-01-09 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2021-01-08 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2021-01-04 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c: Include stdlib.h.
-
-2021-01-04 Mike Frysinger <vapier@gentoo.org>
-
- * iwmmxt.c: Include stdlib.h.
-
-2021-01-04 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2020-12-15 Nick Clifton <nickc@redhat.com>
-
- * wrapper.c (sim_create_inferior): Accept some more ARM machine numbers.
-
-2020-12-15 Jens Bauer <jens@plustv.dk>
-
- * armemu.c (handle_v6_insn): Add support for SDIV and UDIV.
- * thumbemu.c (handle_T2_insn): Likewise.
-
-2020-10-20 Dr. David Alan Gilbert <dgilbert@redhat.com>
-
- * armos.c (SWIread): Fix printf format.
-
-2020-08-13 Luis Machado <luis.machado@linaro.org>
-
- PR sim/26365
-
- * wrapper.c (sim_target_parse_command_line): Free discarded argv
- entries.
- (sim_open): Use a duplicate of argv instead of the original argv.
-
-2020-01-17 Christian Biesinger <cbiesinger@google.com>
-
- * iwmmxt.c: Fix spelling error (seperate).
-
-2019-12-06 Luis Machado <luis.machado@linaro.org>
-
- * armemu.c (isize): Move this declaration ...
- * arminit.c (isize): ... here.
- * maverick.h: New file.
- * wrapper.c: Include "maverick.h".
- (<struct maverick_regs>, <union maverick_acc_regs>): Remove and update
- comment.
- (sim_create_inferior): Cast variables to proper type.
- * maverick.c: Include "maverick.h".
- (<struct maverick_regs>, <union maverick_acc_regs>): Move
- declarations to maverick.h and update comment.
- (DSPsc, DSPacc, DSPregs): Adjust comment.
-
-2018-01-02 Nick Clifton <nickc@redhat.com>
-
- PR 22663
- * maverick.c (DSPCDP4): Add missing parameter to debug print
- statement.
-
-2017-09-21 Yao Qi <yao.qi@linaro.org>
-
- * wrapper.c (print_insn): Use disassembler instead of
- print_insn_little_arm.
-
-2017-09-06 John Baldwin <jhb@FreeBSD.org>
-
- * configure: Regenerate.
-
-2017-02-13 Mike Frysinger <vapier@gentoo.org>
-
- * armos.c: Include libiberty.h.
- (SWIopen): Use ARRAY_SIZE.
- * armsupp.c: Include libiberty.h.
- (ModeToBank): Use ARRAY_SIZE.
- * wrapper.c (sim_target_parse_command_line): Likewise.
-
-2016-07-14 Nick Clifton <nickc@redhat.com>
-
- * armemu.c (Multiply64): Only issue error messages about invalid
- arguments if debugging is enabled.
- * armos.c (ARMul_OSHandleSWI): Ignore invalid flags.
-
-2016-01-10 Mike Frysinger <vapier@gentoo.org>
-
- * config.in, configure: Regenerate.
-
-2016-01-10 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2016-01-10 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
- * configure: Regenerate.
-
-2016-01-10 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2016-01-10 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2016-01-10 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
- * configure: Regenerate.
-
-2016-01-10 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2016-01-10 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2016-01-09 Mike Frysinger <vapier@gentoo.org>
-
- * config.in, configure: Regenerate.
-
-2016-01-06 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (sim_create_inferior): Mark argv and env const.
- (sim_open): Mark argv const.
-
-2016-01-04 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2016-01-03 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (sim_open): Update sim_parse_args comment.
-
-2016-01-03 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (sim_target_parse_arg_array): Replace for loop with
- a call to countargv.
-
-2016-01-03 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
- * configure: Regenerate.
-
-2016-01-02 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
- * wrapper.c (init): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
-
-2015-12-30 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (sim_store_register): Rename to ...
- (arm_reg_store): ... this.
- (sim_fetch_register): Rename to ...
- (arm_reg_fetch): ... this.
- (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
-
-2015-12-27 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (SIM_OBJS): Delete sim-hload.o.
-
-2015-12-26 Mike Frysinger <vapier@gentoo.org>
-
- * config.in, configure: Regenerate.
-
-2015-12-25 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (SIM_OBJS): Delete bag.o.
- * armdefs.h (struct ARMul_State): Delete ErrorCode.
- (ResetPin, FIQPin, IRQPin, AbortPin, TransPin, BigEndPin, Prog32Pin,
- Data32Pin, LateAbortPin, ARMul_OSExit, ARMul_OSLastErrorP,
- ARMul_Debug, ARMul_OSException,rdi_log, SpinCursor, HOURGLASS,
- HOURGLASS_RATE): Delete.
- * armemu.c (ARMul_Emulate26): Delete ARMul_Debug call.
- * arminit.c (ARMul_Reset): Do not set state->ErrorCode.
- (ARMul_Abort): Delete ARMul_OSException call.
- * armopts.h: Delete file.
- * armos.c (isatty_, ARMul_OSExit, ARMul_OSException,
- ARMul_OSLastErrorP, ARMul_Debug, BUFFERSIZE, UNIQUETEMPS, NOOP,
- BINARY, READOP, WRITEOP, FIXCRLF): Delete.
- (struct OSblock): Delete Time0, ErrorP, FileTable, FileFlags, and
- tempnames.
- (ARMul_OSInit): Do not set OSptr->ErrorP, OSptr->FileTable, or
- OSptr->tempnames.
- * armrdi.c: Delete file.
- * armvirt.c: Delete armopts.h include.
- (ARMul_LoadInstrS): Delete HOURGLASS logic.
- * bag.c, bag.h, communicate.c, communicate.h, dbg_conf.h, dbg_cp.h,
- dbg_hif.h: Delete files.
- * dbg_rdi.h (RDP_*, RDI*): Delete defines.
- (PointHandle, ThreadHandle, Dbg_ConfigBlock, Dbg_HostosInterface,
- Dbg_MCState, getbufferproc): Delete.
- (rdi_*): Delete Functions.
- (RDI_ConfigAspect, RDI_ConfigMatchType, RDI_NameList): Delete
- (struct RDIProcVec): Delete.
- * gdbhost.c, gdbhost.h, kid.c, main.c, parent.c: Delete files.
- * wrapper.c (ARMul_Debug): Delete.
-
-2015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
-
- * thumbemu.c (handle_T2_insn): Fix left shift of negative value.
- * armemu.c (handle_v6_insn): Likewise.
-
-2015-11-14 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (sim_close): Delete.
-
-2015-07-14 Nick Clifton <nickc@redhat.com>
-
- * armcopro.c: Remove extraneous whitespace.
- * armdefs.h: Likewise.
- * armfpe.h: Likewise.
- * arminit.c: Likewise.
- * armopts.h: Likewise.
- * armos.c: Likewise.
- * armos.h: Likewise.
- * armrdi.c: Likewise.
- * armsupp.c: Likewise.
- * armvirt.c: Likewise.
- * bag.c: Likewise.
- * bag.h: Likewise.
- * communicate.c: Likewise.
- * communicate.h: Likewise.
- * dbg_conf.h: Likewise.
- * dbg_cp.h: Likewise.
- * dbg_hif.h: Likewise.
- * dbg_rdi.h: Likewise.
- * gdbhost.c: Likewise.
- * gdbhost.h: Likewise.
- * iwmmxt.c: Likewise.
- * iwmmxt.h: Likewise.
- * kid.c: Likewise.
- * main.c: Likewise.
- * maverick.c: Likewise.
- * parent.c: Likewise.
- * thumbemu.c: Likewise.
- * wrapper.c: Likewise.
-
-2015-07-02 Nick Clifton <nickc@redhat.com>
-
- * Makefile.in (SIM_EXTRA_CFLAGS): Revert previous delta.
- (SIM_EXTRA_LIBS): Add -lm.
-
-2015-06-28 Nick Clifton <nickc@redhat.com>
-
- * Makefile.in (SIM_EXTRA_CFLAGS): Add -lm.
- * armdefs.h (ARMdval, ARMfval): New types.
- (ARM_VFP_reg): New union.
- (struct ARMul_State): Add VFP_Reg and FPSCR fields.
- (VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor
- macros for the new VFP_Reg field.
- * armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT,
- QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8,
- USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX
- instructions.
- (handle_VFP_move): New function.
- (ARMul_Emulate16): Add checks for newly supported v6
- instructions. Add support for VMRS, VMOV and MRC instructions.
- (Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when
- operating in v6 mode.
- * armemu.h (t_resolved): Define.
- * armsupp.c: Include math.h.
- (handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH,
- VSTM, VLDM and VPOP instructions.
- (ARMul_LDC): Test for co-processor 10 or 11 and pass call to the
- new handle_VFP_xfer function.
- (ARMul_STC): Likewise.
- (handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS,
- VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP,
- VCMPE and VCVT instructions.
- (ARMul_CDP): Test for co-processor 10 or 11 and pass call to the
- new handle_VFP_op function.
- * thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros.
- (test_cond): New function. Tests a condition and returns non-zero
- if the condition has been met.
- (handle_IT_block): New function.
- (in_IT_block): New function.
- (IT_block_allow): New function.
- (ThumbExpandImm): New function.
- (handle_T2_insn): New function. Handles T2 thumb instructions.
- (handle_v6_thumb_insn): Add next_instr and pc parameters.
- (ARMul_ThumbDecode): Add support for IT blocks. Add support for
- v6 instructions.
- * wrapper.c (sim_create_inferior): Detect a thumb address and call
- SETT appropriately.
-
-2015-06-23 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2015-06-23 Mike Frysinger <vapier@gentoo.org>
-
- * armdefs.h: Always include stdint.h.
- [!__STDC__]: Delete.
- [!HAVE_STDINT_H]: Delete.
- * dbg_hif.h [!__STDC__]: Delete.
-
-2015-06-12 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2015-06-12 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2015-04-18 Mike Frysinger <vapier@gentoo.org>
-
- * sim-main.h (SIM_CPU): Delete.
-
-2015-04-18 Mike Frysinger <vapier@gentoo.org>
-
- * sim-main.h (sim_cia): Delete.
-
-2015-04-17 Mike Frysinger <vapier@gentoo.org>
-
- * sim-main.h (CIA_GET, CIA_SET): Delete.
-
-2015-04-17 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (arm_pc_get, arm_pc_set): New functions.
- (sim_open): Declare new local var i. Call CPU_PC_FETCH &
- CPU_PC_STORE for all cpus.
-
-2015-04-15 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
- * sim-main.h (STATE_CPU): Delete.
-
-2015-04-13 Mike Frysinger <vapier@gentoo.org>
-
- * configure: Regenerate.
-
-2015-04-12 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (SIM_OBJS): Move wrapper.o to the start of the list.
-
-2015-04-06 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (SIM_OBJS): Delete sim-engine.o.
-
-2015-04-01 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (armos.o, armcopro.o, maverick.o, iwmmxt.o, arminit.o,
- armrdi.o, armsupp.o, thumbemu.o, bag.o, wrapper.o): Delete rules.
- * tconfig.h: Delete file.
-
-2015-03-31 Mike Frysinger <vapier@gentoo.org>
-
- * config.in, configure: Regenerate.
-
-2015-03-30 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (SIM_RUN_OBJS): Delete.
- (SIM_EXTRA_CFLAGS): Delete -DSIM_TARGET_SWITCHES and
- -DSIM_USE_DEPRECATED_RUN_FRONTEND.
- (SIM_OBJS): Change to $(SIM_NEW_COMMON_OBJS).
- * sim-main.h: New file.
- * wrapper.c: Delete armdefs.h, sim-utils.h, and run-sim.h includes.
- Add sim-main.h and sim-options.h includes.
- (sim_callback, mem_size, trace): Add TODO comments.
- (state): Delete static and add TODO comment.
- (sim_kind, myname, big_endian): Delete.
- (init): Change big_endian to CURRENT_TARGET_BYTE_ORDER check.
- (sim_size, sim_trace, sim_info, sim_target_display_usage, sim_load,
- sim_do_command, sim_set_callbacks, sim_complete_command): Delete.
- (sim_target_parse_command_line): Mark static.
- (free_state): New function.
- (sim_open): Rewrite to use new common logic.
- (sim_close): Delete body.
-
-2015-03-30 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (SIM_EXTRA_CFLAGS): Delete -DNEED_UI_LOOP_HOOK.
- * interp.c [NEED_UI_LOOP_HOOK] (UI_LOOP_POLL_INTERVAL,
- ui_loop_hook_counter, deprecated_ui_loop_hook): Delete.
- (sim_resume) [NEED_UI_LOOP_HOOK]: Delete ui code.
-
-2015-03-30 Mike Frysinger <vapier@gentoo.org>
-
- * armemu.c [MODE32] (handle_v6_insn): Move definition.
- (ARMul_Emulate26): Initialize do_int after label target.
- * armemu.h (UNDEF_Test, UNDEF_Shift, UNDEF_MSRPC, UNDEF_MRSPC,
- UNDEF_MULPCDest, UNDEF_MULDestEQOp1, UNDEF_LSRBPC,
- UNDEF_LSRBaseEQOffWb, UNDEF_LSRBaseEQDestWb, UNDEF_LSRPCBaseWb,
- UNDEF_LSRPCOffWb, UNDEF_LSMNoRegs, UNDEF_LSMPCBase,
- UNDEF_LSMUserBankWb, UNDEF_LSMBaseInListWb, UNDEF_SWPPC,
- UNDEF_CoProHS, UNDEF_MCRPC, UNDEF_LSCPCBaseWb,
- UNDEF_UndefNotBounced, UNDEF_ShortInt, UNDEF_IllegalMode,
- UNDEF_Prog32SigChange, UNDEF_Data32SigChange): Define to while(0).
- * armsupp.c (ARMul_Align): Convert old style prototype.
- * bag.c (addtolist, killwholelist): Mark static.
- (BAG_newbag): Convert old style prototype.
- * maverick.c (mv_compute_host_endianness): Delete.
- * wrapper.c (verbosity, sim_set_verbose): Delete.
- (init): Set state->verbose to 0.
-
-2015-03-30 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac: Call SIM_AC_OPTION_ENDIAN, SIM_AC_OPTION_ALIGNMENT,
- SIM_AC_OPTION_HOSTENDIAN, SIM_AC_OPTION_ENVIRONMENT,
- SIM_AC_OPTION_INLINE, and SIM_AC_OPTION_WARNINGS.
- * config.in, configure: Regenerate.
-
-2015-03-30 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (COPRO): Delete.
- (SIM_OBJS): Expand COPRO.
- * configure.ac: Deletd stdint.h check.
- (COPRO): Delete.
- * configure: Regenerate.
-
-2015-03-16 Mike Frysinger <vapier@gentoo.org>
-
- * config.in, configure: Regenerate.
- * tconfig.in: Rename file ...
- * tconfig.h: ... here.
-
-2015-03-14 Mike Frysinger <vapier@gentoo.org>
-
- * Makefile.in (SIM_EXTRA_CFLAGS): Add
- -DSIM_USE_DEPRECATED_RUN_FRONTEND.
- (SIM_RUN_OBJS): Set to run.o.
-
-2015-03-14 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac (AC_CHECK_HEADERS): Delete unistd.h.
- * aclocal.m4, configure: Regenerate.
-
-2014-08-19 Alan Modra <amodra@gmail.com>
-
- * configure: Regenerate.
-
-2014-08-15 Roland McGrath <mcgrathr@google.com>
-
- * configure: Regenerate.
- * config.in: Regenerate.
-
-2014-03-18 Nick Clifton <nickc@redhat.com>
-
- * wrapper.c: Convert function declarations to ISO C format.
- (sim_open): Delete code for handling t,d and z command line
- options.
-
-2014-03-14 Nick Clifton <nickc@redhat.com>
-
- * wrapper.c (op_print): New function.
- (sim_dis_read): New function.
- (print_insn): New function - disassembles the given instruction.
- (sim_trace): Note that tracing is now allowed.
- (sim_create_inferior): Default to emulating v6.
- Initialise the disassembler machinery.
- (sim_target_parse_command_line): Add support for -t -d and -z
- options.
- (sim_target_display_usage): Note existence of -d and -z options.
- (sim_open): Parse -t -d and -z options.
- * armemu.h: Add exports of trace, disas and trace_funcs.
- Add prototype for print_insn.
- * armemu.c (ARMul_Emulate26): Add tracing code.
- Delete unused variables.
- * thumbemu (handle_v6_thumb_insn): Delete unused variable Rd.
- Move Rm variable into switch cases.
- Add tracing code.
-
- * armcopro.c (XScale_cp15_init): Add a return value.
- (XScale_cp13_init): Likewise.
- (XScale_cp14_init): Likewise.
- (XScale_cp15_LDC): Delete unused function.
- (XScale_cp15_STC): Likewise.
- * maverick.c: Delete comment inside comment.
- (DSPInit): Delete unused function.
- (DSPMCR4): Fix compile time warning about missing parenthesis.
- (DSPMCR5): Likewise.
- (DSPCDP6): Delete unused variable opcode2.
-
-2014-03-14 David McQuillan <dmcq@tao-group.com>
-
- PR sim/8388
- * armemu.c (WriteR15Load): New function. Determines if the state
- can be changed upon a write to R15.
- (LoadMult): Use WriteR15Load.
- * armemu.h (WRITEDESTB): Use WriteR15Load.
-
-2014-03-10 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (sim_do_command): Add const to cmd.
-
-2014-03-05 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (sim_load): Add const to prog.
-
-2013-09-23 Alan Modra <amodra@gmail.com>
-
- * configure: Regenerate.
-
-2013-06-03 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4, configure: Regenerate.
-
-2013-05-07 Jayant Sonar <jayant.sonar@kpitcummins.com>
- Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
-
- * armemu.c (ARMul_Emulate32): Emulate instructions MOVW and MOVT.
-
-2012-12-19 Joel Brobecker <brobecker@adacore.com>
-
- * COPYING: Update to GPL version 3.
-
-2012-09-03 Nick Clifton <nickc@redhat.com>
-
- PR sim/14540
- * armsupp.c (ARMul_MRC): Return 0 if access to the MRC instruction
- is denied.
-
-2012-08-01 Kevin Buettner <kevinb@redhat.com>
-
- * wrapper.c (libiberty.h): Include.
- (sim_store_register, sim_fetch_register): On success, return
- length, instead of -1.
-
-2012-06-15 Joel Brobecker <brobecker@adacore.com>
-
- * config.in, configure: Regenerate.
-
-2012-06-13 Nick Clifton <nickc@redhat.com>
-
- * wrapper.c (sim_create_inferior): Treat WMMX2 binaries as iWMMXt
- binaries (for now).
-
-2012-05-24 Pedro Alves <palves@redhat.com>
-
- PR gdb/7205
-
- Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout.
-
-2012-05-18 Nick Clifton <nickc@redhat.com>
-
- PR 14072
- * wrapper.c: Include config.h before system header files.
-
-2012-03-24 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4, config.in, configure: Regenerate.
-
-2011-12-03 Mike Frysinger <vapier@gentoo.org>
-
- * aclocal.m4: New file.
- * configure: Regenerate.
-
-2011-10-17 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac: Change include to common/acinclude.m4.
-
-2011-10-17 Mike Frysinger <vapier@gentoo.org>
-
- * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
- call. Replace common.m4 include with SIM_AC_COMMON.
- * configure: Regenerate.
-
-2011-07-01 Nick Clifton <nickc@redhat.com>
-
- PR sim/12737
- * iwmmxt.c (WCMPGT): Sign extend 32-bit values before performing a
- signed compare.
- (WMAC): Extend computed result before adding to result register.
- (WRSA): Sign extend 32-bit values before shifting.
-
-2011-04-16 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (sim_complete_command): New stub function.
-
-2010-05-26 Ozkan Sezer <sezeroz@gmail.com>
-
- * communicate.c (MYread_char): Check error return from accept() call
- by its equality to -1 not by it being negative.
- (MYread_charwait): Likewise.
- * main.c (main): Likewise for both socket() and accept() calls.
-
-2010-04-14 Mike Frysinger <vapier@gentoo.org>
-
- * wrapper.c (sim_write): Add const to buffer arg.
-
-2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
-
- * configure: Regenerate.
-
-2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
-
- * config.in: Regenerate.
- * configure: Likewise.
-
- * configure: Regenerate.
-
-2008-11-24 Joel Sherrill <joel.sherrill@oarcorp.com>
-
- * arminit.c, iwmmxt.c: Include <string.h> to
- eliminate warning.
-2008-07-11 Hans-Peter Nilsson <hp@axis.com>
-
- * configure: Regenerate to track ../common/common.m4 changes.
- * config.in: Ditto.
-
-2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
- Daniel Jacobowitz <dan@codesourcery.com>
- Joseph Myers <joseph@codesourcery.com>
-
- * configure: Regenerate.
- * wrapper.c (sim_target_display_usage): Add help parameter.
-
-2007-02-27 Mark Mitchell <mark@codesourcery.com>
-
- * armos.c (SWIflen): Do not treate file descriptor zero as
- special.
-
-2007-02-15 Nick Clifton <nickc@redhat.com>
-
- * armemu.c (handle_v6_insn): Fix typo in sign extension test of
- the sext and sxtah instructions.
-
-2007-02-08 Daniel Jacobowitz <dan@codesourcery.com>
-
- Reported by timeless@gmail.com:
- * wrapper.c (sim_target_parse_arg_array): Do not return void value.
-
-2006-12-21 Hans-Peter Nilsson <hp@axis.com>
-
- * acconfig.h: Remove.
- * config.in: Regenerate.
-
-2006-06-13 Richard Earnshaw <rearnsha@arm.com>
-
- * configure: Regenerated.
-
-2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
-
- * configure: Regenerated.
-
-2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
-
- * configure: Regenerated.
-
-2006-03-07 Paul Brook <paul@codesourcery.com>
-
- * elfos.c (ARMul_OSHandleSWI): Call correct function for IsTTY.
-
-2006-02-01 Shaun Jackman <sjackman@gmail.com>
-
- * armos.c (ARMul_OSHandleSWI): Handle the RedBoot system
- call meminfo. Return ENOSYS for unhandled RedBoot syscalls.
-
-2005-11-23 Mark Mitchell <mark@codesourcery.com>
-
- * wrapper.c (gdb/signals.h): Include it.
- (SIGTRAP): Don't define.
- (SIGBUS): Likewise.
- (sim_stop_reason): Use TARGET_SIGNAL_* instead of SIG*.
-
-2005-11-16 Shaun Jackman <sjackman@gmail.com>
-
- * armos.c: Include limits.h
- (unlink): Remove this macro. It is unused in this file and
- conflicts with sim_callback->unlink.
- (PATH_MAX): Define as 1024 if not already defined.
- (ReadFileName): New function.
- (SWIopen): Fix a potential buffer overflow.
- (SWIremove): New function.
- (SWIrename): Ditto.
- (ARMul_OSHandleSWI): Handle the RDP calls SWI_IsTTY,
- SWI_Remove, and SWI_Rename, as well as the RDI calls
- AngelSWI_Reason_IsTTY, AngelSWI_Reason_Remove, and
- AngelSWI_Reason_Rename.
-
-2005-09-19 Paul Brook <paul@codesourcery.com>
-
- * armdefs.h: Define ARMsword and ARMsdword. Use stdint.h when
- available.
- * armemu.c: Use them.
- * armvirt.c (ARMul_MemoryInit): Use correct type for size.
- * configure.ac: Check for stdint.h.
- * config.in: Regenerate.
- * configure: Regenerate.
-
-2005-05-24 Nick Clifton <nickc@redhat.com>
-
- * thumbemu.c (handle_v6_thumb_insn): New function.
- (ARMul_ThumbDecode): Call handle_v6_thumb_insn() when an undefined
- instruction binary is encountered.
-
-2005-05-12 Nick Clifton <nickc@redhat.com>
-
- * Update the address and phone number of the FSF organization in
- the GPL notices in the following files:
- COPYING, Makefile.in, armcopro.c, armdefs.h, armemu.c,
- armemu.h, armfpe.h, arminit.c, armopts.h, armos.c, armos.h,
- armrdi.c, armsupp.c, armvirt.c, bag.c, bag.h, communicate.c,
- communicate.h, dbg_conf.h, dbg_cp.h, dbg_hif.h, dbg_rdi.h,
- gdbhost.c, gdbhost.h, iwmmxt.c, iwmmxt.h, kid.c, main.c,
- maverick.c, parent.c, thumbemu.c, wrapper.c
-
-2005-04-20 Nick Clifton <nickc@redhat.com>
-
- * armemu.c (handle_v6_insn): New function - emulate a few of the
- v6 instructions - the ones now generated by GCC.
- (ARMulEmulate32): Call handle_v6_insn when a possible v6 insn is
- found.
- * armdefs.h (struct ARMul_State): Add new field: is_v6.
- (ARM_v6_Prop): Define.
- * arminit.c (ARMul_NewState): Initialise the v6 flag.
- (ARMul_SelectProcessor): Determine if the v6 flag should be
- set.
- * wrapper.c (sim_create_inferior): For unknown architectures,
- default to allowing the v6 instructions.
-
-2005-04-18 Nick Clifton <nickc@redhat.com>
-
- * iwmmxt.c (WMAC, WMADD): Move casts from the LHS of an assignment
- operator to the RHS.
- (WSLL, WSRA, WSRL, WUNPCKEH, WUNPACKEL): Use ULL suffix to
- indicate an unsigned long long constant.
-
-2005-03-23 Mark Kettenis <kettenis@gnu.org>
-
- * configure: Regenerate.
-
-2005-01-14 Andrew Cagney <cagney@gnu.org>
-
- * configure.ac: Sinclude aclocal.m4 before common.m4. Add
- explicit call to AC_CONFIG_HEADER.
- * configure: Regenerate.
-
-2005-01-12 Andrew Cagney <cagney@gnu.org>
-
- * configure.ac: Update to use ../common/common.m4.
- * configure: Re-generate.
-
-2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2005-01-07 Andrew Cagney <cagney@gnu.org>
-
- * configure.ac: Rename configure.in, require autoconf 2.59.
- * configure: Re-generate.
-
-2004-12-08 Hans-Peter Nilsson <hp@axis.com>
-
- * configure: Regenerate for ../common/aclocal.m4 update.
-
-2004-06-28 Andrew Cagney <cagney@gnu.org>
-
- * armemu.c: Rename ui_loop_hook to deprecated_ui_loop_hook.
-
-2003-12-29 Mark Mitchell <mark@codesourcery.com>
-
- * armos.c (fcntl.h): Do not include it.
- (O_RDONLY): Do not define.
- (O_WRONLY): Likewise.
- (O_RDWR): Likewise.
- (targ-vals.h): Include it.
- (translate_open_mode): Use TARGET_O_* instead of O_*.
- (SWIopen): Likewise.
- * Makefile.in (armos.o): Depend on targ-vals.h.
-
-2003-04-13 Nick Clifton <nickc@redhat.com>
-
- * armvirt.c (GetWord): Only call XScale_check_memacc if in XScale
- mode.
- (PutWord): Likewise.
-
-2003-03-30 Nick Clifton <nickc@redhat.com>
-
- * configure.in (CON_FLAGS): Remove.
- (COPRO): Unconditionally include iwmmxt.o.
- * configure: Regenerate.
- * Makefile.in (CON_FLAGS): Remove.
- * armcopro.c: Remove use of __IWMMXT__ flag.
- * wrapper.c: Likewise.
- * armemu.c: Likewise.
- Add explanatory comment for suppressed code.
-
-2003-03-27 Nick Clifton <nickc@redhat.com>
-
- * armos.c (ARMul_OsHandleSWI): Catch SWIs for unhandled vectors.
-
-2003-03-27 Nick Clifton <nickc@redhat.com>
-
- * configure.in: (CON_FLAGS): Define and intialise.
- (COPRO): Add iwmmxt.o if configuring for XScale.
- * configure: Regenerate.
- * Makefile.in (iwmmxt.o): Add rule to build.
- (COM_FLAGS): Define.
- (ALL_FLAGS): Add CON_FLAGS.
- * armcopro.c (ARMul_CoProInit): Initialise iWMMXt coprocessors.
- * armdefs.h (struct ARMul_State): Add 'is_iWMMXt' field.
- (ARM_iWMMXt_Prop): Define.
- * armemu.c (ARMul_Emulate16): Intercept iWMMXt instructions and
- pass to coprocessor.
- * arminit.c (ARMul_NewState): Initialise 'is_iWMMXt'.
- (ARMul_Abort): Catch branches through uninitialised vectors.
- * armos.c (softevtorcode): Update comment.
- (ARMul_OsInit): Use ARMUndefinedInstrV.
- * wrapper.c (sim_create_inferior): Handle iWMMXt processor type.
- (sim_store_register): Handle iWMMXt registers.
- (sim_fetch_register): Handle iWMMXt registers.
- * iwmmxt.h: New file. Exported iWMMXt coprocessor emulator
- functions.
- * iwmmxt.c: New file: iWMMXt emulator.
-
-2003-03-20 Nick Clifton <nickc@redhat.com>
-
- * Contribute support for Cirrus Maverick ARM co-processor,
- written by Aldy Hernandez <aldyh@redhat.com> and
- Andrew Cagney <cagney@redhat.com>:
-
- * maverick.c: New file: Support for Maverick floating point
- co-processor.
- * Makefile.in: Add maverick.o target.
- * configure.in (COPRO): Add maverick.o.
- * configure: Regenerate.
- * armcopro.c (ARMul_CoProInit): Only initialise co-processors
- available on target processor. Add code to initialse Maverick
- co-processor support code.
- * armdefs.h (ARMul_state): Add is_ep9312 field.
- (ARM_ep9312_Prop): Define.
- * armemu.h: Add prototypes for Maverick co-processor
- functions.
- * arminit.c (ARMul_SelectProcessor): Initialise the
- co-processor support once the chip has been selected.
- * wrapper.c: Add support for Maverick co-processor.
- (init): Do not call ARMul_CoProInit. Delays this until the
- chip has been selected.
-
-2003-03-02 Nick Clifton <nickc@redhat.com>
-
- * armos.c (SWIWrite0): Catch big-endian bug when printing
- characters.
-
-2003-02-27 Andrew Cagney <cagney@redhat.com>
-
- * wrapper.c (sim_create_inferior, sim_open): Rename _bfd to bfd.
-
-2003-01-10 Ben Elliston <bje@redhat.com>
-
- * README.Cygnus: Rename from this ..
- * README: .. to this.
-
-2002-09-27 Andrew Cagney <ac131313@redhat.com>
-
- * wrapper.c (sim_open): Add support for -m<mem-size>.
- (mem_size): Reduce to 2MB.
- Fix PR gdb/433.
-
-2002-08-15 Nick Clifton <nickc@redhat.com>
-
- * armos.c (ARMul_OSHandleSWI): Catch and ignore SWIs of -1, they
- can be caused by an interrupted system call being resumed by GDB.
-
-2002-07-05 Nick Clifton <nickc@cambridge.redhat.com>
-
- * armemu.c (ARMul_Emulate32): Add more tests for valid MIA, MIAPH
- and MIAxy instructions.
-
-2002-06-21 Nick Clifton <nickc@cambridge.redhat.com>
-
- * armos.h (ADP_Stopped_RunTimeError): Set correct value.
-
-2002-06-16 Andrew Cagney <ac131313@redhat.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2002-06-12 Andrew Cagney <ac131313@redhat.com>
-
- * Makefile.in: Update copyright.
- (wrapper.o): Specify dependencies.
- * wrapper.c: Include "gdb/sim-arm.h".
- (sim_store_register, sim_fetch_register): Rewrite using `enum
- arm_sim_regs' and a switch.
-
-2002-06-09 Andrew Cagney <cagney@redhat.com>
-
- * wrapper.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
- * armos.c: Include "gdb/callback.h".
-
-2002-05-29 Nick Clifton <nickc@cambridge.redhat.com>
-
- * armcopro.c (XScale_check_memacc): Set the FSR and FAR registers
- if a Data Abort is detected.
-
-2002-05-27 Nick Clifton <nickc@cambridge.redhat.com>
-
- * armvirt.c (GetWord): Only perform access checks if 'check'
- is set.
- (PutWord): Likewise.
- * wrapper.c (sim_create_inferior): Report unknown machine
- numbers.
- * thumbemu.c (ARMul_ThumbDecode, Case 31): Do not set LR to pc +
- 2, it has already been advanced.
-
-2002-05-23 Nick Clifton <nickc@cambridge.redhat.com>
-
- * thumbemu.c (ARMul_ThumbDecode): When decoding a BLX(1)
- instruction do not add in the second bit of the base address -
- this has already been accounted for.
-
-2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
-
- * armcopro.c (check_cp13_access): Allow access to register 1 when
- CRm is 1.
- (write_cp13_reg): Allow bit 0 of reg 1 of CRm 1 to be written to.
-
-2002-05-17 Nick Clifton <nickc@cambridge.redhat.com>
-
- * Makefile.in (SIM_TARGET_SWITCHES): Define.
- * armos.c (swi_mask): Define. Initialise to supporting all
- SWI emulations.
- (ARMul_OSInit): For XScale targets, only support the ANGEL
- SWI interface. (This is at the request if Intel).
- (ARMul_OSHandleSWI): Examine swi_mask to see if a particular
- SWI call should be emulated.
- Do not fall through from AngelSWI_Reason_WriteC.
- Propagate exit code from RedBoot Exit SWI.
- * rdi-dgb.h (swi_mask): Prototype.
- (SWI_MASK_DEMON, SWI_MASK_ANGEL, SWI_MASK_REDBOOT): Define.
- * wrapper.c (sim_target_parse_command_line): New function.
- Look for and handle --swi-support switch.
- (sim_target_parse_arg_array): New function. Process an argv
- array for parsing by sim_target_parse_command_line.
- (sim_target_display_usage): New function. Describe syntax of
- --swi-suppoort switch.
- (sim_open): Add call to sim_target_parse_arg_array).
-
-2002-05-09 Nick Clifton <nickc@cambridge.redhat.com>
-
- * armos.c (ARMul_OSHandleSWI): Support the RedBoot SWI in ARM
- mode and some of its system calls.
-
-2002-03-17 Anthony Green <green@redhat.com>
-
- * wrapper.c (mem_size): Increase the default target memory to 8MB.
-
-2002-02-21 Keith Seitz <keiths@redhat.com>
-
- * armos.c (SWIWrite0): Use generic host_callback mechanism
- for supported OS functions "open", "close", "write", etc.
- (SWIopen): Likewise.
- (SWIread): Likewise.
- (SWIwrite): Likewise.
- (SWIflen): Likewise.
- (ARMul_OSHandleSWI): Likewise.
-
-2002-02-05 Nick Clifton <nickc@cambridge.redhat.com>
-
- * wrapper.c (sim_create_inferior): Modify previous patch so that
- it is only triggered for COFF format executables.
-
-2002-02-04 Nick Clifton <nickc@cambridge.redhat.com>
-
- * wrapper.c (sin_create_inferior): If a v5 architecture is
- detected, assume it might be an XScale binary, since there is no
- way to distinguish between the two in the COFF file format.
-
-2002-01-10 Nick Clifton <nickc@cambridge.redhat.com>
-
- * arminit.c (ARMul_Abort): Fix parameters passed to CPRead[13].
- * armemu.c (ARMul_Emulate32): Fix parameters passed to CPRead[13]
- and CPRead[14].
- Fix formatting. Improve layout.
- * armemu.h: Fix formatting. Improve layout.
-
-2002-01-09 Nick Clifton <nickc@cambridge.redhat.com>
-
- * wrapper.c (sim_fetch_register): If fetching more than 4 bytes
- return zeroes in the other words.
- General formatting tidy ups.
-
-2001-11-16 Ben Harris <bjh21@netbsd.org>
-
- * Makefile.in (armemu32.o): Replace $< with autoconf recommended
- $(srcdir)/....
- (armemu26.o): Ditto.
-
-2001-10-18 Nick Clifton <nickc@cambridge.redhat.com>
-
- * armemu.h (CP_ACCESS_ALLOWED): New macro.
- Fix formatting.
- * armcopro.c (read_cp14_reg): Make static.
- (write_cp14_reg): Make static.
- (check_cp13_access): Use CP_ACCESS_ALLOWED macro.
- Fix formatting.
- * armsupp.c (ARMul_LDC): Check CP_ACCESS_ALLOWED.
- (ARMul_STC): Check CP_ACCESS_ALLOWED.
- (ARMul_MCR): Check CP_ACCESS_ALLOWED.
- (ARMul_MRC): Check CP_ACCESS_ALLOWED.
- (ARMul_CDP): Check CP_ACCESS_ALLOWED.
- Fix formatting.
- * armemu.c (MCRR): Check CP_ACCESS_ALLOWED. Test Rd and Rn not
- equal to 15.
- (MRRC): Check CP_ACCESS_ALLOWED. Test Rd and Rn not equal to 15.
- Fix formatting.
-
-2001-05-11 Nick Clifton <nickc@cambridge.redhat.com>
-
- * armemu.c (ARMul_Emulate32): Fix handling of XScale LDRD and STRD
- instructions with post indexed addressing modes.
-
-2001-05-08 Jens-Christian Lache <lache@tu-harburg.de>
-
- * armsupp.c (ARMul_FixCPSR): Check Mode not Bank in order to
- determine rocesor mode.
-
-2001-04-18 matthew green <mrg@redhat.com>
-
- * armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
- (read_cp15_reg): Make non-static.
- (XScale_cp15_LDC): Update for write_cp15_reg() change.
- (XScale_cp15_MCR): Likewise.
- (XScale_cp15_write_reg): Likewise.
- (XScale_check_memacc): New function. Check for breakpoints being
- activated by memory accesses. Does not support the Branch Target
- Buffer.
- (XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
- (XScale_debug_moe): New function. Set the debug Method Of Entry,
- if configured.
- (write_cp14_reg): Reset count counter if requested.
- * armdefs.h (struct ARMul_State): New members `LastTime' and
- `CP14R0_CCD' used for the timer/counters.
- (ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
- ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
- ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
- ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
- ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
- ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
- ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
- ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
- defines for XScale registers.
- (XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
- (ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
- (ARMul_Emulate32): Handle the clock counter and hardware instruction
- breakpoints. Call XScale_set_fsr_far() for software breakpoints and
- software interrupts.
- (LoadMult): Call XScale_set_fsr_far() for data aborts.
- (LoadSMult): Likewise.
- (StoreMult): Likewise.
- (StoreSMult): Likewise.
- * armemu.h (write_cp15_reg): Update prototype.
- * arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
- (ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
- register 0.
- * armvirt.c (GetWord): Call XScale_check_memacc().
- (PutWord): Likewise.
-
-2001-03-20 Nick Clifton <nickc@redhat.com>
-
- * armvirt.c (ARMul_ReLoadInstr): Do not enable alignment checking
- when loading unaligned thumb instructions.
-
-2001-03-06 Nick Clifton <nickc@redhat.com>
-
- * thumbemu.c (ARMul_ThumbDecode): Delete label bo_blx2.
- Compute destination address of BLX(1) instruction by
- taking bit 1 from PC and not from bit 0 of the offset.
-
-2001-02-27 Nick Clifton <nickc@redhat.com>
-
- * armvirt.c (GetWord): Add new parameter - check - to enable or
- disable the alignment checking.
- (PutWord): Add new parameter - check - to enable or disable the
- alignment checking.
- (ARMul_ReLoadInstr): Pass extra parameter to GetWord.
- (ARMul_ReadWord): Pass extra parameter to GetWord.
- (ARMul_WriteWord): Pass extra parameter to PutWord.
- (ARMul_StoreHalfWord): Pass extra parameter to PutWord.
- (ARMul_WriteByte): Pass extra parameter to GetWord.
- (ARMul_SwapWord): Pass extra parameter to PutWord.
- (ARMul_SafeReadByte): New Function: Read a byte but do not abort.
- (ARMul_SafeWriteByte): New Function: Write a byte but do not abort.
-
- * armdefs.h: Add prototypes for ARMul_SafeReadByte and
- ARMul_SafeWriteByte.
-
- * wrapper.c (sim_write): Use ARMul_SafeWriteByte.
- (sim_read): Use ARMul_SafeReadByte.
-
- * armos.c (in_SWI_handler): Remove.
- (SWIWrite0): Use ARMul_SafeReadByte.
- (WriteCommandLineTo): Use ARMul_SafeWriteByte.
- (SWIopen): Use ARMul_SafeReadByte.
- (SWIread): Use ARMul_SafeWriteByte.
- (SWIwrite): Use ARMul_SafeReadByte.
- (ARMul_OSHandleSWI): Remove use of is_SWI_handler.
- (ARMul_OSException): Remove use of is_SWI_handler.
-
-2001-02-16 Nick Clifton <nickc@redhat.com>
-
- * armemu.c: Remove Prefetch abort for breakpoints. Instead set
- the state to RESUME.
-
-2001-02-14 Nick Clifton <nickc@redhat.com>
-
- * armemu.c: Add code to preserve processor mode when a prefetch
- abort is signalled after processing a breakpoint.
-
- * wrapper.c (sim_create_inferior): Reset processor into ARM mode
- for any machine type except the early ARMs.
-
-2001-02-13 Nick Clifton <nickc@redhat.com>
-
- * armos.c (in_SWI_handler): New static variable.
- (ARMul_OSHandleSWI): Set in_SWI_handler whilst emulating a SWI.
- (ARMul_OSException): Ignore exceptions generated whilst emulating
- a SWI.
-
-2001-02-12 Nick Clifton <nickc@redhat.com>
-
- * armemu.h (NEGBRANCH): Fix defintion.
-
-2001-02-01 Nick Clifton <nickc@redhat.com>
-
- * armemu.c (LoadSMult): Update base address register after
- restoring register bank.
- (StoreMult): Update base address register after restoring register
- bank.
-
-2001-01-31 Nick Clifton <nickc@redhat.com>
-
- * armvirt.c (PutWord): Detect installation of SWI vector.
- (SWI_vector_installed): Define.
- * armos.c (ARMul_OsInit): Reset SWI_vector_installed.
- * armos.h (SWI_vector_installed): Declare.
- * wrapper.c (SWI_vector_installed): Remove definition.
- (sim_write): Remove check of SWI vector installation
-
-2000-12-18 Nick Clifton <nickc@redhat.com>
-
- * armemu.c (ARMul_Emulate26): Fix test for StoreDouble
- instruction.
-
-2000-12-10 Nick Clifton <nickc@redhat.com>
-
- * armos.c (ARMul_OSHandleSWI): Add 0x91 as an FPE SWI.
-
-2000-12-07 Nick Clifton <nickc@redhat.com>
-
- * armemu.c (ARMul_Emulate26): Detect double word load and
- store instructions and call emulation routines.
- (Handle_Load_Double): Emulate a double word load instruction.
- (Handle_Store_Double): Emulate a double word store
- instruction.
-
-2000-12-03 Nick Clifton <nickc@redhat.com>
-
- * armos.c: Fix formatting.
- (ARMul_OSHandleSWI): Suppress support of DEMON SWIs when in xscale
- mode.
-
-2000-11-29 Nick Clifton <nickc@redhat.com>
-
- * armdefs.h (State): Add 'v5e' and 'xscale' fields.
- (ARM_v5e_Prop): Define.
- (ARM_XScale_Prop): Define.
-
- * wrapper.c (sim_create_inferior): Select processor based on
- machine number.
- (SWI_vector_installed): New boolean. Set to true if the SWI
- vector address is written to by the executable.
-
- * arminit.c (ARMul_NewState): Switch default to 32 bit mode.
- (ARMul_SelectProcessor): Initialise v5e and xscale signals.
- (ARMul_Abort): Fix calculation of LR address.
-
- * armos.c (ARMul_OSHandleSWI): If a SWI vector has been installed
- and a SWI is not handled by the simulator, pass the SWI off to the
- vector, otherwise issue a warning message and continue.
-
- * armsupp.c (ARMul_CPSRAltered): Set S bit aswell.
-
- * thumbemu.c: Add v5 instruction simulation.
- * armemu.c: Add v5, XScale and El Segundo instruction simulation.
-
- * armcopro.c: Add XScale co-processor emulation.
- * armemu.h: Add exported XScale co-processor functions.
-
-2000-09-15 Nick Clifton <nickc@redhat.com>
-
- * armdefs.h: Rename StrongARM property to v4_ARM and add v5 ARM
- property. Delete unnecessary processor names.
- (ARM_Strong_Prop): Delete.
- (STRONGARM): Delete.
- (ARM_v4_Prop): Add.
- (ARM_v5_Prop): Add
- (State): Delete is_StrongARM boolean. Add is_v4 and is_v5
- booleans.
-
- * armemu.h (BUSUSEDINCPCS): Use is_v4 boolean.
- (BUSUSEDINCPCN): Use is_v4 boolean.
-
- * arminit.c (ARMul_NewState): Initialise is_v4 and is_v5 fields.
- (ARMul_SelectProcessor): Change second parameter from 'processor'
- to 'properties'. Set is_v4 and is_v5 booleans in State.
-
- * armrdi.c: Remove use of ARM processor names. Replace with ARM
- processor properties.
-
- * wrapper.c (sim_create_inferior): Choose properties passed to
- ARMul_SelectProcessor based on machine number.
-
-2000-08-14 Nick Clifton <nickc@redhat.com>
-
- * armemu.c (LHPOSTDOWN): Compute write back value before
- performing load in case the offset register is overwritten.
- (LHPOSTUP): Ditto.
-
-2000-07-14 Fernando Nasser <fnasser@cygnus.com>
-
- * wrapper.c (sim_create_inferior): Fix typo in the previous patch.
-
-2000-07-14 Fernando Nasser <fnasser@cygnus.com>
-
- * wrapper.c (sim_create_inferior): Reset mode to ARM when creating a
- new inferior.
-
-2000-07-04 Alexandre Oliva <aoliva@redhat.com>
-
- * armvirt.c (ABORTS): Do not define.
-
- * armdefs.h (struct ARMul_State): Add is_StrongARM.
- (ARM_Strong_Prop, STRONGARM): Define.
- * arminit.c (ARMul_NewState): Reset is_StrongARM.
- (ARMul_SelectProcessor): Set is_StrongARM.
- * wrapper.c (sim_create_inferior): Use bfd machine type to
- determine processor type to emulate.
- * armemu.h (BUSUSEDINCPCS, BUSUSEDINCPCN): Don't increment PC
- when emulating StrongARM.
-
- * armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.
-
- * armemu.h (INSN_SIZE): New macro.
- (SET_ABORT): Save CPSR in SPSR and set LR.
- * armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE.
- (WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode.
- * arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
-
- * armemu.c (LoadSMult): Use WriteR15() to discard the least
- significant bits of PC.
-
- * armemu.h (WRITEDESTB): New macro.
- * armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to
- modify PC. Moved the existing logic...
- (WriteR15Branch): ... here. New function.
- (WriteR15, WriteSR15): Drop the two least significant bits.
- (LoadSMult): Use WriteR15Branch() to modify PC.
- (LoadMult): Use WRITEDESTB() instead of WRITEDEST().
-
- * armemu.h (GETSPSR): Call ARMul_GetSPSR().
- * armsupp.c (ARMul_CPSRAltered): Zero out bits as they're
- extracted from state->Cpsr, but preserve the unused bits.
- (ARMul_GetCPSR): Get bits preserved in state->Cpsr.
- (ARMul_GetSPSR, ARMul_FixCPSR): Use ARMul_GetCPSR() to
- get the full CPSR word.
-
- * armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.
- (SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
- (SETPSR, SET_INTMODE, SETCC): Removed.
- * armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
- mask. Use SETPSR_* to modify PSR.
- (ARMul_SetCPSR): Load all bits from value.
- * armemu.c (ARMul_Emulate, msr): Do not test bit mask.
-
- * armemu.c (ARMul_Emulate): Compute writeback value before
- loading, since the offset register may be the destination
- register.
-
- * armdefs.h (SYSTEMBANK): Define as USERBANK.
- * armsupp.c (ARMul_SwitchMode): Remove SYSTEMBANK cases.
-
-2000-06-22 Alexandre Oliva <aoliva@cygnus.com>
-
- * armemu.c (Multiply64): Fix computation of flag N.
-
- * armemu.c (MultiplyAdd64): Fix computation of flag N.
-
-2000-06-20 Alexandre Oliva <aoliva@cygnus.com>
-
- * armemu.h (NEGBRANCH): Do not overwrite the two most significant
- bits of the offset.
-
-2000-05-25 Nick Clifton <nickc@cygnus.com>
-
- * armcopro.c (MMUMCR): Only indicate mode change if a singal has
- really changed.
- (MMUWrite): Only indicate mode change if a singal has really
- changed.
-
- * armdefs.h (SYSTEMMODE): Define.
- (BANK_CAN_ACEESS_SPSR): Define.
-
- * armemu.c (ARM_Emulate26): If the mode has changed allow the PC
- to advance before stopping the emulation.
-
- * arminit.c (ARMul_Reset): Ensure Mode field of State is set
- correctly.
-
- * armos.c (ARMul_OSInit): Create a initial stack pointer for
- System mode.
-
- * armsupp.c (ModeToBank): Remove unused first parameter.
- Add support for System Mode.
- (ARMul_GetSPSR): Use BANK_CAN_ACCESS_SPSR macro.
- (ARMul_SetSPSR): Use BANK_CAN_ACCESS_SPSR macro.
- (ARMul_FixSPSR): Use BANK_CAN_ACCESS_SPSR macro.
- (ARMulSwitchMode): Add support for System Mode.
-
-Wed May 24 14:40:34 2000 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2000-05-23 Nick Clifton <nickc@cygnus.com>
-
- * wrapper.c (sim_store_register): Special handling for CPSR
- register.
-
-2000-03-11 Philip Blundell <philb@gnu.org>
-
- * armemu.c (LoadSMult, LoadMult): Correct handling of aborts.
- Patch from Allan Skillman <Allan.Skillman@arm.com>.
-
-Wed Mar 22 15:24:21 2000 glen mccready <gkm@pobox.com>
-
- * wrapper.c (sim_open,sim_close): Copy into myname, free myname.
-
-2000-02-08 Nick Clifton <nickc@cygnus.com>
-
- * wrapper.c: Fix compile time warning messages.
- * armcopro.c: Fix compile time warning messages.
- * armdefs.h: Fix compile time warning messages.
- * armemu.c: Fix compile time warning messages.
- * armemu.h: Fix compile time warning messages.
- * armos.c: Fix compile time warning messages.
- * armsupp.c: Fix compile time warning messages.
- * armvirt.c: Fix compile time warning messages.
- * bag.c: Fix compile time warning messages.
-
-2000-02-02 Bernd Schmidt <bernds@cygnus.co.uk>
-
- * *.[ch]: Use indent to make readable.
-
-1999-11-22 Nick Clifton <nickc@cygnus.com>
-
- * armos.c (SWIread): Generate an error message if a huge read is
- performed.
- (SWIwrite): Generate an error message if a huge write is
- performed.
-
-1999-10-27 Nick Clifton <nickc@cygnus.com>
-
- * thumbemu.c (ARMul_ThumbDecode): Accept 0xbebe as a thumb
- breakpoint.
-
-1999-10-08 Ulrich Drepper <drepper@cygnus.com>
-
- * armos.c (SWIopen): Always pass third parameter with 0666 since
- otherwise uninitialized memory gets access if the O_CREAT bit is
- set and so we possibly cannot access the file afterwards.
-
-1999-09-29 Doug Evans <devans@casey.cygnus.com>
-
- * armos.c (SWIWrite0): Send output to stdout instead of stderr.
- (ARMul_OSHandleSWI, case SWI_WriteC,AngelSWI_Reason_WriteC): Ditto.
-
-Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-1999-05-08 Felix Lee <flee@cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-1999-04-06 Keith Seitz <keiths@cygnus.com>
-
- * wrapper.c (stop_simulator): New global.
- (sim_stop): Set sim state to STOP and set
- stop_simulator.
- (sim_resume): Reset stop_simulator.
- (sim_stop_reason): If stop_simulator is set, tell gdb
- that the we took SIGINT.
- * armemu.c (ARMul_Emulate26): Don't loop forever. Stop if
- stop_simulator is set.
-
-1999-04-02 Keith Seitz <keiths@cygnus.com>
-
- * armemu.c (ARMul_Emulate26): If NEED_UI_LOOP_HOOK, call ui_loop_hook
- whenever the counter expires.
- * Makefile.in (SIM_EXTRA_CFLAGS): Include define NEED_UI_LOOP_HOOK.
-
-1999-03-24 Nick Clifton <nickc@cygnus.com>
-
- * armemu.c (ARMul_Emulate26): Handle new breakpoint value.
- * thumbemu.c (ARMul_ThumbDecode): Handle new breakpoint value.
-
-Mon Sep 14 09:00:05 1998 Nick Clifton <nickc@cygnus.com>
-
- * wrapper.c (sim_open): Set endianness according to BFD or command
- line switch.
-
- * tconfig.in: Define SIM_HAVE_BIENDIAN.
-
-Thu Aug 27 11:00:05 1998 Nick Clifton <nickc@cygnus.com>
-
- * armemu.c (Multiply64): Test for Rm (rather than Rs) not being
- the same as either RdHi or RdLo.
-
-Thu Jul 2 10:24:35 1998 Nick Clifton <nickc@cygnus.com>
-
- * armos.c (ARMul_OSHandleSWI: AngelSWI_Reason_ReportException):
- Set Reg[0] based on reason for for the exception.
-
-Thu Jun 4 15:22:03 1998 Jason Molenda (crash@bugshack.cygnus.com)
-
- * armos.c (SWIwrite0): New function.
- (WriteCommandLineTo): New function.
- (SWIopen): New function.
- (SWIread): New function.
- (SWIwrite): New function.
- (SWIflen): New function.
- (ARMul_OSHandleSWI): Call new functions instead of handling
- these here.
- (ARMul_OSHandleSWI): Handle Angel SWIs correctly.
- (*): Reformat spacing to be a bit more GNUly.
- Most code taken from a patch by Anthony Thompson
- (athompso@cambridge.arm.com)
-
-Tue Jun 2 15:22:22 1998 Nick Clifton <nickc@cygnus.com>
-
- * armos.h: Add Angel SWI and its reason codes.
- * armos.c (ARMul_OSHandleSWI): Ignore Angel SWIs (for now).
-
-Mon Jun 1 17:14:19 1998 Anthony Thompson (athompso@cambridge.arm.com)
-
- * armos.c (ARMul_OSHandleSWI::SWI_Open): Handle special case
- of ":tt" to catch stdin in addition to stdout.
- (ARMul_OSHandleSWI::SWI_Seek): Return 0 or 1 to indicate failure
- or success of lseek().
-
-Wed May 20 17:36:25 1998 Nick Clifton <nickc@cygnus.com>
-
- * armos.c (ARMul_OSHandleSWI): Special case code to catch attempts
- to open stdout.
-
-Wed Apr 29 15:29:55 1998 Jeff Johnston <jjohnstn@cygnus.com>
-
- * armos.c (ARMul_OSHandleSWI): Added code for SWI_Clock,
- SWI_Flen, and SWI_Time. Also fixed SWI_Seek code to only
- seek from offset 0 and not to use R2 for whence since it is
- not passed as part of the SWI call.
-
-Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Sun Apr 26 15:20:26 1998 Tom Tromey <tromey@cygnus.com>
-
- * acconfig.h: New file.
- * configure.in: Reverted change of Apr 24; use sinclude again.
-
-Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Fri Apr 24 11:20:19 1998 Tom Tromey <tromey@cygnus.com>
-
- * configure.in: Don't call sinclude.
-
-Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Mar 10 09:26:38 1998 Nick Clifton <nickc@cygnus.com>
-
- * armopts.h: Remove definition of LITTLEND - it is not used.
-
-Tue Feb 17 12:35:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * wrapper.c (sim_store_register, sim_fetch_register): Pass in
- length parameter. Return -1.
-
-Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Tue Dec 9 11:30:48 1997 Nick Clifton <nickc@cygnus.com>
-
- * Makefile.in: Updated with changes from branch.
- * armdefs.h: ditto
- * armemu.c: ditto these changes
- * armemu.h: ditto add support for
- * armos.c: ditto the Thumb instruction
- * armsupp.c: ditto set and the new v4
- * armvirt.c: ditto architecture.
- * wrapper.c: ditto
- * thumbemu.c: New file from branch.
-
-
-Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Thu Oct 30 13:54:06 1997 Nick Clifton <nickc@cygnus.com>
-
- * armos.c (ARMul_OSHandleSWI): Add support for GetEnv SWI. Patch
- from Tony Thompson at ARM: athompso@arm.com
-
- * wrapper.c (sim_create_inferior): Add code to create an execution
- environment. Patch from Tony Thompson at ARM: athompso@arm.com
-
-Wed Oct 22 14:43:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * wrapper.c (sim_load): Pass lma_p and sim_write args to
- sim_load_file.
-
-Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Tue Aug 26 10:37:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * wrapper.c (sim_kill): Delete.
- (sim_create_inferior): Add ABFD argument.
- (sim_load): Move setting of PC from here.
- (sim_create_inferior): To here.
-
-Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Mon Aug 25 15:35:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * wrapper.c (sim_open): Add ABFD argument.
-
-Tue May 20 10:13:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * wrapper.c (sim_open): Add callback argument.
- (sim_set_callbacks): Drop SIM_DESC argument.
-
-Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Apr 18 13:32:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * wrapper.c (sim_stop): Stub sim_stop function.
-
-Thu Apr 17 18:33:01 1997 Fred Fish <fnf@cygnus.com>
-
- * arminit.c (ARMul_NewState): Preinitialize the state to
- all zero/NULL.
-
-Thu Apr 17 02:39:02 1997 Doug Evans <dje@canuck.cygnus.com>
-
- * Makefile.in (SIM_OBJS): Add sim-load.o.
- * wrapper.c (sim_kind,myname): New static locals.
- (sim_open): Set sim_kind, myname.
- (sim_load): Call sim_load_file to do work. Set start address from bfd.
- (sim_create_inferior): Return SIM_RC. Delete start_address arg.
-
-Thu Apr 17 11:48:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
-
- * wrapper.c (sim_trace): Update so that it matches prototype.
-
-Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
- * config.in: Ditto.
-
-Mon Apr 7 12:01:17 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
-
- * Makefile.in (armemu32.o): Replace $< with autoconf recommended
- $(srcdir)/....
- (armemu26.o): Ditto.
-
-Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
-
- * wrapper.c (sim_open): New arg `kind'.
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Apr 2 14:50:44 1997 Ian Lance Taylor <ian@cygnus.com>
-
- * COPYING: Update FSF address.
-
-Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
-
- * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
-
- * configure: Re-generate.
-
-Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
-
- * configure: Regenerate to track ../common/aclocal.m4 changes.
-
-Thu Mar 13 12:38:56 1997 Doug Evans <dje@canuck.cygnus.com>
-
- * wrapper.c (sim_open): Has result now.
- (sim_*): New SIM_DESC argument.
-
-Tue Feb 4 13:22:21 1997 Doug Evans <dje@canuck.cygnus.com>
-
- * Makefile.in (@COMMON_MAKEFILE_FRAG@): Use
- COMMON_{PRE,POST}_CONFIG_FRAG instead.
- * configure.in: sinclude ../common/aclocal.m4.
- * configure: Regenerated.
-
-Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
-
- * configure configure.in Makefile.in: Update to new configure
- scheme which is more compatible with WinGDB builds.
- * configure.in: Improve comment on how to run autoconf.
- * configure: Re-run autoconf to get new ../common/aclocal.m4.
- * Makefile.in: Use autoconf substitution to install common
- makefile fragment.
-
-Wed Nov 20 01:05:10 1996 Doug Evans <dje@canuck.cygnus.com>
-
- * run.c: Deleted, use one in ../common now.
- * Makefile.in: Delete everything that's been moved to
- ../common/Make-common.in.
- (SIM_OBJS): Define.
- * configure.in: Simplify using macros in ../common/aclocal.m4.
- * configure: Regenerated.
- * config.in: New file.
- * armos.c: #include config.h.
- * wrapper.c (mem_size): Value is in bytes now.
- (sim_callback): New global.
- (arm_sim_set_profile{,_size}): Delete.
- (arm_sim_set_mem_size): Rename to sim_size.
- (sim_do_command): Call printf_filtered via callback.
- (sim_set_callbacks): Record callback.
-
-Thu Oct 3 16:10:27 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
-
- * Makefile.in (mostlyclean): Remove config.log.
-
-Wed Jun 26 12:17:24 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
-
- * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
- INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
- (docdir): Removed.
- * configure.in (AC_PREREQ): autoconf 2.5 or higher.
- (AC_PROG_INSTALL): Added.
- * configure: Rebuilt.
-
-Wed Feb 21 12:14:31 1996 Ian Lance Taylor <ian@cygnus.com>
-
- * configure: Regenerate with autoconf 2.7.
-
-Fri Dec 15 16:27:30 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * run.c (main): Use new bfd_big_endian macro.
-
-Mon Nov 20 17:40:38 1995 Doug Evans <dje@canuck.cygnus.com>
-
- * run.c: Include "getopt.h".
- (verbose): Delete.
- (usage): Make static.
- (main): Call arm_sim_set_verbosity.
- Only load sections marked SEC_LOAD.
- * wrapper.c (mem_size, verbosity): New static global.
- (arm_sim_set_mem_size): Renamed from sim_size. Callers updated.
- (arm_sim_set_profile{,_size}): Renamed from sim_foo. Callers updated.
-
-Fri Nov 17 19:35:11 1995 Doug Evans <dje@canuck.cygnus.com>
-
- * armdefs.h (ARMul_State): New member `verbose'.
- * armrdi.c (ARMul_ConsolePrint): Add missing va_end.
- * run.c (verbose): Make global.
- * wrapper.c (init): Set state->verbose.
- (ARMul_ConsolePrint): Don't print anything if !verbose.
-
-Fri Oct 13 15:30:30 1995 Doug Evans <dje@canuck.cygnus.com>
-
- * armos.c: #include dbg_rdi.h.
- (ARMul_OSHandleSWI): Handle SWI_Breakpoint.
- * armos.h (SWI_Breakpoint): Define.
- * wrapper.c: #include armemu.h, dbg_rdi.h.
- (rc): Delete.
- (sim_resume): Use state->EndCondition to record stop state.
- Call FLUSHPIPE before returning.
- (sim_stop_reason): Determine reason from state->EndCondition.
-
-Fri Oct 13 15:04:05 1995 steve chamberlain <sac@slash.cygnus.com>
-
- * wrapper.c (sim_set_callbacks): New.
-
-Thu Sep 28 19:45:56 1995 Doug Evans <dje@deneb.cygnus.com>
-
- * armos.c (ARMul_OSHandleSWI): Result of read/write calls is
- number of bytes not read/written (or -1).
-
-Wed Sep 20 13:35:54 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * Makefile.in (maintainer-clean): New synonym for realclean.
-
-Fri Sep 8 14:27:20 1995 Ian Lance Taylor <ian@cygnus.com>
-
- * configure.in: Remove AC_PROG_INSTALL.
- * configure: Rebuild.
- * Makefile.in (INSTALL): Revert to using install.sh.
- (INSTALL_PROGRAM, INSTALL_DATA): Set to $(INSTALL).
- (INSTALL_XFORM, INSTALL_XFORM1): Restore.
- (mostlyclean): Make the same as clean, not distclean.
- (clean): Remove config.log.
- (install): Don't install in $(tooldir).
-
-Thu Sep 7 12:00:17 1995 Doug Evans <dje@canuck.cygnus.com>
-
- (Try to) Update to new bfd autoconf scheme.
- * run.c: Don't include sysdep.h.
- * Makefile.in (INSTALL{,_PROGRAM,_DATA}): Use autoconf computed value.
- (CC, CFLAGS, AR, RANLIB): Likewise.
- (HDEFINES, TDEFINES): Define.
- (CC_FOR_BUILD): Delete.
- (host_makefile_frag): Delete.
- (Makefile): Don't depend on frags.
- * configure.in (sysdep.h): Don't create symlink.
- (host_makefile_frag, frags): Deleted.
- (CC, CFLAGS, AR, RANLIB, INSTALL): Compute values.
- * configure: Regenerated.
-
-Thu Aug 3 10:45:37 1995 Fred Fish <fnf@cygnus.com>
-
- * Update all FSF addresses except those in COPYING* files.
-
-Wed Jul 5 16:15:54 1995 J.T. Conklin <jtc@rtl.cygnus.com>
-
- * Makefile.in (clean): Remove run, libsim.a.
-
- * Makefile.in, configure.in: converted to autoconf.
- * configure: New file, generated with autconf 2.4.
-
- * arm.mt: Removed.
-
-Fri Jun 30 16:49:47 1995 Stan Shebs <shebs@andros.cygnus.com>
-
- * wrapper.c (sim_do_command): New function.
-
-Tue Jun 13 10:57:32 1995 Steve Chamberlain <sac@slash.cygnus.com>
-
- * armos.c (ARMul_OSHandleSWI): New version to work with
- newlib simply.
-
-Thu Jun 8 14:37:14 1995 Steve Chamberlain <sac@slash.cygnus.com>
-
- * run.c (main): Grab return value from right register.
-
-Wed May 24 14:37:31 1995 Steve Chamberlain <sac@slash.cygnus.com>
-
- * New.
+++ /dev/null
-
-This directory contains the standard release of the ARMulator from
-Advanced RISC Machines, and was ftp'd from.
-
-ftp.cl.cam.ac.uk:/arm/gnu
-
-It likes to use TCP/IP between the simulator and the host, which is
-nice, but is a pain to use under anything non-unix.
-
-I've added created a new Makefile.in (the original in Makefile.orig)
-to build a version of the simulator without the TCP/IP stuff, and a
-wrapper.c to link directly into gdb and the run command.
-
-It should be possible (barring major changes in the layout of
-the armulator) to upgrade the simulator by copying all the files
-out of a release into this directory and renaming the Makefile.
-
-(Except that I changed armos.c to work more simply with our
-simulator rigs)
-
-Steve
-
-sac@cygnus.com
-
-Mon May 15 12:03:28 PDT 1995
-
-
+++ /dev/null
-/* Simulation code for the ARM processor.
- Copyright (C) 2009-2024 Free Software Foundation, Inc.
-
- This file is part of the GNU simulators.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-#ifndef ARM_SIM_H
-#define ARM_SIM_H
-
-#include "armdefs.h"
-
-extern struct ARMul_State *state;
-
-#endif
+++ /dev/null
-/* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
- Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* This must come before any other includes. */
-#include "defs.h"
-
-#include "armdefs.h"
-#include "armos.h"
-#include "armemu.h"
-#include "ansidecl.h"
-#include "iwmmxt.h"
-
-/* Dummy Co-processors. */
-
-static unsigned
-NoCoPro3R (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned a ATTRIBUTE_UNUSED,
- ARMword b ATTRIBUTE_UNUSED)
-{
- return ARMul_CANT;
-}
-
-static unsigned
-NoCoPro4R (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned a ATTRIBUTE_UNUSED,
- ARMword b ATTRIBUTE_UNUSED,
- ARMword c ATTRIBUTE_UNUSED)
-{
- return ARMul_CANT;
-}
-
-static unsigned
-NoCoPro4W (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned a ATTRIBUTE_UNUSED,
- ARMword b ATTRIBUTE_UNUSED,
- ARMword * c ATTRIBUTE_UNUSED)
-{
- return ARMul_CANT;
-}
-
-/* The XScale Co-processors. */
-
-/* Coprocessor 15: System Control. */
-static void write_cp14_reg (unsigned, ARMword);
-static ARMword read_cp14_reg (unsigned);
-
-/* There are two sets of registers for copro 15.
- One set is available when opcode_2 is 0 and
- the other set when opcode_2 >= 1. */
-static ARMword XScale_cp15_opcode_2_is_0_Regs[16];
-static ARMword XScale_cp15_opcode_2_is_not_0_Regs[16];
-/* There are also a set of breakpoint registers
- which are accessed via CRm instead of opcode_2. */
-static ARMword XScale_cp15_DBR1;
-static ARMword XScale_cp15_DBCON;
-static ARMword XScale_cp15_IBCR0;
-static ARMword XScale_cp15_IBCR1;
-
-static unsigned
-XScale_cp15_init (ARMul_State * state ATTRIBUTE_UNUSED)
-{
- int i;
-
- for (i = 16; i--;)
- {
- XScale_cp15_opcode_2_is_0_Regs[i] = 0;
- XScale_cp15_opcode_2_is_not_0_Regs[i] = 0;
- }
-
- /* Initialise the processor ID. */
- XScale_cp15_opcode_2_is_0_Regs[0] = 0x69052000;
-
- /* Initialise the cache type. */
- XScale_cp15_opcode_2_is_not_0_Regs[0] = 0x0B1AA1AA;
-
- /* Initialise the ARM Control Register. */
- XScale_cp15_opcode_2_is_0_Regs[1] = 0x00000078;
-
- return TRUE;
-}
-
-/* Check an access to a register. */
-
-static unsigned
-check_cp15_access (ARMul_State * state,
- unsigned reg,
- unsigned CRm,
- unsigned opcode_1,
- unsigned opcode_2)
-{
- /* Do not allow access to these register in USER mode. */
- if (state->Mode == USER26MODE || state->Mode == USER32MODE)
- return ARMul_CANT;
-
- /* Opcode_1should be zero. */
- if (opcode_1 != 0)
- return ARMul_CANT;
-
- /* Different register have different access requirements. */
- switch (reg)
- {
- case 0:
- case 1:
- /* CRm must be 0. Opcode_2 can be anything. */
- if (CRm != 0)
- return ARMul_CANT;
- break;
- case 2:
- case 3:
- /* CRm must be 0. Opcode_2 must be zero. */
- if ((CRm != 0) || (opcode_2 != 0))
- return ARMul_CANT;
- break;
- case 4:
- /* Access not allowed. */
- return ARMul_CANT;
- case 5:
- case 6:
- /* Opcode_2 must be zero. CRm must be 0. */
- if ((CRm != 0) || (opcode_2 != 0))
- return ARMul_CANT;
- break;
- case 7:
- /* Permissible combinations:
- Opcode_2 CRm
- 0 5
- 0 6
- 0 7
- 1 5
- 1 6
- 1 10
- 4 10
- 5 2
- 6 5 */
- switch (opcode_2)
- {
- default: return ARMul_CANT;
- case 6: if (CRm != 5) return ARMul_CANT; break;
- case 5: if (CRm != 2) return ARMul_CANT; break;
- case 4: if (CRm != 10) return ARMul_CANT; break;
- case 1: if ((CRm != 5) && (CRm != 6) && (CRm != 10)) return ARMul_CANT; break;
- case 0: if ((CRm < 5) || (CRm > 7)) return ARMul_CANT; break;
- }
- break;
-
- case 8:
- /* Permissible combinations:
- Opcode_2 CRm
- 0 5
- 0 6
- 0 7
- 1 5
- 1 6 */
- if (opcode_2 > 1)
- return ARMul_CANT;
- if ((CRm < 5) || (CRm > 7))
- return ARMul_CANT;
- if (opcode_2 == 1 && CRm == 7)
- return ARMul_CANT;
- break;
- case 9:
- /* Opcode_2 must be zero or one. CRm must be 1 or 2. */
- if ( ((CRm != 0) && (CRm != 1))
- || ((opcode_2 != 1) && (opcode_2 != 2)))
- return ARMul_CANT;
- break;
- case 10:
- /* Opcode_2 must be zero or one. CRm must be 4 or 8. */
- if ( ((CRm != 0) && (CRm != 1))
- || ((opcode_2 != 4) && (opcode_2 != 8)))
- return ARMul_CANT;
- break;
- case 11:
- /* Access not allowed. */
- return ARMul_CANT;
- case 12:
- /* Access not allowed. */
- return ARMul_CANT;
- case 13:
- /* Opcode_2 must be zero. CRm must be 0. */
- if ((CRm != 0) || (opcode_2 != 0))
- return ARMul_CANT;
- break;
- case 14:
- /* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */
- if (opcode_2 != 0)
- return ARMul_CANT;
-
- if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8) && (CRm != 9))
- return ARMul_CANT;
- break;
- case 15:
- /* Opcode_2 must be zero. CRm must be 1. */
- if ((CRm != 1) || (opcode_2 != 0))
- return ARMul_CANT;
- break;
- default:
- /* Should never happen. */
- return ARMul_CANT;
- }
-
- return ARMul_DONE;
-}
-
-/* Store a value into one of coprocessor 15's registers. */
-
-static void
-write_cp15_reg (ARMul_State * state,
- unsigned reg,
- unsigned opcode_2,
- unsigned CRm,
- ARMword value)
-{
- if (opcode_2)
- {
- switch (reg)
- {
- case 0: /* Cache Type. */
- /* Writes are not allowed. */
- return;
-
- case 1: /* Auxiliary Control. */
- /* Only BITS (5, 4) and BITS (1, 0) can be written. */
- value &= 0x33;
- break;
-
- default:
- return;
- }
-
- XScale_cp15_opcode_2_is_not_0_Regs [reg] = value;
- }
- else
- {
- switch (reg)
- {
- case 0: /* ID. */
- /* Writes are not allowed. */
- return;
-
- case 1: /* ARM Control. */
- /* Only BITS (13, 11), BITS (9, 7) and BITS (2, 0) can be written.
- BITS (31, 14) and BIT (10) write as zero, BITS (6, 3) write as one. */
- value &= 0x00003b87;
- value |= 0x00000078;
-
- /* Change the endianness if necessary. */
- if ((value & ARMul_CP15_R1_ENDIAN) !=
- (XScale_cp15_opcode_2_is_0_Regs [reg] & ARMul_CP15_R1_ENDIAN))
- {
- state->bigendSig = value & ARMul_CP15_R1_ENDIAN;
- /* Force ARMulator to notice these now. */
- state->Emulate = CHANGEMODE;
- }
- break;
-
- case 2: /* Translation Table Base. */
- /* Only BITS (31, 14) can be written. */
- value &= 0xffffc000;
- break;
-
- case 3: /* Domain Access Control. */
- /* All bits writable. */
- break;
-
- case 5: /* Fault Status Register. */
- /* BITS (10, 9) and BITS (7, 0) can be written. */
- value &= 0x000006ff;
- break;
-
- case 6: /* Fault Address Register. */
- /* All bits writable. */
- break;
-
- case 7: /* Cache Functions. */
- case 8: /* TLB Operations. */
- case 10: /* TLB Lock Down. */
- /* Ignore writes. */
- return;
-
- case 9: /* Data Cache Lock. */
- /* Only BIT (0) can be written. */
- value &= 0x1;
- break;
-
- case 13: /* Process ID. */
- /* Only BITS (31, 25) are writable. */
- value &= 0xfe000000;
- break;
-
- case 14: /* DBR0, DBR1, DBCON, IBCR0, IBCR1 */
- /* All bits can be written. Which register is accessed is
- dependent upon CRm. */
- switch (CRm)
- {
- case 0: /* DBR0 */
- break;
- case 3: /* DBR1 */
- XScale_cp15_DBR1 = value;
- break;
- case 4: /* DBCON */
- XScale_cp15_DBCON = value;
- break;
- case 8: /* IBCR0 */
- XScale_cp15_IBCR0 = value;
- break;
- case 9: /* IBCR1 */
- XScale_cp15_IBCR1 = value;
- break;
- default:
- return;
- }
- break;
-
- case 15: /* Coprpcessor Access Register. */
- /* Access is only valid if CRm == 1. */
- if (CRm != 1)
- return;
-
- /* Only BITS (13, 0) may be written. */
- value &= 0x00003fff;
- break;
-
- default:
- return;
- }
-
- XScale_cp15_opcode_2_is_0_Regs [reg] = value;
- }
-
- return;
-}
-
-/* Return the value in a cp15 register. */
-
-ARMword
-read_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm)
-{
- if (opcode_2 == 0)
- {
- if (reg == 15 && CRm != 1)
- return 0;
-
- if (reg == 14)
- {
- switch (CRm)
- {
- case 3: return XScale_cp15_DBR1;
- case 4: return XScale_cp15_DBCON;
- case 8: return XScale_cp15_IBCR0;
- case 9: return XScale_cp15_IBCR1;
- default:
- break;
- }
- }
-
- return XScale_cp15_opcode_2_is_0_Regs [reg];
- }
- else
- return XScale_cp15_opcode_2_is_not_0_Regs [reg];
-
- return 0;
-}
-
-static unsigned
-XScale_cp15_MRC (ARMul_State * state,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword * value)
-{
- unsigned opcode_2 = BITS (5, 7);
- unsigned CRm = BITS (0, 3);
- unsigned reg = BITS (16, 19);
- unsigned result;
-
- result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2);
-
- if (result == ARMul_DONE)
- * value = read_cp15_reg (reg, opcode_2, CRm);
-
- return result;
-}
-
-static unsigned
-XScale_cp15_MCR (ARMul_State * state,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword value)
-{
- unsigned opcode_2 = BITS (5, 7);
- unsigned CRm = BITS (0, 3);
- unsigned reg = BITS (16, 19);
- unsigned result;
-
- result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2);
-
- if (result == ARMul_DONE)
- write_cp15_reg (state, reg, opcode_2, CRm, value);
-
- return result;
-}
-
-static unsigned
-XScale_cp15_read_reg (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned reg,
- ARMword * value)
-{
- /* FIXME: Not sure what to do about the alternative register set
- here. For now default to just accessing CRm == 0 registers. */
- * value = read_cp15_reg (reg, 0, 0);
-
- return TRUE;
-}
-
-static unsigned
-XScale_cp15_write_reg (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned reg,
- ARMword value)
-{
- /* FIXME: Not sure what to do about the alternative register set
- here. For now default to just accessing CRm == 0 registers. */
- write_cp15_reg (state, reg, 0, 0, value);
-
- return TRUE;
-}
-
-/* Check for special XScale memory access features. */
-
-void
-XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
-{
- ARMword dbcon, r0, r1;
- int e1, e0;
-
- if (!state->is_XScale)
- return;
-
- /* Check for PID-ification.
- XXX BTB access support will require this test failing. */
- r0 = (read_cp15_reg (13, 0, 0) & 0xfe000000);
- if (r0 && (* address & 0xfe000000) == 0)
- * address |= r0;
-
- /* Check alignment fault enable/disable. */
- if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (* address & 3))
- {
- /* Set the FSR and FAR.
- Do not use XScale_set_fsr_far as this checks the DCSR register. */
- write_cp15_reg (state, 5, 0, 0, ARMul_CP15_R5_MMU_EXCPT);
- write_cp15_reg (state, 6, 0, 0, * address);
-
- ARMul_Abort (state, ARMul_DataAbortV);
- }
-
- if (XScale_debug_moe (state, -1))
- return;
-
- /* Check the data breakpoint registers. */
- dbcon = read_cp15_reg (14, 0, 4);
- r0 = read_cp15_reg (14, 0, 0);
- r1 = read_cp15_reg (14, 0, 3);
- e0 = dbcon & ARMul_CP15_DBCON_E0;
-
- if (dbcon & ARMul_CP15_DBCON_M)
- {
- /* r1 is a inverse mask. */
- if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
- && ((* address & ~r1) == (r0 & ~r1)))
- {
- XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
- ARMul_OSHandleSWI (state, SWI_Breakpoint);
- }
- }
- else
- {
- if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
- && ((* address & ~3) == (r0 & ~3)))
- {
- XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
- ARMul_OSHandleSWI (state, SWI_Breakpoint);
- }
-
- e1 = (dbcon & ARMul_CP15_DBCON_E1) >> 2;
- if (e1 != 0 && ((store && e1 != 3) || (!store && e1 != 1))
- && ((* address & ~3) == (r1 & ~3)))
- {
- XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
- ARMul_OSHandleSWI (state, SWI_Breakpoint);
- }
- }
-}
-
-/* Set the XScale FSR and FAR registers. */
-
-void
-XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far)
-{
- if (!state->is_XScale || (read_cp14_reg (10) & (1UL << 31)) == 0)
- return;
-
- write_cp15_reg (state, 5, 0, 0, fsr);
- write_cp15_reg (state, 6, 0, 0, far);
-}
-
-/* Set the XScale debug `method of entry' if it is enabled. */
-
-int
-XScale_debug_moe (ARMul_State * state, int moe)
-{
- ARMword value;
-
- if (!state->is_XScale)
- return 1;
-
- value = read_cp14_reg (10);
- if (value & (1UL << 31))
- {
- if (moe != -1)
- {
- value &= ~0x1c;
- value |= moe;
-
- write_cp14_reg (10, value);
- }
- return 1;
- }
- return 0;
-}
-
-/* Coprocessor 13: Interrupt Controller and Bus Controller. */
-
-/* There are two sets of registers for copro 13.
- One set (of three registers) is available when CRm is 0
- and the other set (of six registers) when CRm is 1. */
-
-static ARMword XScale_cp13_CR0_Regs[16];
-static ARMword XScale_cp13_CR1_Regs[16];
-
-static unsigned
-XScale_cp13_init (ARMul_State * state ATTRIBUTE_UNUSED)
-{
- int i;
-
- for (i = 16; i--;)
- {
- XScale_cp13_CR0_Regs[i] = 0;
- XScale_cp13_CR1_Regs[i] = 0;
- }
-
- return TRUE;
-}
-
-/* Check an access to a register. */
-
-static unsigned
-check_cp13_access (ARMul_State * state,
- unsigned reg,
- unsigned CRm,
- unsigned opcode_1,
- unsigned opcode_2)
-{
- /* Do not allow access to these registers in USER mode. */
- if (state->Mode == USER26MODE || state->Mode == USER32MODE)
- return ARMul_CANT;
-
- /* The opcodes should be zero. */
- if ((opcode_1 != 0) || (opcode_2 != 0))
- return ARMul_CANT;
-
- /* Do not allow access to these register if bit
- 13 of coprocessor 15's register 15 is zero. */
- if (! CP_ACCESS_ALLOWED (state, 13))
- return ARMul_CANT;
-
- /* Registers 0, 4 and 8 are defined when CRm == 0.
- Registers 0, 1, 4, 5, 6, 7, 8 are defined when CRm == 1.
- For all other CRm values undefined behaviour results. */
- if (CRm == 0)
- {
- if (reg == 0 || reg == 4 || reg == 8)
- return ARMul_DONE;
- }
- else if (CRm == 1)
- {
- if (reg == 0 || reg == 1 || (reg >= 4 && reg <= 8))
- return ARMul_DONE;
- }
-
- return ARMul_CANT;
-}
-
-/* Store a value into one of coprocessor 13's registers. */
-
-static void
-write_cp13_reg (unsigned reg, unsigned CRm, ARMword value)
-{
- switch (CRm)
- {
- case 0:
- switch (reg)
- {
- case 0: /* INTCTL */
- /* Only BITS (3:0) can be written. */
- value &= 0xf;
- break;
-
- case 4: /* INTSRC */
- /* No bits may be written. */
- return;
-
- case 8: /* INTSTR */
- /* Only BITS (1:0) can be written. */
- value &= 0x3;
- break;
-
- default:
- /* Should not happen. Ignore any writes to unimplemented registers. */
- return;
- }
-
- XScale_cp13_CR0_Regs [reg] = value;
- break;
-
- case 1:
- switch (reg)
- {
- case 0: /* BCUCTL */
- /* Only BITS (30:28) and BITS (3:0) can be written.
- BIT(31) is write ignored. */
- value &= 0x7000000f;
- value |= XScale_cp13_CR1_Regs[0] & (1UL << 31);
- break;
-
- case 1: /* BCUMOD */
- /* Only bit 0 is accecssible. */
- value &= 1;
- value |= XScale_cp13_CR1_Regs[1] & ~ 1;
- break;
-
- case 4: /* ELOG0 */
- case 5: /* ELOG1 */
- case 6: /* ECAR0 */
- case 7: /* ECAR1 */
- /* No bits can be written. */
- return;
-
- case 8: /* ECTST */
- /* Only BITS (7:0) can be written. */
- value &= 0xff;
- break;
-
- default:
- /* Should not happen. Ignore any writes to unimplemented registers. */
- return;
- }
-
- XScale_cp13_CR1_Regs [reg] = value;
- break;
-
- default:
- /* Should not happen. */
- break;
- }
-
- return;
-}
-
-/* Return the value in a cp13 register. */
-
-static ARMword
-read_cp13_reg (unsigned reg, unsigned CRm)
-{
- if (CRm == 0)
- return XScale_cp13_CR0_Regs [reg];
- else if (CRm == 1)
- return XScale_cp13_CR1_Regs [reg];
-
- return 0;
-}
-
-static unsigned
-XScale_cp13_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
-{
- unsigned reg = BITS (12, 15);
- unsigned result;
-
- result = check_cp13_access (state, reg, 0, 0, 0);
-
- if (result == ARMul_DONE && type == ARMul_DATA)
- write_cp13_reg (reg, 0, data);
-
- return result;
-}
-
-static unsigned
-XScale_cp13_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
-{
- unsigned reg = BITS (12, 15);
- unsigned result;
-
- result = check_cp13_access (state, reg, 0, 0, 0);
-
- if (result == ARMul_DONE && type == ARMul_DATA)
- * data = read_cp13_reg (reg, 0);
-
- return result;
-}
-
-static unsigned
-XScale_cp13_MRC (ARMul_State * state,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword * value)
-{
- unsigned CRm = BITS (0, 3);
- unsigned reg = BITS (16, 19);
- unsigned result;
-
- result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7));
-
- if (result == ARMul_DONE)
- * value = read_cp13_reg (reg, CRm);
-
- return result;
-}
-
-static unsigned
-XScale_cp13_MCR (ARMul_State * state,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword value)
-{
- unsigned CRm = BITS (0, 3);
- unsigned reg = BITS (16, 19);
- unsigned result;
-
- result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7));
-
- if (result == ARMul_DONE)
- write_cp13_reg (reg, CRm, value);
-
- return result;
-}
-
-static unsigned
-XScale_cp13_read_reg (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned reg,
- ARMword * value)
-{
- /* FIXME: Not sure what to do about the alternative register set
- here. For now default to just accessing CRm == 0 registers. */
- * value = read_cp13_reg (reg, 0);
-
- return TRUE;
-}
-
-static unsigned
-XScale_cp13_write_reg (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned reg,
- ARMword value)
-{
- /* FIXME: Not sure what to do about the alternative register set
- here. For now default to just accessing CRm == 0 registers. */
- write_cp13_reg (reg, 0, value);
-
- return TRUE;
-}
-
-/* Coprocessor 14: Performance Monitoring, Clock and Power management,
- Software Debug. */
-
-static ARMword XScale_cp14_Regs[16];
-
-static unsigned
-XScale_cp14_init (ARMul_State * state ATTRIBUTE_UNUSED)
-{
- int i;
-
- for (i = 16; i--;)
- XScale_cp14_Regs[i] = 0;
-
- return TRUE;
-}
-
-/* Check an access to a register. */
-
-static unsigned
-check_cp14_access (ARMul_State * state,
- unsigned reg,
- unsigned CRm,
- unsigned opcode1,
- unsigned opcode2)
-{
- /* Not allowed to access these register in USER mode. */
- if (state->Mode == USER26MODE || state->Mode == USER32MODE)
- return ARMul_CANT;
-
- /* CRm should be zero. */
- if (CRm != 0)
- return ARMul_CANT;
-
- /* OPcodes should be zero. */
- if (opcode1 != 0 || opcode2 != 0)
- return ARMul_CANT;
-
- /* Accessing registers 4 or 5 has unpredicatable results. */
- if (reg >= 4 && reg <= 5)
- return ARMul_CANT;
-
- return ARMul_DONE;
-}
-
-/* Store a value into one of coprocessor 14's registers. */
-
-static void
-write_cp14_reg (unsigned reg, ARMword value)
-{
- switch (reg)
- {
- case 0: /* PMNC */
- /* Only BITS (27:12), BITS (10:8) and BITS (6:0) can be written. */
- value &= 0x0ffff77f;
-
- /* Reset the clock counter if necessary. */
- if (value & ARMul_CP14_R0_CLKRST)
- XScale_cp14_Regs [1] = 0;
- break;
-
- case 4:
- case 5:
- /* We should not normally reach this code. The debugger interface
- can bypass the normal checks though, so it could happen. */
- value = 0;
- break;
-
- case 6: /* CCLKCFG */
- /* Only BITS (3:0) can be written. */
- value &= 0xf;
- break;
-
- case 7: /* PWRMODE */
- /* Although BITS (1:0) can be written with non-zero values, this would
- have the side effect of putting the processor to sleep. Thus in
- order for the register to be read again, it would have to go into
- ACTIVE mode, which means that any read will see these bits as zero.
-
- Rather than trying to implement complex reset-to-zero-upon-read logic
- we just override the write value with zero. */
- value = 0;
- break;
-
- case 10: /* DCSR */
- /* Only BITS (31:30), BITS (23:22), BITS (20:16) and BITS (5:0) can
- be written. */
- value &= 0xc0df003f;
- break;
-
- case 11: /* TBREG */
- /* No writes are permitted. */
- value = 0;
- break;
-
- case 14: /* TXRXCTRL */
- /* Only BITS (31:30) can be written. */
- value &= 0xc0000000;
- break;
-
- default:
- /* All bits can be written. */
- break;
- }
-
- XScale_cp14_Regs [reg] = value;
-}
-
-/* Return the value in a cp14 register. Not a static function since
- it is used by the code to emulate the BKPT instruction in armemu.c. */
-
-ARMword
-read_cp14_reg (unsigned reg)
-{
- return XScale_cp14_Regs [reg];
-}
-
-static unsigned
-XScale_cp14_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
-{
- unsigned reg = BITS (12, 15);
- unsigned result;
-
- result = check_cp14_access (state, reg, 0, 0, 0);
-
- if (result == ARMul_DONE && type == ARMul_DATA)
- write_cp14_reg (reg, data);
-
- return result;
-}
-
-static unsigned
-XScale_cp14_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
-{
- unsigned reg = BITS (12, 15);
- unsigned result;
-
- result = check_cp14_access (state, reg, 0, 0, 0);
-
- if (result == ARMul_DONE && type == ARMul_DATA)
- * data = read_cp14_reg (reg);
-
- return result;
-}
-
-static unsigned
-XScale_cp14_MRC
-(
- ARMul_State * state,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword * value
-)
-{
- unsigned reg = BITS (16, 19);
- unsigned result;
-
- result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7));
-
- if (result == ARMul_DONE)
- * value = read_cp14_reg (reg);
-
- return result;
-}
-
-static unsigned
-XScale_cp14_MCR
-(
- ARMul_State * state,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword value
-)
-{
- unsigned reg = BITS (16, 19);
- unsigned result;
-
- result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7));
-
- if (result == ARMul_DONE)
- write_cp14_reg (reg, value);
-
- return result;
-}
-
-static unsigned
-XScale_cp14_read_reg
-(
- ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned reg,
- ARMword * value
-)
-{
- * value = read_cp14_reg (reg);
-
- return TRUE;
-}
-
-static unsigned
-XScale_cp14_write_reg
-(
- ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned reg,
- ARMword value
-)
-{
- write_cp14_reg (reg, value);
-
- return TRUE;
-}
-
-/* Here's ARMulator's MMU definition. A few things to note:
- 1) It has eight registers, but only two are defined.
- 2) You can only access its registers with MCR and MRC.
- 3) MMU Register 0 (ID) returns 0x41440110
- 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4
- controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
- bit 6 controls late abort timimg and bit 7 controls big/little endian. */
-
-static ARMword MMUReg[8];
-
-static unsigned
-MMUInit (ARMul_State * state)
-{
- MMUReg[1] = state->prog32Sig << 4 |
- state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
-
- ARMul_ConsolePrint (state, ", MMU present");
-
- return TRUE;
-}
-
-static unsigned
-MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword * value)
-{
- int reg = BITS (16, 19) & 7;
-
- if (reg == 0)
- *value = 0x41440110;
- else
- *value = MMUReg[reg];
-
- return ARMul_DONE;
-}
-
-static unsigned
-MMUMCR (ARMul_State * state,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword value)
-{
- int reg = BITS (16, 19) & 7;
-
- MMUReg[reg] = value;
-
- if (reg == 1)
- {
- ARMword p,d,l,b;
-
- p = state->prog32Sig;
- d = state->data32Sig;
- l = state->lateabtSig;
- b = state->bigendSig;
-
- state->prog32Sig = value >> 4 & 1;
- state->data32Sig = value >> 5 & 1;
- state->lateabtSig = value >> 6 & 1;
- state->bigendSig = value >> 7 & 1;
-
- if ( p != state->prog32Sig
- || d != state->data32Sig
- || l != state->lateabtSig
- || b != state->bigendSig)
- /* Force ARMulator to notice these now. */
- state->Emulate = CHANGEMODE;
- }
-
- return ARMul_DONE;
-}
-
-static unsigned
-MMURead (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value)
-{
- if (reg == 0)
- *value = 0x41440110;
- else if (reg < 8)
- *value = MMUReg[reg];
-
- return TRUE;
-}
-
-static unsigned
-MMUWrite (ARMul_State * state, unsigned reg, ARMword value)
-{
- if (reg < 8)
- MMUReg[reg] = value;
-
- if (reg == 1)
- {
- ARMword p,d,l,b;
-
- p = state->prog32Sig;
- d = state->data32Sig;
- l = state->lateabtSig;
- b = state->bigendSig;
-
- state->prog32Sig = value >> 4 & 1;
- state->data32Sig = value >> 5 & 1;
- state->lateabtSig = value >> 6 & 1;
- state->bigendSig = value >> 7 & 1;
-
- if ( p != state->prog32Sig
- || d != state->data32Sig
- || l != state->lateabtSig
- || b != state->bigendSig)
- /* Force ARMulator to notice these now. */
- state->Emulate = CHANGEMODE;
- }
-
- return TRUE;
-}
-
-
-/* What follows is the Validation Suite Coprocessor. It uses two
- co-processor numbers (4 and 5) and has the follwing functionality.
- Sixteen registers. Both co-processor nuimbers can be used in an MCR
- and MRC to access these registers. CP 4 can LDC and STC to and from
- the registers. CP 4 and CP 5 CDP 0 will busy wait for the number of
- cycles specified by a CP register. CP 5 CDP 1 issues a FIQ after a
- number of cycles (specified in a CP register), CDP 2 issues an IRQW
- in the same way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5
- stores a 32 bit time value in a CP register (actually it's the total
- number of N, S, I, C and F cyles). */
-
-static ARMword ValReg[16];
-
-static unsigned
-ValLDC (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type,
- ARMword instr,
- ARMword data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA)
- words = 0;
- else
- {
- ValReg[BITS (12, 15)] = data;
-
- if (BIT (22))
- /* It's a long access, get two words. */
- if (words++ != 4)
- return ARMul_INC;
- }
-
- return ARMul_DONE;
-}
-
-static unsigned
-ValSTC (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type,
- ARMword instr,
- ARMword * data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA)
- words = 0;
- else
- {
- * data = ValReg[BITS (12, 15)];
-
- if (BIT (22))
- /* It's a long access, get two words. */
- if (words++ != 4)
- return ARMul_INC;
- }
-
- return ARMul_DONE;
-}
-
-static unsigned
-ValMRC (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword * value)
-{
- *value = ValReg[BITS (16, 19)];
-
- return ARMul_DONE;
-}
-
-static unsigned
-ValMCR (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword value)
-{
- ValReg[BITS (16, 19)] = value;
-
- return ARMul_DONE;
-}
-
-static unsigned
-ValCDP (ARMul_State * state, unsigned type, ARMword instr)
-{
- static unsigned long finish = 0;
-
- if (BITS (20, 23) != 0)
- return ARMul_CANT;
-
- if (type == ARMul_FIRST)
- {
- ARMword howlong;
-
- howlong = ValReg[BITS (0, 3)];
-
- /* First cycle of a busy wait. */
- finish = ARMul_Time (state) + howlong;
-
- return howlong == 0 ? ARMul_DONE : ARMul_BUSY;
- }
- else if (type == ARMul_BUSY)
- {
- if (ARMul_Time (state) >= finish)
- return ARMul_DONE;
- else
- return ARMul_BUSY;
- }
-
- return ARMul_CANT;
-}
-
-static unsigned
-DoAFIQ (ARMul_State * state)
-{
- state->NfiqSig = LOW;
- state->Exception++;
- return 0;
-}
-
-static unsigned
-DoAIRQ (ARMul_State * state)
-{
- state->NirqSig = LOW;
- state->Exception++;
- return 0;
-}
-
-static unsigned
-IntCDP (ARMul_State * state, unsigned type, ARMword instr)
-{
- static unsigned long finish;
- ARMword howlong;
-
- howlong = ValReg[BITS (0, 3)];
-
- switch ((int) BITS (20, 23))
- {
- case 0:
- if (type == ARMul_FIRST)
- {
- /* First cycle of a busy wait. */
- finish = ARMul_Time (state) + howlong;
-
- return howlong == 0 ? ARMul_DONE : ARMul_BUSY;
- }
- else if (type == ARMul_BUSY)
- {
- if (ARMul_Time (state) >= finish)
- return ARMul_DONE;
- else
- return ARMul_BUSY;
- }
- return ARMul_DONE;
-
- case 1:
- if (howlong == 0)
- ARMul_Abort (state, ARMul_FIQV);
- else
- ARMul_ScheduleEvent (state, howlong, DoAFIQ);
- return ARMul_DONE;
-
- case 2:
- if (howlong == 0)
- ARMul_Abort (state, ARMul_IRQV);
- else
- ARMul_ScheduleEvent (state, howlong, DoAIRQ);
- return ARMul_DONE;
-
- case 3:
- state->NfiqSig = HIGH;
- state->Exception--;
- return ARMul_DONE;
-
- case 4:
- state->NirqSig = HIGH;
- state->Exception--;
- return ARMul_DONE;
-
- case 5:
- ValReg[BITS (0, 3)] = ARMul_Time (state);
- return ARMul_DONE;
- }
-
- return ARMul_CANT;
-}
-
-/* Install co-processor instruction handlers in this routine. */
-
-unsigned
-ARMul_CoProInit (ARMul_State * state)
-{
- unsigned int i;
-
- /* Initialise tham all first. */
- for (i = 0; i < 16; i++)
- ARMul_CoProDetach (state, i);
-
- /* Install CoPro Instruction handlers here.
- The format is:
- ARMul_CoProAttach (state, CP Number, Init routine, Exit routine
- LDC routine, STC routine, MRC routine, MCR routine,
- CDP routine, Read Reg routine, Write Reg routine). */
- if (state->is_ep9312)
- {
- ARMul_CoProAttach (state, 4, NULL, NULL, DSPLDC4, DSPSTC4,
- DSPMRC4, DSPMCR4, DSPCDP4, NULL, NULL);
- ARMul_CoProAttach (state, 5, NULL, NULL, DSPLDC5, DSPSTC5,
- DSPMRC5, DSPMCR5, DSPCDP5, NULL, NULL);
- ARMul_CoProAttach (state, 6, NULL, NULL, NULL, NULL,
- DSPMRC6, DSPMCR6, DSPCDP6, NULL, NULL);
- }
- else
- {
- ARMul_CoProAttach (state, 4, NULL, NULL, ValLDC, ValSTC,
- ValMRC, ValMCR, ValCDP, NULL, NULL);
-
- ARMul_CoProAttach (state, 5, NULL, NULL, NULL, NULL,
- ValMRC, ValMCR, IntCDP, NULL, NULL);
- }
-
- if (state->is_XScale)
- {
- ARMul_CoProAttach (state, 13, XScale_cp13_init, NULL,
- XScale_cp13_LDC, XScale_cp13_STC, XScale_cp13_MRC,
- XScale_cp13_MCR, NULL, XScale_cp13_read_reg,
- XScale_cp13_write_reg);
-
- ARMul_CoProAttach (state, 14, XScale_cp14_init, NULL,
- XScale_cp14_LDC, XScale_cp14_STC, XScale_cp14_MRC,
- XScale_cp14_MCR, NULL, XScale_cp14_read_reg,
- XScale_cp14_write_reg);
-
- ARMul_CoProAttach (state, 15, XScale_cp15_init, NULL,
- NULL, NULL, XScale_cp15_MRC, XScale_cp15_MCR,
- NULL, XScale_cp15_read_reg, XScale_cp15_write_reg);
- }
- else
- {
- ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL,
- MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
- }
-
- if (state->is_iWMMXt)
- {
- ARMul_CoProAttach (state, 0, NULL, NULL, IwmmxtLDC, IwmmxtSTC,
- NULL, NULL, IwmmxtCDP, NULL, NULL);
-
- ARMul_CoProAttach (state, 1, NULL, NULL, NULL, NULL,
- IwmmxtMRC, IwmmxtMCR, IwmmxtCDP, NULL, NULL);
- }
-
- /* No handlers below here. */
-
- /* Call all the initialisation routines. */
- for (i = 0; i < 16; i++)
- if (state->CPInit[i])
- (state->CPInit[i]) (state);
-
- return TRUE;
-}
-
-/* Install co-processor finalisation routines in this routine. */
-
-void
-ARMul_CoProExit (ARMul_State * state)
-{
- register unsigned i;
-
- for (i = 0; i < 16; i++)
- if (state->CPExit[i])
- (state->CPExit[i]) (state);
-
- for (i = 0; i < 16; i++) /* Detach all handlers. */
- ARMul_CoProDetach (state, i);
-}
-
-/* Routines to hook Co-processors into ARMulator. */
-
-void
-ARMul_CoProAttach (ARMul_State * state,
- unsigned number,
- ARMul_CPInits * init,
- ARMul_CPExits * exit,
- ARMul_LDCs * ldc,
- ARMul_STCs * stc,
- ARMul_MRCs * mrc,
- ARMul_MCRs * mcr,
- ARMul_CDPs * cdp,
- ARMul_CPReads * read,
- ARMul_CPWrites * write)
-{
- if (init != NULL)
- state->CPInit[number] = init;
- if (exit != NULL)
- state->CPExit[number] = exit;
- if (ldc != NULL)
- state->LDC[number] = ldc;
- if (stc != NULL)
- state->STC[number] = stc;
- if (mrc != NULL)
- state->MRC[number] = mrc;
- if (mcr != NULL)
- state->MCR[number] = mcr;
- if (cdp != NULL)
- state->CDP[number] = cdp;
- if (read != NULL)
- state->CPRead[number] = read;
- if (write != NULL)
- state->CPWrite[number] = write;
-}
-
-void
-ARMul_CoProDetach (ARMul_State * state, unsigned number)
-{
- ARMul_CoProAttach (state, number, NULL, NULL,
- NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
- NoCoPro3R, NULL, NULL);
-
- state->CPInit[number] = NULL;
- state->CPExit[number] = NULL;
- state->CPRead[number] = NULL;
- state->CPWrite[number] = NULL;
-}
+++ /dev/null
-/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-#ifndef ARMDEFS_H
-#define ARMDEFS_H
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <ansidecl.h>
-
-#define FALSE 0
-#define TRUE 1
-#define LOW 0
-#define HIGH 1
-#define LOWHIGH 1
-#define HIGHLOW 2
-
-typedef uint32_t ARMword;
-typedef int32_t ARMsword;
-typedef uint64_t ARMdword;
-typedef int64_t ARMsdword;
-typedef struct ARMul_State ARMul_State;
-
-typedef unsigned ARMul_CPInits (ARMul_State * state);
-typedef unsigned ARMul_CPExits (ARMul_State * state);
-typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
- ARMword instr, ARMword value);
-typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
- ARMword instr, ARMword * value);
-typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
- ARMword instr, ARMword * value);
-typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
- ARMword instr, ARMword value);
-typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
- ARMword instr);
-typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
- ARMword * value);
-typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
- ARMword value);
-
-typedef double ARMdval; /* FIXME: Must be a 64-bit floating point type. */
-typedef float ARMfval; /* FIXME: Must be a 32-bit floating point type. */
-
-typedef union
-{
- ARMword uword[2];
- ARMsword sword[2];
- ARMfval fval[2];
- ARMdword dword;
- ARMdval dval;
-} ARM_VFP_reg;
-
-#define VFP_fval(N) (state->VFP_Reg[(N)>> 1].fval[(N) & 1])
-#define VFP_uword(N) (state->VFP_Reg[(N)>> 1].uword[(N) & 1])
-#define VFP_sword(N) (state->VFP_Reg[(N)>> 1].sword[(N) & 1])
-
-#define VFP_dval(N) (state->VFP_Reg[(N)].dval)
-#define VFP_dword(N) (state->VFP_Reg[(N)].dword)
-
-struct ARMul_State
-{
- ARMword Emulate; /* to start and stop emulation */
- unsigned EndCondition; /* reason for stopping */
- ARMword Reg[16]; /* the current register file */
- ARMword RegBank[7][16]; /* all the registers */
- /* 40 bit accumulator. We always keep this 64 bits wide,
- and move only 40 bits out of it in an MRA insn. */
- ARMdword Accumulator;
- ARMword Cpsr; /* the current psr */
- ARMword Spsr[7]; /* the exception psr's */
- ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
- ARMword SFlag;
-#ifdef MODET
- ARMword TFlag; /* Thumb state */
-#endif
- ARMword Bank; /* the current register bank */
- ARMword Mode; /* the current mode */
- ARMword instr, pc, temp; /* saved register state */
- ARMword loaded, decoded; /* saved pipeline state */
- unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
- unsigned long NumInstrs; /* the number of instructions executed */
- unsigned NextInstr;
- unsigned VectorCatch; /* caught exception mask */
- unsigned CallDebug; /* set to call the debugger */
- unsigned CanWatch; /* set by memory interface if its willing to suffer the
- overhead of checking for watchpoints on each memory
- access */
- unsigned MemReadDebug, MemWriteDebug;
- unsigned long StopHandle;
-
- unsigned char *MemDataPtr; /* admin data */
- unsigned char *MemInPtr; /* the Data In bus */
- unsigned char *MemOutPtr; /* the Data Out bus (which you may not need */
- unsigned char *MemSparePtr; /* extra space */
- ARMword MemSize;
-
- unsigned char *OSptr; /* OS Handle */
- char *CommandLine; /* Command Line from ARMsd */
-
- ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
- ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
- ARMul_LDCs *LDC[16]; /* LDC instruction */
- ARMul_STCs *STC[16]; /* STC instruction */
- ARMul_MRCs *MRC[16]; /* MRC instruction */
- ARMul_MCRs *MCR[16]; /* MCR instruction */
- ARMul_CDPs *CDP[16]; /* CDP instruction */
- ARMul_CPReads *CPRead[16]; /* Read CP register */
- ARMul_CPWrites *CPWrite[16]; /* Write CP register */
- unsigned char *CPData[16]; /* Coprocessor data */
- unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
- unsigned long LastTime; /* Value of last call to ARMul_Time() */
- ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit
- 3 set */
-
- unsigned EventSet; /* the number of events in the queue */
- unsigned long Now; /* time to the nearest cycle */
- struct EventNode **EventPtr; /* the event list */
-
- unsigned Exception; /* enable the next four values */
- unsigned Debug; /* show instructions as they are executed */
- unsigned NresetSig; /* reset the processor */
- unsigned NfiqSig;
- unsigned NirqSig;
-
- unsigned abortSig;
- unsigned NtransSig;
- unsigned bigendSig;
- unsigned prog32Sig;
- unsigned data32Sig;
- unsigned lateabtSig;
- ARMword Vector; /* synthesize aborts in cycle modes */
- ARMword Aborted; /* sticky flag for aborts */
- ARMword Reseted; /* sticky flag for Reset */
- ARMword Inted, LastInted; /* sticky flags for interrupts */
- ARMword Base; /* extra hand for base writeback */
- ARMword AbortAddr; /* to keep track of Prefetch aborts */
-
- const struct Dbg_HostosInterface *hostif;
-
- unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
- unsigned is_v5; /* Are we emulating a v5 architecture ? */
- unsigned is_v5e; /* Are we emulating a v5e architecture ? */
- unsigned is_v6; /* Are we emulating a v6 architecture ? */
- unsigned is_XScale; /* Are we emulating an XScale architecture ? */
- unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
- unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
- unsigned verbose; /* Print various messages like the banner */
-
- ARM_VFP_reg VFP_Reg[32]; /* Advanced SIMD registers. */
- ARMword FPSCR; /* Floating Point Status Register. */
-};
-
-/***************************************************************************\
-* Properties of ARM we know about *
-\***************************************************************************/
-
-/* The bitflags */
-#define ARM_Fix26_Prop 0x01
-#define ARM_Nexec_Prop 0x02
-#define ARM_Debug_Prop 0x10
-#define ARM_Isync_Prop ARM_Debug_Prop
-#define ARM_Lock_Prop 0x20
-#define ARM_v4_Prop 0x40
-#define ARM_v5_Prop 0x80
-#define ARM_v5e_Prop 0x100
-#define ARM_XScale_Prop 0x200
-#define ARM_ep9312_Prop 0x400
-#define ARM_iWMMXt_Prop 0x800
-#define ARM_v6_Prop 0x1000
-
-/***************************************************************************\
-* Macros to extract instruction fields *
-\***************************************************************************/
-
-#undef BIT /* common/sim-bits.h conflict :( */
-#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
-#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
-#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
-
-/***************************************************************************\
-* The hardware vector addresses *
-\***************************************************************************/
-
-#define ARMResetV 0L
-#define ARMUndefinedInstrV 4L
-#define ARMSWIV 8L
-#define ARMPrefetchAbortV 12L
-#define ARMDataAbortV 16L
-#define ARMAddrExceptnV 20L
-#define ARMIRQV 24L
-#define ARMFIQV 28L
-#define ARMErrorV 32L /* This is an offset, not an address ! */
-
-#define ARMul_ResetV ARMResetV
-#define ARMul_UndefinedInstrV ARMUndefinedInstrV
-#define ARMul_SWIV ARMSWIV
-#define ARMul_PrefetchAbortV ARMPrefetchAbortV
-#define ARMul_DataAbortV ARMDataAbortV
-#define ARMul_AddrExceptnV ARMAddrExceptnV
-#define ARMul_IRQV ARMIRQV
-#define ARMul_FIQV ARMFIQV
-
-/***************************************************************************\
-* Mode and Bank Constants *
-\***************************************************************************/
-
-#define USER26MODE 0L
-#define FIQ26MODE 1L
-#define IRQ26MODE 2L
-#define SVC26MODE 3L
-#define USER32MODE 16L
-#define FIQ32MODE 17L
-#define IRQ32MODE 18L
-#define SVC32MODE 19L
-#define ABORT32MODE 23L
-#define UNDEF32MODE 27L
-#define SYSTEMMODE 31L
-
-#define ARM32BITMODE (state->Mode > 3)
-#define ARM26BITMODE (state->Mode <= 3)
-#define ARMMODE (state->Mode)
-#define ARMul_MODEBITS 0x1fL
-#define ARMul_MODE32BIT ARM32BITMODE
-#define ARMul_MODE26BIT ARM26BITMODE
-
-#define USERBANK 0
-#define FIQBANK 1
-#define IRQBANK 2
-#define SVCBANK 3
-#define ABORTBANK 4
-#define UNDEFBANK 5
-#define DUMMYBANK 6
-#define SYSTEMBANK USERBANK
-
-#define BANK_CAN_ACCESS_SPSR(bank) \
- ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
-
-/***************************************************************************\
-* Definitons of things in the emulator *
-\***************************************************************************/
-
-extern void ARMul_EmulateInit (void);
-extern ARMul_State *ARMul_NewState (void);
-extern void ARMul_Reset (ARMul_State * state);
-extern ARMword ARMul_DoProg (ARMul_State * state);
-extern ARMword ARMul_DoInstr (ARMul_State * state);
-
-/***************************************************************************\
-* Definitons of things for event handling *
-\***************************************************************************/
-
-extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
- unsigned (*func) ());
-extern void ARMul_EnvokeEvent (ARMul_State * state);
-extern unsigned long ARMul_Time (ARMul_State * state);
-
-/***************************************************************************\
-* Useful support routines *
-\***************************************************************************/
-
-extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
- unsigned reg);
-extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
- ARMword value);
-extern ARMword ARMul_GetPC (ARMul_State * state);
-extern ARMword ARMul_GetNextPC (ARMul_State * state);
-extern void ARMul_SetPC (ARMul_State * state, ARMword value);
-extern ARMword ARMul_GetR15 (ARMul_State * state);
-extern void ARMul_SetR15 (ARMul_State * state, ARMword value);
-
-extern ARMword ARMul_GetCPSR (ARMul_State * state);
-extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
-extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
-extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
-
-/***************************************************************************\
-* Definitons of things to handle aborts *
-\***************************************************************************/
-
-extern void ARMul_Abort (ARMul_State * state, ARMword address);
-#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
-#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
- state->AbortAddr = (address & ~3L)
-#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
- state->Aborted = ARMul_DataAbortV ;
-#define ARMul_CLEARABORT state->abortSig = LOW
-
-/***************************************************************************\
-* Definitons of things in the memory interface *
-\***************************************************************************/
-
-extern unsigned ARMul_MemoryInit (ARMul_State * state,
- unsigned long initmemsize);
-extern void ARMul_MemoryExit (ARMul_State * state);
-
-extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
- ARMword isize);
-extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
- ARMword isize);
-extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
- ARMword isize);
-
-extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
-extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
-extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
-extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
-
-extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
- ARMword data);
-extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
- ARMword data);
-extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
- ARMword data);
-extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
- ARMword data);
-
-extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
- ARMword data);
-extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
- ARMword data);
-
-extern void ARMul_Icycles (ARMul_State * state, unsigned number,
- ARMword address);
-extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
- ARMword address);
-
-extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
-extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
-extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address);
-extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
- ARMword data);
-extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
- ARMword data);
-extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address,
- ARMword data);
-
-extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
- ARMword, ARMword, ARMword, ARMword, ARMword,
- ARMword, ARMword, ARMword);
-
-/***************************************************************************\
-* Definitons of things in the co-processor interface *
-\***************************************************************************/
-
-#define ARMul_FIRST 0
-#define ARMul_TRANSFER 1
-#define ARMul_BUSY 2
-#define ARMul_DATA 3
-#define ARMul_INTERRUPT 4
-#define ARMul_DONE 0
-#define ARMul_CANT 1
-#define ARMul_INC 3
-
-#define ARMul_CP13_R0_FIQ 0x1
-#define ARMul_CP13_R0_IRQ 0x2
-#define ARMul_CP13_R8_PMUS 0x1
-
-#define ARMul_CP14_R0_ENABLE 0x0001
-#define ARMul_CP14_R0_CLKRST 0x0004
-#define ARMul_CP14_R0_CCD 0x0008
-#define ARMul_CP14_R0_INTEN0 0x0010
-#define ARMul_CP14_R0_INTEN1 0x0020
-#define ARMul_CP14_R0_INTEN2 0x0040
-#define ARMul_CP14_R0_FLAG0 0x0100
-#define ARMul_CP14_R0_FLAG1 0x0200
-#define ARMul_CP14_R0_FLAG2 0x0400
-#define ARMul_CP14_R10_MOE_IB 0x0004
-#define ARMul_CP14_R10_MOE_DB 0x0008
-#define ARMul_CP14_R10_MOE_BT 0x000c
-#define ARMul_CP15_R1_ENDIAN 0x0080
-#define ARMul_CP15_R1_ALIGN 0x0002
-#define ARMul_CP15_R5_X 0x0400
-#define ARMul_CP15_R5_ST_ALIGN 0x0001
-#define ARMul_CP15_R5_IMPRE 0x0406
-#define ARMul_CP15_R5_MMU_EXCPT 0x0400
-#define ARMul_CP15_DBCON_M 0x0100
-#define ARMul_CP15_DBCON_E1 0x000c
-#define ARMul_CP15_DBCON_E0 0x0003
-
-extern unsigned ARMul_CoProInit (ARMul_State * state);
-extern void ARMul_CoProExit (ARMul_State * state);
-extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
- ARMul_CPInits * init, ARMul_CPExits * exit,
- ARMul_LDCs * ldc, ARMul_STCs * stc,
- ARMul_MRCs * mrc, ARMul_MCRs * mcr,
- ARMul_CDPs * cdp,
- ARMul_CPReads * read, ARMul_CPWrites * write);
-extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
-extern void XScale_check_memacc (ARMul_State * state, ARMword * address,
- int store);
-extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far);
-extern int XScale_debug_moe (ARMul_State * state, int moe);
-
-/***************************************************************************\
-* Definitons of things in the host environment *
-\***************************************************************************/
-
-extern unsigned ARMul_OSInit (ARMul_State * state);
-extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
-
-/***************************************************************************\
-* Host-dependent stuff *
-\***************************************************************************/
-
-extern void ARMul_UndefInstr (ARMul_State *, ARMword);
-extern void ARMul_FixCPSR (ARMul_State *, ARMword, ARMword);
-extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword);
-extern void ARMul_ConsolePrint (ARMul_State *, const char *, ...)
- ATTRIBUTE_PRINTF (2, 3);
-extern void ARMul_SelectProcessor (ARMul_State *, unsigned);
-
-#endif
+++ /dev/null
-/* armemu.c -- Main instruction emulation: ARM7 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
- Modifications to add arch. v4 support by <jsmith@cygnus.com>.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* This must come before any other includes. */
-#include "defs.h"
-
-#include "armdefs.h"
-#include "armemu.h"
-#include "armos.h"
-#include "iwmmxt.h"
-
-static ARMword GetDPRegRHS (ARMul_State *, ARMword);
-static ARMword GetDPSRegRHS (ARMul_State *, ARMword);
-static void WriteR15 (ARMul_State *, ARMword);
-static void WriteSR15 (ARMul_State *, ARMword);
-static void WriteR15Branch (ARMul_State *, ARMword);
-static void WriteR15Load (ARMul_State *, ARMword);
-static ARMword GetLSRegRHS (ARMul_State *, ARMword);
-static ARMword GetLS7RHS (ARMul_State *, ARMword);
-static unsigned LoadWord (ARMul_State *, ARMword, ARMword);
-static unsigned LoadHalfWord (ARMul_State *, ARMword, ARMword, int);
-static unsigned LoadByte (ARMul_State *, ARMword, ARMword, int);
-static unsigned StoreWord (ARMul_State *, ARMword, ARMword);
-static unsigned StoreHalfWord (ARMul_State *, ARMword, ARMword);
-static unsigned StoreByte (ARMul_State *, ARMword, ARMword);
-static void LoadMult (ARMul_State *, ARMword, ARMword, ARMword);
-static void StoreMult (ARMul_State *, ARMword, ARMword, ARMword);
-static void LoadSMult (ARMul_State *, ARMword, ARMword, ARMword);
-static void StoreSMult (ARMul_State *, ARMword, ARMword, ARMword);
-static unsigned Multiply64 (ARMul_State *, ARMword, int, int);
-static unsigned MultiplyAdd64 (ARMul_State *, ARMword, int, int);
-static void Handle_Load_Double (ARMul_State *, ARMword);
-static void Handle_Store_Double (ARMul_State *, ARMword);
-
-#define LUNSIGNED (0) /* unsigned operation */
-#define LSIGNED (1) /* signed operation */
-#define LDEFAULT (0) /* default : do nothing */
-#define LSCC (1) /* set condition codes on result */
-
-extern int stop_simulator;
-
-/* Short-hand macros for LDR/STR. */
-
-/* Store post decrement writeback. */
-#define SHDOWNWB() \
- lhs = LHS ; \
- if (StoreHalfWord (state, instr, lhs)) \
- LSBase = lhs - GetLS7RHS (state, instr);
-
-/* Store post increment writeback. */
-#define SHUPWB() \
- lhs = LHS ; \
- if (StoreHalfWord (state, instr, lhs)) \
- LSBase = lhs + GetLS7RHS (state, instr);
-
-/* Store pre decrement. */
-#define SHPREDOWN() \
- (void)StoreHalfWord (state, instr, LHS - GetLS7RHS (state, instr));
-
-/* Store pre decrement writeback. */
-#define SHPREDOWNWB() \
- temp = LHS - GetLS7RHS (state, instr); \
- if (StoreHalfWord (state, instr, temp)) \
- LSBase = temp;
-
-/* Store pre increment. */
-#define SHPREUP() \
- (void)StoreHalfWord (state, instr, LHS + GetLS7RHS (state, instr));
-
-/* Store pre increment writeback. */
-#define SHPREUPWB() \
- temp = LHS + GetLS7RHS (state, instr); \
- if (StoreHalfWord (state, instr, temp)) \
- LSBase = temp;
-
-/* Load post decrement writeback. */
-#define LHPOSTDOWN() \
-{ \
- int done = 1; \
- lhs = LHS; \
- temp = lhs - GetLS7RHS (state, instr); \
- \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
- LSBase = temp; \
- break; \
- case 2: /* SB */ \
- if (LoadByte (state, instr, lhs, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 3: /* SH */ \
- if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 0: /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Load post increment writeback. */
-#define LHPOSTUP() \
-{ \
- int done = 1; \
- lhs = LHS; \
- temp = lhs + GetLS7RHS (state, instr); \
- \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
- LSBase = temp; \
- break; \
- case 2: /* SB */ \
- if (LoadByte (state, instr, lhs, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 3: /* SH */ \
- if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 0: /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Load pre decrement. */
-#define LHPREDOWN() \
-{ \
- int done = 1; \
- \
- temp = LHS - GetLS7RHS (state, instr); \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \
- break; \
- case 2: /* SB */ \
- (void) LoadByte (state, instr, temp, LSIGNED); \
- break; \
- case 3: /* SH */ \
- (void) LoadHalfWord (state, instr, temp, LSIGNED); \
- break; \
- case 0: \
- /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Load pre decrement writeback. */
-#define LHPREDOWNWB() \
-{ \
- int done = 1; \
- \
- temp = LHS - GetLS7RHS (state, instr); \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \
- LSBase = temp; \
- break; \
- case 2: /* SB */ \
- if (LoadByte (state, instr, temp, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 3: /* SH */ \
- if (LoadHalfWord (state, instr, temp, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 0: \
- /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Load pre increment. */
-#define LHPREUP() \
-{ \
- int done = 1; \
- \
- temp = LHS + GetLS7RHS (state, instr); \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \
- break; \
- case 2: /* SB */ \
- (void) LoadByte (state, instr, temp, LSIGNED); \
- break; \
- case 3: /* SH */ \
- (void) LoadHalfWord (state, instr, temp, LSIGNED); \
- break; \
- case 0: \
- /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Load pre increment writeback. */
-#define LHPREUPWB() \
-{ \
- int done = 1; \
- \
- temp = LHS + GetLS7RHS (state, instr); \
- switch (BITS (5, 6)) \
- { \
- case 1: /* H */ \
- if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \
- LSBase = temp; \
- break; \
- case 2: /* SB */ \
- if (LoadByte (state, instr, temp, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 3: /* SH */ \
- if (LoadHalfWord (state, instr, temp, LSIGNED)) \
- LSBase = temp; \
- break; \
- case 0: \
- /* SWP handled elsewhere. */ \
- default: \
- done = 0; \
- break; \
- } \
- if (done) \
- break; \
-}
-
-/* Attempt to emulate an ARMv6 instruction.
- Returns non-zero upon success. */
-
-#ifdef MODE32
-static int
-handle_v6_insn (ARMul_State * state, ARMword instr)
-{
- ARMword val;
- ARMword Rd;
- ARMword Rm;
- ARMword Rn;
-
- switch (BITS (20, 27))
- {
-#if 0
- case 0x03: printf ("Unhandled v6 insn: ldr\n"); break;
- case 0x04: printf ("Unhandled v6 insn: umaal\n"); break;
- case 0x06: printf ("Unhandled v6 insn: mls/str\n"); break;
- case 0x16: printf ("Unhandled v6 insn: smi\n"); break;
- case 0x18: printf ("Unhandled v6 insn: strex\n"); break;
- case 0x19: printf ("Unhandled v6 insn: ldrex\n"); break;
- case 0x1a: printf ("Unhandled v6 insn: strexd\n"); break;
- case 0x1b: printf ("Unhandled v6 insn: ldrexd\n"); break;
- case 0x1c: printf ("Unhandled v6 insn: strexb\n"); break;
- case 0x1d: printf ("Unhandled v6 insn: ldrexb\n"); break;
- case 0x1e: printf ("Unhandled v6 insn: strexh\n"); break;
- case 0x1f: printf ("Unhandled v6 insn: ldrexh\n"); break;
- case 0x32: printf ("Unhandled v6 insn: nop/sev/wfe/wfi/yield\n"); break;
- case 0x3f: printf ("Unhandled v6 insn: rbit\n"); break;
-#endif
- case 0x61: printf ("Unhandled v6 insn: sadd/ssub\n"); break;
- case 0x63: printf ("Unhandled v6 insn: shadd/shsub\n"); break;
- case 0x6c: printf ("Unhandled v6 insn: uxtb16/uxtab16\n"); break;
- case 0x70: printf ("Unhandled v6 insn: smuad/smusd/smlad/smlsd\n"); break;
- case 0x74: printf ("Unhandled v6 insn: smlald/smlsld\n"); break;
- case 0x75: printf ("Unhandled v6 insn: smmla/smmls/smmul\n"); break;
- case 0x78: printf ("Unhandled v6 insn: usad/usada8\n"); break;
-
- case 0x30:
- {
- /* MOVW<c> <Rd>,#<imm16>
- instr[31,28] = cond
- instr[27,20] = 0011 0000
- instr[19,16] = imm4
- instr[15,12] = Rd
- instr[11, 0] = imm12. */
- Rd = BITS (12, 15);
- val = (BITS (16, 19) << 12) | BITS (0, 11);
- state->Reg[Rd] = val;
- return 1;
- }
-
- case 0x34:
- {
- /* MOVT<c> <Rd>,#<imm16>
- instr[31,28] = cond
- instr[27,20] = 0011 0100
- instr[19,16] = imm4
- instr[15,12] = Rd
- instr[11, 0] = imm12. */
- Rd = BITS (12, 15);
- val = (BITS (16, 19) << 12) | BITS (0, 11);
- state->Reg[Rd] &= 0xFFFF;
- state->Reg[Rd] |= val << 16;
- return 1;
- }
-
- case 0x62:
- {
- ARMword val1;
- ARMword val2;
- ARMsword n, m, r;
- int i;
-
- Rd = BITS (12, 15);
- Rn = BITS (16, 19);
- Rm = BITS (0, 3);
-
- if (Rd == 15 || Rn == 15 || Rm == 15)
- break;
-
- val1 = state->Reg[Rn];
- val2 = state->Reg[Rm];
-
- switch (BITS (4, 11))
- {
- case 0xF1: /* QADD16<c> <Rd>,<Rn>,<Rm>. */
- state->Reg[Rd] = 0;
-
- for (i = 0; i < 32; i+= 16)
- {
- n = (val1 >> i) & 0xFFFF;
- if (n & 0x8000)
- n |= -(1 << 16);
-
- m = (val2 >> i) & 0xFFFF;
- if (m & 0x8000)
- m |= -(1 << 16);
-
- r = n + m;
-
- if (r > 0x7FFF)
- r = 0x7FFF;
- else if (r < -(0x8000))
- r = - 0x8000;
-
- state->Reg[Rd] |= (r & 0xFFFF) << i;
- }
- return 1;
-
- case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>. */
- n = val1 & 0xFFFF;
- if (n & 0x8000)
- n |= -(1 << 16);
-
- m = (val2 >> 16) & 0xFFFF;
- if (m & 0x8000)
- m |= -(1 << 16);
-
- r = n - m;
-
- if (r > 0x7FFF)
- r = 0x7FFF;
- else if (r < -(0x8000))
- r = - 0x8000;
-
- state->Reg[Rd] = (r & 0xFFFF);
-
- n = (val1 >> 16) & 0xFFFF;
- if (n & 0x8000)
- n |= -(1 << 16);
-
- m = val2 & 0xFFFF;
- if (m & 0x8000)
- m |= -(1 << 16);
-
- r = n + m;
-
- if (r > 0x7FFF)
- r = 0x7FFF;
- else if (r < -(0x8000))
- r = - 0x8000;
-
- state->Reg[Rd] |= (r & 0xFFFF) << 16;
- return 1;
-
- case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>. */
- n = val1 & 0xFFFF;
- if (n & 0x8000)
- n |= -(1 << 16);
-
- m = (val2 >> 16) & 0xFFFF;
- if (m & 0x8000)
- m |= -(1 << 16);
-
- r = n + m;
-
- if (r > 0x7FFF)
- r = 0x7FFF;
- else if (r < -(0x8000))
- r = - 0x8000;
-
- state->Reg[Rd] = (r & 0xFFFF);
-
- n = (val1 >> 16) & 0xFFFF;
- if (n & 0x8000)
- n |= -(1 << 16);
-
- m = val2 & 0xFFFF;
- if (m & 0x8000)
- m |= -(1 << 16);
-
- r = n - m;
-
- if (r > 0x7FFF)
- r = 0x7FFF;
- else if (r < -(0x8000))
- r = - 0x8000;
-
- state->Reg[Rd] |= (r & 0xFFFF) << 16;
- return 1;
-
- case 0xF7: /* QSUB16<c> <Rd>,<Rn>,<Rm>. */
- state->Reg[Rd] = 0;
-
- for (i = 0; i < 32; i+= 16)
- {
- n = (val1 >> i) & 0xFFFF;
- if (n & 0x8000)
- n |= -(1 << 16);
-
- m = (val2 >> i) & 0xFFFF;
- if (m & 0x8000)
- m |= -(1 << 16);
-
- r = n - m;
-
- if (r > 0x7FFF)
- r = 0x7FFF;
- else if (r < -(0x8000))
- r = - 0x8000;
-
- state->Reg[Rd] |= (r & 0xFFFF) << i;
- }
- return 1;
-
- case 0xF9: /* QADD8<c> <Rd>,<Rn>,<Rm>. */
- state->Reg[Rd] = 0;
-
- for (i = 0; i < 32; i+= 8)
- {
- n = (val1 >> i) & 0xFF;
- if (n & 0x80)
- n |= - (1 << 8);
-
- m = (val2 >> i) & 0xFF;
- if (m & 0x80)
- m |= - (1 << 8);
-
- r = n + m;
-
- if (r > 127)
- r = 127;
- else if (r < -128)
- r = -128;
-
- state->Reg[Rd] |= (r & 0xFF) << i;
- }
- return 1;
-
- case 0xFF: /* QSUB8<c> <Rd>,<Rn>,<Rm>. */
- state->Reg[Rd] = 0;
-
- for (i = 0; i < 32; i+= 8)
- {
- n = (val1 >> i) & 0xFF;
- if (n & 0x80)
- n |= - (1 << 8);
-
- m = (val2 >> i) & 0xFF;
- if (m & 0x80)
- m |= - (1 << 8);
-
- r = n - m;
-
- if (r > 127)
- r = 127;
- else if (r < -128)
- r = -128;
-
- state->Reg[Rd] |= (r & 0xFF) << i;
- }
- return 1;
-
- default:
- break;
- }
- break;
- }
-
- case 0x65:
- {
- ARMword valn;
- ARMword valm;
- ARMword res1, res2, res3, res4;
-
- /* U{ADD|SUB}{8|16}<c> <Rd>, <Rn>, <Rm>
- instr[31,28] = cond
- instr[27,20] = 0110 0101
- instr[19,16] = Rn
- instr[15,12] = Rd
- instr[11, 8] = 1111
- instr[ 7, 4] = opcode: UADD8 (1001), UADD16 (0001), USUB8 (1111), USUB16 (0111)
- instr[ 3, 0] = Rm. */
- if (BITS (8, 11) != 0xF)
- break;
-
- Rn = BITS (16, 19);
- Rd = BITS (12, 15);
- Rm = BITS (0, 3);
-
- if (Rn == 15 || Rd == 15 || Rm == 15)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- break;
- }
-
- valn = state->Reg[Rn];
- valm = state->Reg[Rm];
-
- switch (BITS (4, 7))
- {
- case 1: /* UADD16. */
- res1 = (valn & 0xFFFF) + (valm & 0xFFFF);
- if (res1 > 0xFFFF)
- state->Cpsr |= (GE0 | GE1);
- else
- state->Cpsr &= ~ (GE0 | GE1);
-
- res2 = (valn >> 16) + (valm >> 16);
- if (res2 > 0xFFFF)
- state->Cpsr |= (GE2 | GE3);
- else
- state->Cpsr &= ~ (GE2 | GE3);
-
- state->Reg[Rd] = (res1 & 0xFFFF) | (res2 << 16);
- return 1;
-
- case 7: /* USUB16. */
- res1 = (valn & 0xFFFF) - (valm & 0xFFFF);
- if (res1 & 0x800000)
- state->Cpsr |= (GE0 | GE1);
- else
- state->Cpsr &= ~ (GE0 | GE1);
-
- res2 = (valn >> 16) - (valm >> 16);
- if (res2 & 0x800000)
- state->Cpsr |= (GE2 | GE3);
- else
- state->Cpsr &= ~ (GE2 | GE3);
-
- state->Reg[Rd] = (res1 & 0xFFFF) | (res2 << 16);
- return 1;
-
- case 9: /* UADD8. */
- res1 = (valn & 0xFF) + (valm & 0xFF);
- if (res1 > 0xFF)
- state->Cpsr |= GE0;
- else
- state->Cpsr &= ~ GE0;
-
- res2 = ((valn >> 8) & 0xFF) + ((valm >> 8) & 0xFF);
- if (res2 > 0xFF)
- state->Cpsr |= GE1;
- else
- state->Cpsr &= ~ GE1;
-
- res3 = ((valn >> 16) & 0xFF) + ((valm >> 16) & 0xFF);
- if (res3 > 0xFF)
- state->Cpsr |= GE2;
- else
- state->Cpsr &= ~ GE2;
-
- res4 = (valn >> 24) + (valm >> 24);
- if (res4 > 0xFF)
- state->Cpsr |= GE3;
- else
- state->Cpsr &= ~ GE3;
-
- state->Reg[Rd] = (res1 & 0xFF) | ((res2 << 8) & 0xFF00)
- | ((res3 << 16) & 0xFF0000) | (res4 << 24);
- return 1;
-
- case 15: /* USUB8. */
- res1 = (valn & 0xFF) - (valm & 0xFF);
- if (res1 & 0x800000)
- state->Cpsr |= GE0;
- else
- state->Cpsr &= ~ GE0;
-
- res2 = ((valn >> 8) & 0XFF) - ((valm >> 8) & 0xFF);
- if (res2 & 0x800000)
- state->Cpsr |= GE1;
- else
- state->Cpsr &= ~ GE1;
-
- res3 = ((valn >> 16) & 0XFF) - ((valm >> 16) & 0xFF);
- if (res3 & 0x800000)
- state->Cpsr |= GE2;
- else
- state->Cpsr &= ~ GE2;
-
- res4 = (valn >> 24) - (valm >> 24) ;
- if (res4 & 0x800000)
- state->Cpsr |= GE3;
- else
- state->Cpsr &= ~ GE3;
-
- state->Reg[Rd] = (res1 & 0xFF) | ((res2 << 8) & 0xFF00)
- | ((res3 << 16) & 0xFF0000) | (res4 << 24);
- return 1;
-
- default:
- break;
- }
- break;
- }
-
- case 0x68:
- {
- ARMword res;
-
- /* PKHBT<c> <Rd>,<Rn>,<Rm>{,LSL #<imm>}
- PKHTB<c> <Rd>,<Rn>,<Rm>{,ASR #<imm>}
- SXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>}
- SXTB16<c> <Rd>,<Rm>{,<rotation>}
- SEL<c> <Rd>,<Rn>,<Rm>
-
- instr[31,28] = cond
- instr[27,20] = 0110 1000
- instr[19,16] = Rn
- instr[15,12] = Rd
- instr[11, 7] = imm5 (PKH), 11111 (SEL), rr000 (SXTAB16 & SXTB16),
- instr[6] = tb (PKH), 0 (SEL), 1 (SXT)
- instr[5] = opcode: PKH (0), SEL/SXT (1)
- instr[4] = 1
- instr[ 3, 0] = Rm. */
-
- if (BIT (4) != 1)
- break;
-
- if (BIT (5) == 0)
- {
- /* FIXME: Add implementation of PKH. */
- fprintf (stderr, "PKH: NOT YET IMPLEMENTED\n");
- ARMul_UndefInstr (state, instr);
- break;
- }
-
- if (BIT (6) == 1)
- {
- /* FIXME: Add implementation of SXT. */
- fprintf (stderr, "SXT: NOT YET IMPLEMENTED\n");
- ARMul_UndefInstr (state, instr);
- break;
- }
-
- Rn = BITS (16, 19);
- Rd = BITS (12, 15);
- Rm = BITS (0, 3);
- if (Rn == 15 || Rm == 15 || Rd == 15)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- break;
- }
-
- res = (state->Reg[(state->Cpsr & GE0) ? Rn : Rm]) & 0xFF;
- res |= (state->Reg[(state->Cpsr & GE1) ? Rn : Rm]) & 0xFF00;
- res |= (state->Reg[(state->Cpsr & GE2) ? Rn : Rm]) & 0xFF0000;
- res |= (state->Reg[(state->Cpsr & GE3) ? Rn : Rm]) & 0xFF000000;
- state->Reg[Rd] = res;
- return 1;
- }
-
- case 0x6a:
- {
- int ror = -1;
-
- switch (BITS (4, 11))
- {
- case 0x07: ror = 0; break;
- case 0x47: ror = 8; break;
- case 0x87: ror = 16; break;
- case 0xc7: ror = 24; break;
-
- case 0x01:
- case 0xf3:
- printf ("Unhandled v6 insn: ssat\n");
- return 0;
-
- default:
- break;
- }
-
- if (ror == -1)
- {
- if (BITS (4, 6) == 0x7)
- {
- printf ("Unhandled v6 insn: ssat\n");
- return 0;
- }
- break;
- }
-
- Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
- if (Rm & 0x80)
- Rm |= 0xffffff00;
-
- if (BITS (16, 19) == 0xf)
- /* SXTB */
- state->Reg[BITS (12, 15)] = Rm;
- else
- /* SXTAB */
- state->Reg[BITS (12, 15)] += Rm;
- }
- return 1;
-
- case 0x6b:
- {
- int ror = -1;
-
- switch (BITS (4, 11))
- {
- case 0x07: ror = 0; break;
- case 0x47: ror = 8; break;
- case 0x87: ror = 16; break;
- case 0xc7: ror = 24; break;
-
- case 0xf3:
- {
- /* REV<c> <Rd>,<Rm>
- instr[31,28] = cond
- instr[27,20] = 0110 1011
- instr[19,16] = 1111
- instr[15,12] = Rd
- instr[11, 4] = 1111 0011
- instr[ 3, 0] = Rm. */
- if (BITS (16, 19) != 0xF)
- break;
-
- Rd = BITS (12, 15);
- Rm = BITS (0, 3);
- if (Rd == 15 || Rm == 15)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- break;
- }
-
- val = state->Reg[Rm] << 24;
- val |= ((state->Reg[Rm] << 8) & 0xFF0000);
- val |= ((state->Reg[Rm] >> 8) & 0xFF00);
- val |= ((state->Reg[Rm] >> 24));
- state->Reg[Rd] = val;
- return 1;
- }
-
- case 0xfb:
- {
- /* REV16<c> <Rd>,<Rm>. */
- if (BITS (16, 19) != 0xF)
- break;
-
- Rd = BITS (12, 15);
- Rm = BITS (0, 3);
- if (Rd == 15 || Rm == 15)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- break;
- }
-
- val = 0;
- val |= ((state->Reg[Rm] >> 8) & 0x00FF00FF);
- val |= ((state->Reg[Rm] << 8) & 0xFF00FF00);
- state->Reg[Rd] = val;
- return 1;
- }
-
- default:
- break;
- }
-
- if (ror == -1)
- break;
-
- Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF);
- if (Rm & 0x8000)
- Rm |= 0xffff0000;
-
- if (BITS (16, 19) == 0xf)
- /* SXTH */
- state->Reg[BITS (12, 15)] = Rm;
- else
- /* SXTAH */
- state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm;
- }
- return 1;
-
- case 0x6e:
- {
- int ror = -1;
-
- switch (BITS (4, 11))
- {
- case 0x07: ror = 0; break;
- case 0x47: ror = 8; break;
- case 0x87: ror = 16; break;
- case 0xc7: ror = 24; break;
-
- case 0x01:
- case 0xf3:
- printf ("Unhandled v6 insn: usat\n");
- return 0;
-
- default:
- break;
- }
-
- if (ror == -1)
- {
- if (BITS (4, 6) == 0x7)
- {
- printf ("Unhandled v6 insn: usat\n");
- return 0;
- }
- break;
- }
-
- Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
-
- if (BITS (16, 19) == 0xf)
- /* UXTB */
- state->Reg[BITS (12, 15)] = Rm;
- else
- /* UXTAB */
- state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm;
- }
- return 1;
-
- case 0x6f:
- {
- int i;
- int ror = -1;
-
- switch (BITS (4, 11))
- {
- case 0x07: ror = 0; break;
- case 0x47: ror = 8; break;
- case 0x87: ror = 16; break;
- case 0xc7: ror = 24; break;
-
- case 0xf3: /* RBIT */
- if (BITS (16, 19) != 0xF)
- break;
- Rd = BITS (12, 15);
- state->Reg[Rd] = 0;
- Rm = state->Reg[BITS (0, 3)];
- for (i = 0; i < 32; i++)
- if (Rm & (1 << i))
- state->Reg[Rd] |= (1 << (31 - i));
- return 1;
-
- case 0xfb:
- printf ("Unhandled v6 insn: revsh\n");
- return 0;
-
- default:
- break;
- }
-
- if (ror == -1)
- break;
-
- Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF);
-
- if (BITS (16, 19) == 0xf)
- /* UXT */
- state->Reg[BITS (12, 15)] = Rm;
- else
- /* UXTAH */
- state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm;
- }
- return 1;
-
- case 0x71:
- case 0x73:
- {
- ARMword valn, valm;
- /* SDIV<c> <Rd>,<Rn>,<Rm>
- UDIV<c> <Rd>,<Rn>,<Rm>
- instr[31,28] = cond
- instr[27,20] = 0111 0001 (SDIV), 0111 0011 (UDIV)
- instr[21,21] = sign
- instr[19,16] = Rn
- instr[15,12] = 1111
- instr[11, 8] = Rd
- instr[ 7, 4] = 1111
- instr[ 3, 0] = Rm */
- /* These bit-positions are confusing!
- instr[15,12] = Rd
- instr[11, 8] = 1111 */
-
-#if 0 /* This is what I would expect: */
- Rn = BITS (16, 19);
- Rd = BITS (8, 11);
- Rm = BITS (0, 3);
-#else /* This seem to work: */
- Rd = BITS (16, 19);
- Rm = BITS (8, 11);
- Rn = BITS (0, 3);
-#endif
- if (Rn == 15 || Rd == 15 || Rm == 15
- || Rn == 13 || Rd == 13 || Rm == 13)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- break;
- }
-
- valn = state->Reg[Rn];
- valm = state->Reg[Rm];
-
- if (valm == 0)
- {
-#if 0
- /* Exceptions: UsageFault, address 20
- Note: UsageFault is for Cortex-M; I don't know what it would be on non-Cortex-M. */
- ARMul_Abort (state, address);
-#endif
- printf ("Unhandled v6 insn: %cDIV divide by zero exception\n", "SU"[BIT(21)]);
- }
- else
- {
- if(BIT(21))
- {
- val = valn / valm;
- }
- else
- {
- val = ((ARMsword)valn / (ARMsword)valm);
- }
- state->Reg[Rd] = val;
- }
- return 1;
- }
-
- case 0x7c:
- case 0x7d:
- {
- int lsb;
- int msb;
- ARMword mask;
-
- /* BFC<c> <Rd>,#<lsb>,#<width>
- BFI<c> <Rd>,<Rn>,#<lsb>,#<width>
-
- instr[31,28] = cond
- instr[27,21] = 0111 110
- instr[20,16] = msb
- instr[15,12] = Rd
- instr[11, 7] = lsb
- instr[ 6, 4] = 001 1111
- instr[ 3, 0] = Rn (BFI) / 1111 (BFC). */
-
- if (BITS (4, 6) != 0x1)
- break;
-
- Rd = BITS (12, 15);
- if (Rd == 15)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- }
-
- lsb = BITS (7, 11);
- msb = BITS (16, 20);
- if (lsb > msb)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- }
-
- mask = -(1 << lsb);
- mask &= ~(-(1 << (msb + 1)));
- state->Reg[Rd] &= ~ mask;
-
- Rn = BITS (0, 3);
- if (Rn != 0xF)
- {
- val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb)));
- state->Reg[Rd] |= val << lsb;
- }
- return 1;
- }
- case 0x7b:
- case 0x7a: /* SBFX<c> <Rd>,<Rn>,#<lsb>,#<width>. */
- {
- int lsb;
- int widthm1;
- ARMsword sval;
-
- if (BITS (4, 6) != 0x5)
- break;
-
- Rd = BITS (12, 15);
- if (Rd == 15)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- }
-
- Rn = BITS (0, 3);
- if (Rn == 15)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- }
-
- lsb = BITS (7, 11);
- widthm1 = BITS (16, 20);
-
- sval = state->Reg[Rn];
- sval <<= (31 - (lsb + widthm1));
- sval >>= (31 - widthm1);
- state->Reg[Rd] = sval;
-
- return 1;
- }
-
- case 0x7f:
- case 0x7e:
- {
- int lsb;
- int widthm1;
-
- /* UBFX<c> <Rd>,<Rn>,#<lsb>,#<width>
- instr[31,28] = cond
- instr[27,21] = 0111 111
- instr[20,16] = widthm1
- instr[15,12] = Rd
- instr[11, 7] = lsb
- instr[ 6, 4] = 101
- instr[ 3, 0] = Rn. */
-
- if (BITS (4, 6) != 0x5)
- break;
-
- Rd = BITS (12, 15);
- if (Rd == 15)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- }
-
- Rn = BITS (0, 3);
- if (Rn == 15)
- {
- ARMul_UndefInstr (state, instr);
- state->Emulate = FALSE;
- }
-
- lsb = BITS (7, 11);
- widthm1 = BITS (16, 20);
-
- val = state->Reg[Rn];
- val >>= lsb;
- val &= ~(-(1 << (widthm1 + 1)));
-
- state->Reg[Rd] = val;
-
- return 1;
- }
-#if 0
- case 0x84: printf ("Unhandled v6 insn: srs\n"); break;
-#endif
- default:
- break;
- }
- printf ("Unhandled v6 insn: UNKNOWN: %08x\n", instr);
- return 0;
-}
-#endif
-
-static void
-handle_VFP_move (ARMul_State * state, ARMword instr)
-{
- switch (BITS (20, 27))
- {
- case 0xC4:
- case 0xC5:
- switch (BITS (4, 11))
- {
- case 0xA1:
- case 0xA3:
- {
- /* VMOV two core <-> two VFP single precision. */
- int sreg = (BITS (0, 3) << 1) | BIT (5);
-
- if (BIT (20))
- {
- state->Reg[BITS (12, 15)] = VFP_uword (sreg);
- state->Reg[BITS (16, 19)] = VFP_uword (sreg + 1);
- }
- else
- {
- VFP_uword (sreg) = state->Reg[BITS (12, 15)];
- VFP_uword (sreg + 1) = state->Reg[BITS (16, 19)];
- }
- }
- break;
-
- case 0xB1:
- case 0xB3:
- {
- /* VMOV two core <-> VFP double precision. */
- int dreg = BITS (0, 3) | (BIT (5) << 4);
-
- if (BIT (20))
- {
- if (trace)
- fprintf (stderr, " VFP: VMOV: r%d r%d <= d%d\n",
- BITS (12, 15), BITS (16, 19), dreg);
-
- state->Reg[BITS (12, 15)] = VFP_dword (dreg);
- state->Reg[BITS (16, 19)] = VFP_dword (dreg) >> 32;
- }
- else
- {
- VFP_dword (dreg) = state->Reg[BITS (16, 19)];
- VFP_dword (dreg) <<= 32;
- VFP_dword (dreg) |= state->Reg[BITS (12, 15)];
-
- if (trace)
- fprintf (stderr, " VFP: VMOV: d%d <= r%d r%d : %g\n",
- dreg, BITS (16, 19), BITS (12, 15),
- VFP_dval (dreg));
- }
- }
- break;
-
- default:
- fprintf (stderr, "SIM: VFP: Unimplemented move insn %x\n", BITS (20, 27));
- break;
- }
- break;
-
- case 0xe0:
- case 0xe1:
- /* VMOV single core <-> VFP single precision. */
- if (BITS (0, 6) != 0x10 || BITS (8, 11) != 0xA)
- fprintf (stderr, "SIM: VFP: Unimplemented move insn %x\n", BITS (20, 27));
- else
- {
- int sreg = (BITS (16, 19) << 1) | BIT (7);
-
- if (BIT (20))
- state->Reg[DESTReg] = VFP_uword (sreg);
- else
- VFP_uword (sreg) = state->Reg[DESTReg];
- }
- break;
-
- default:
- fprintf (stderr, "SIM: VFP: Unimplemented move insn %x\n", BITS (20, 27));
- return;
- }
-}
-
-/* EMULATION of ARM6. */
-
-ARMword
-#ifdef MODE32
-ARMul_Emulate32 (ARMul_State * state)
-#else
-ARMul_Emulate26 (ARMul_State * state)
-#endif
-{
- ARMword instr; /* The current instruction. */
- ARMword dest = 0; /* Almost the DestBus. */
- ARMword temp; /* Ubiquitous third hand. */
- ARMword pc = 0; /* The address of the current instruction. */
- ARMword lhs; /* Almost the ABus and BBus. */
- ARMword rhs;
- ARMword decoded = 0; /* Instruction pipeline. */
- ARMword loaded = 0;
-
- /* Execute the next instruction. */
-
- if (state->NextInstr < PRIMEPIPE)
- {
- decoded = state->decoded;
- loaded = state->loaded;
- pc = state->pc;
- }
-
- do
- {
- /* Just keep going. */
- isize = INSN_SIZE;
-
- switch (state->NextInstr)
- {
- case SEQ:
- /* Advance the pipeline, and an S cycle. */
- state->Reg[15] += isize;
- pc += isize;
- instr = decoded;
- decoded = loaded;
- loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
- break;
-
- case NONSEQ:
- /* Advance the pipeline, and an N cycle. */
- state->Reg[15] += isize;
- pc += isize;
- instr = decoded;
- decoded = loaded;
- loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize);
- NORMALCYCLE;
- break;
-
- case PCINCEDSEQ:
- /* Program counter advanced, and an S cycle. */
- pc += isize;
- instr = decoded;
- decoded = loaded;
- loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
- NORMALCYCLE;
- break;
-
- case PCINCEDNONSEQ:
- /* Program counter advanced, and an N cycle. */
- pc += isize;
- instr = decoded;
- decoded = loaded;
- loaded = ARMul_LoadInstrN (state, pc + (isize * 2), isize);
- NORMALCYCLE;
- break;
-
- case RESUME:
- /* The program counter has been changed. */
- pc = state->Reg[15];
-#ifndef MODE32
- pc = pc & R15PCBITS;
-#endif
- state->Reg[15] = pc + (isize * 2);
- state->Aborted = 0;
- instr = ARMul_ReLoadInstr (state, pc, isize);
- decoded = ARMul_ReLoadInstr (state, pc + isize, isize);
- loaded = ARMul_ReLoadInstr (state, pc + isize * 2, isize);
- NORMALCYCLE;
- break;
-
- default:
- /* The program counter has been changed. */
- pc = state->Reg[15];
-#ifndef MODE32
- pc = pc & R15PCBITS;
-#endif
- state->Reg[15] = pc + (isize * 2);
- state->Aborted = 0;
- instr = ARMul_LoadInstrN (state, pc, isize);
- decoded = ARMul_LoadInstrS (state, pc + (isize), isize);
- loaded = ARMul_LoadInstrS (state, pc + (isize * 2), isize);
- NORMALCYCLE;
- break;
- }
-
- if (state->EventSet)
- ARMul_EnvokeEvent (state);
-
- if (! TFLAG && trace)
- {
- fprintf (stderr, "pc: %x, ", pc & ~1);
- if (! disas)
- fprintf (stderr, "instr: %x\n", instr);
- }
-
- if (instr == 0 || pc < 0x10)
- {
- ARMul_Abort (state, ARMUndefinedInstrV);
- state->Emulate = FALSE;
- }
-
-#if 0 /* Enable this code to help track down stack alignment bugs. */
- {
- static ARMword old_sp = -1;
-
- if (old_sp != state->Reg[13])
- {
- old_sp = state->Reg[13];
- fprintf (stderr, "pc: %08x: SP set to %08x%s\n",
- pc & ~1, old_sp, (old_sp % 8) ? " [UNALIGNED!]" : "");
- }
- }
-#endif
-
- if (state->Exception)
- {
- /* Any exceptions ? */
- if (state->NresetSig == LOW)
- {
- ARMul_Abort (state, ARMul_ResetV);
- break;
- }
- else if (!state->NfiqSig && !FFLAG)
- {
- ARMul_Abort (state, ARMul_FIQV);
- break;
- }
- else if (!state->NirqSig && !IFLAG)
- {
- ARMul_Abort (state, ARMul_IRQV);
- break;
- }
- }
-
- if (state->CallDebug > 0)
- {
- if (state->Emulate < ONCE)
- {
- state->NextInstr = RESUME;
- break;
- }
- if (state->Debug)
- {
- fprintf (stderr, "sim: At %08lx Instr %08lx Mode %02lx\n",
- (long) pc, (long) instr, (long) state->Mode);
- (void) fgetc (stdin);
- }
- }
- else if (state->Emulate < ONCE)
- {
- state->NextInstr = RESUME;
- break;
- }
-
- state->NumInstrs++;
-
-#ifdef MODET
- /* Provide Thumb instruction decoding. If the processor is in Thumb
- mode, then we can simply decode the Thumb instruction, and map it
- to the corresponding ARM instruction (by directly loading the
- instr variable, and letting the normal ARM simulator
- execute). There are some caveats to ensure that the correct
- pipelined PC value is used when executing Thumb code, and also for
- dealing with the BL instruction. */
- if (TFLAG)
- {
- ARMword new;
-
- /* Check if in Thumb mode. */
- switch (ARMul_ThumbDecode (state, pc, instr, &new))
- {
- case t_undefined:
- /* This is a Thumb instruction. */
- ARMul_UndefInstr (state, instr);
- goto donext;
-
- case t_branch:
- /* Already processed. */
- goto donext;
-
- case t_decoded:
- /* ARM instruction available. */
- if (disas || trace)
- {
- fprintf (stderr, " emulate as: ");
- if (trace)
- fprintf (stderr, "%08x ", new);
- if (! disas)
- fprintf (stderr, "\n");
- }
- instr = new;
- /* So continue instruction decoding. */
- break;
- default:
- break;
- }
- }
-#endif
- if (disas)
- print_insn (instr);
-
- /* Check the condition codes. */
- if ((temp = TOPBITS (28)) == AL)
- /* Vile deed in the need for speed. */
- goto mainswitch;
-
- /* Check the condition code. */
- switch ((int) TOPBITS (28))
- {
- case AL:
- temp = TRUE;
- break;
- case NV:
- if (state->is_v5)
- {
- if (BITS (25, 27) == 5) /* BLX(1) */
- {
- state->Reg[14] = pc + 4;
-
- /* Force entry into Thumb mode. */
- dest = pc + 8 + 1;
- if (BIT (23))
- dest += (NEGBRANCH + (BIT (24) << 1));
- else
- dest += POSBRANCH + (BIT (24) << 1);
-
- WriteR15Branch (state, dest);
- goto donext;
- }
- else if ((instr & 0xFC70F000) == 0xF450F000)
- /* The PLD instruction. Ignored. */
- goto donext;
- else if ( ((instr & 0xfe500f00) == 0xfc100100)
- || ((instr & 0xfe500f00) == 0xfc000100))
- /* wldrw and wstrw are unconditional. */
- goto mainswitch;
- else
- /* UNDEFINED in v5, UNPREDICTABLE in v3, v4, non executed in v1, v2. */
- ARMul_UndefInstr (state, instr);
- }
- temp = FALSE;
- break;
- case EQ:
- temp = ZFLAG;
- break;
- case NE:
- temp = !ZFLAG;
- break;
- case VS:
- temp = VFLAG;
- break;
- case VC:
- temp = !VFLAG;
- break;
- case MI:
- temp = NFLAG;
- break;
- case PL:
- temp = !NFLAG;
- break;
- case CS:
- temp = CFLAG;
- break;
- case CC:
- temp = !CFLAG;
- break;
- case HI:
- temp = (CFLAG && !ZFLAG);
- break;
- case LS:
- temp = (!CFLAG || ZFLAG);
- break;
- case GE:
- temp = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
- break;
- case LT:
- temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
- break;
- case GT:
- temp = ((!NFLAG && !VFLAG && !ZFLAG) || (NFLAG && VFLAG && !ZFLAG));
- break;
- case LE:
- temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
- break;
- } /* cc check */
-
- /* Handle the Clock counter here. */
- if (state->is_XScale)
- {
- ARMword cp14r0;
- int ok;
-
- ok = state->CPRead[14] (state, 0, & cp14r0);
-
- if (ok && (cp14r0 & ARMul_CP14_R0_ENABLE))
- {
- unsigned long newcycles, nowtime = ARMul_Time (state);
-
- newcycles = nowtime - state->LastTime;
- state->LastTime = nowtime;
-
- if (cp14r0 & ARMul_CP14_R0_CCD)
- {
- if (state->CP14R0_CCD == -1)
- state->CP14R0_CCD = newcycles;
- else
- state->CP14R0_CCD += newcycles;
-
- if (state->CP14R0_CCD >= 64)
- {
- newcycles = 0;
-
- while (state->CP14R0_CCD >= 64)
- state->CP14R0_CCD -= 64, newcycles++;
-
- goto check_PMUintr;
- }
- }
- else
- {
- ARMword cp14r1;
- int do_int;
-
- state->CP14R0_CCD = -1;
-check_PMUintr:
- do_int = 0;
- cp14r0 |= ARMul_CP14_R0_FLAG2;
- (void) state->CPWrite[14] (state, 0, cp14r0);
-
- ok = state->CPRead[14] (state, 1, & cp14r1);
-
- /* Coded like this for portability. */
- while (ok && newcycles)
- {
- if (cp14r1 == 0xffffffff)
- {
- cp14r1 = 0;
- do_int = 1;
- }
- else
- cp14r1 ++;
-
- newcycles --;
- }
-
- (void) state->CPWrite[14] (state, 1, cp14r1);
-
- if (do_int && (cp14r0 & ARMul_CP14_R0_INTEN2))
- {
- ARMword cp;
-
- if (state->CPRead[13] (state, 8, & cp)
- && (cp & ARMul_CP13_R8_PMUS))
- ARMul_Abort (state, ARMul_FIQV);
- else
- ARMul_Abort (state, ARMul_IRQV);
- }
- }
- }
- }
-
- /* Handle hardware instructions breakpoints here. */
- if (state->is_XScale)
- {
- if ( (pc | 3) == (read_cp15_reg (14, 0, 8) | 2)
- || (pc | 3) == (read_cp15_reg (14, 0, 9) | 2))
- {
- if (XScale_debug_moe (state, ARMul_CP14_R10_MOE_IB))
- ARMul_OSHandleSWI (state, SWI_Breakpoint);
- }
- }
-
- /* Actual execution of instructions begins here. */
- /* If the condition codes don't match, stop here. */
- if (temp)
- {
- mainswitch:
-
- if (state->is_XScale)
- {
- if (BIT (20) == 0 && BITS (25, 27) == 0)
- {
- if (BITS (4, 7) == 0xD)
- {
- /* XScale Load Consecutive insn. */
- ARMword temp1 = GetLS7RHS (state, instr);
- ARMword temp2 = BIT (23) ? LHS + temp1 : LHS - temp1;
- ARMword addr = BIT (24) ? temp2 : LHS;
-
- if (BIT (12))
- ARMul_UndefInstr (state, instr);
- else if (addr & 7)
- /* Alignment violation. */
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- {
- int wb = BIT (21) || (! BIT (24));
-
- state->Reg[BITS (12, 15)] =
- ARMul_LoadWordN (state, addr);
- state->Reg[BITS (12, 15) + 1] =
- ARMul_LoadWordN (state, addr + 4);
- if (wb)
- LSBase = temp2;
- }
-
- goto donext;
- }
- else if (BITS (4, 7) == 0xF)
- {
- /* XScale Store Consecutive insn. */
- ARMword temp1 = GetLS7RHS (state, instr);
- ARMword temp2 = BIT (23) ? LHS + temp1 : LHS - temp1;
- ARMword addr = BIT (24) ? temp2 : LHS;
-
- if (BIT (12))
- ARMul_UndefInstr (state, instr);
- else if (addr & 7)
- /* Alignment violation. */
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- {
- ARMul_StoreWordN (state, addr,
- state->Reg[BITS (12, 15)]);
- ARMul_StoreWordN (state, addr + 4,
- state->Reg[BITS (12, 15) + 1]);
-
- if (BIT (21)|| ! BIT (24))
- LSBase = temp2;
- }
-
- goto donext;
- }
- }
-
- if (ARMul_HandleIwmmxt (state, instr))
- goto donext;
- }
-
- switch ((int) BITS (20, 27))
- {
- /* Data Processing Register RHS Instructions. */
-
- case 0x00: /* AND reg and MUL */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, no write-back, down, post indexed. */
- SHDOWNWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- if (BITS (4, 7) == 9)
- {
- /* MUL */
- rhs = state->Reg[MULRHSReg];
- if (MULLHSReg == MULDESTReg)
- {
- UNDEF_MULDestEQOp1;
- state->Reg[MULDESTReg] = 0;
- }
- else if (MULDESTReg != 15)
- state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs;
- else
- UNDEF_MULPCDest;
-
- for (dest = 0, temp = 0; dest < 32; dest ++)
- if (rhs & (1L << dest))
- temp = dest;
-
- /* Mult takes this many/2 I cycles. */
- ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
- }
- else
- {
- /* AND reg. */
- rhs = DPRegRHS;
- dest = LHS & rhs;
- WRITEDEST (dest);
- }
- break;
-
- case 0x01: /* ANDS reg and MULS */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- /* LDR register offset, no write-back, down, post indexed. */
- LHPOSTDOWN ();
- /* Fall through to rest of decoding. */
-#endif
- if (BITS (4, 7) == 9)
- {
- /* MULS */
- rhs = state->Reg[MULRHSReg];
-
- if (MULLHSReg == MULDESTReg)
- {
- UNDEF_MULDestEQOp1;
- state->Reg[MULDESTReg] = 0;
- CLEARN;
- SETZ;
- }
- else if (MULDESTReg != 15)
- {
- dest = state->Reg[MULLHSReg] * rhs;
- ARMul_NegZero (state, dest);
- state->Reg[MULDESTReg] = dest;
- }
- else
- UNDEF_MULPCDest;
-
- for (dest = 0, temp = 0; dest < 32; dest ++)
- if (rhs & (1L << dest))
- temp = dest;
-
- /* Mult takes this many/2 I cycles. */
- ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
- }
- else
- {
- /* ANDS reg. */
- rhs = DPSRegRHS;
- dest = LHS & rhs;
- WRITESDEST (dest);
- }
- break;
-
- case 0x02: /* EOR reg and MLA */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, write-back, down, post indexed. */
- SHDOWNWB ();
- break;
- }
-#endif
- if (BITS (4, 7) == 9)
- { /* MLA */
- rhs = state->Reg[MULRHSReg];
- if (MULLHSReg == MULDESTReg)
- {
- UNDEF_MULDestEQOp1;
- state->Reg[MULDESTReg] = state->Reg[MULACCReg];
- }
- else if (MULDESTReg != 15)
- state->Reg[MULDESTReg] =
- state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg];
- else
- UNDEF_MULPCDest;
-
- for (dest = 0, temp = 0; dest < 32; dest ++)
- if (rhs & (1L << dest))
- temp = dest;
-
- /* Mult takes this many/2 I cycles. */
- ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
- }
- else
- {
- rhs = DPRegRHS;
- dest = LHS ^ rhs;
- WRITEDEST (dest);
- }
- break;
-
- case 0x03: /* EORS reg and MLAS */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- /* LDR register offset, write-back, down, post-indexed. */
- LHPOSTDOWN ();
- /* Fall through to rest of the decoding. */
-#endif
- if (BITS (4, 7) == 9)
- {
- /* MLAS */
- rhs = state->Reg[MULRHSReg];
-
- if (MULLHSReg == MULDESTReg)
- {
- UNDEF_MULDestEQOp1;
- dest = state->Reg[MULACCReg];
- ARMul_NegZero (state, dest);
- state->Reg[MULDESTReg] = dest;
- }
- else if (MULDESTReg != 15)
- {
- dest =
- state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg];
- ARMul_NegZero (state, dest);
- state->Reg[MULDESTReg] = dest;
- }
- else
- UNDEF_MULPCDest;
-
- for (dest = 0, temp = 0; dest < 32; dest ++)
- if (rhs & (1L << dest))
- temp = dest;
-
- /* Mult takes this many/2 I cycles. */
- ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
- }
- else
- {
- /* EORS Reg. */
- rhs = DPSRegRHS;
- dest = LHS ^ rhs;
- WRITESDEST (dest);
- }
- break;
-
- case 0x04: /* SUB reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, no write-back, down, post indexed. */
- SHDOWNWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS - rhs;
- WRITEDEST (dest);
- break;
-
- case 0x05: /* SUBS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- /* LDR immediate offset, no write-back, down, post indexed. */
- LHPOSTDOWN ();
- /* Fall through to the rest of the instruction decoding. */
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs - rhs;
-
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x06: /* RSB reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, write-back, down, post indexed. */
- SHDOWNWB ();
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = rhs - LHS;
- WRITEDEST (dest);
- break;
-
- case 0x07: /* RSBS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- /* LDR immediate offset, write-back, down, post indexed. */
- LHPOSTDOWN ();
- /* Fall through to remainder of instruction decoding. */
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = rhs - lhs;
-
- if ((rhs >= lhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, rhs, lhs, dest);
- ARMul_SubOverflow (state, rhs, lhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x08: /* ADD reg */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, no write-back, up, post indexed. */
- SHUPWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
-#ifdef MODET
- if (BITS (4, 7) == 0x9)
- {
- /* MULL */
- /* 32x32 = 64 */
- ARMul_Icycles (state,
- Multiply64 (state, instr, LUNSIGNED,
- LDEFAULT), 0L);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS + rhs;
- WRITEDEST (dest);
- break;
-
- case 0x09: /* ADDS reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- /* LDR register offset, no write-back, up, post indexed. */
- LHPOSTUP ();
- /* Fall through to remaining instruction decoding. */
-#endif
-#ifdef MODET
- if (BITS (4, 7) == 0x9)
- {
- /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- Multiply64 (state, instr, LUNSIGNED, LSCC),
- 0L);
- break;
- }
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs + rhs;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- {
- /* Possible C,V,N to set. */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x0a: /* ADC reg */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, write-back, up, post-indexed. */
- SHUPWB ();
- break;
- }
- if (BITS (4, 7) == 0x9)
- {
- /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- MultiplyAdd64 (state, instr, LUNSIGNED,
- LDEFAULT), 0L);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS + rhs + CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x0b: /* ADCS reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- /* LDR register offset, write-back, up, post indexed. */
- LHPOSTUP ();
- /* Fall through to remaining instruction decoding. */
- if (BITS (4, 7) == 0x9)
- {
- /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- MultiplyAdd64 (state, instr, LUNSIGNED,
- LSCC), 0L);
- break;
- }
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs + rhs + CFLAG;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- {
- /* Possible C,V,N to set. */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x0c: /* SBC reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, no write-back, up post indexed. */
- SHUPWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0x9)
- {
- /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- Multiply64 (state, instr, LSIGNED, LDEFAULT),
- 0L);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS - rhs - !CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x0d: /* SBCS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- /* LDR immediate offset, no write-back, up, post indexed. */
- LHPOSTUP ();
-
- if (BITS (4, 7) == 0x9)
- {
- /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- Multiply64 (state, instr, LSIGNED, LSCC),
- 0L);
- break;
- }
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs - rhs - !CFLAG;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x0e: /* RSC reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, write-back, up, post indexed. */
- SHUPWB ();
- break;
- }
-
- if (BITS (4, 7) == 0x9)
- {
- /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- MultiplyAdd64 (state, instr, LSIGNED,
- LDEFAULT), 0L);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = rhs - LHS - !CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x0f: /* RSCS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- /* LDR immediate offset, write-back, up, post indexed. */
- LHPOSTUP ();
- /* Fall through to remaining instruction decoding. */
-
- if (BITS (4, 7) == 0x9)
- {
- /* MULL */
- /* 32x32=64 */
- ARMul_Icycles (state,
- MultiplyAdd64 (state, instr, LSIGNED, LSCC),
- 0L);
- break;
- }
-#endif
- lhs = LHS;
- rhs = DPRegRHS;
- dest = rhs - lhs - !CFLAG;
-
- if ((rhs >= lhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, rhs, lhs, dest);
- ARMul_SubOverflow (state, rhs, lhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x10: /* TST reg and MRS CPSR and SWP word. */
- if (state->is_v5e)
- {
- if (BIT (4) == 0 && BIT (7) == 1)
- {
- /* ElSegundo SMLAxy insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (8, 11)];
- ARMword Rn = state->Reg[BITS (12, 15)];
-
- if (BIT (5))
- op1 >>= 16;
- if (BIT (6))
- op2 >>= 16;
- op1 &= 0xFFFF;
- op2 &= 0xFFFF;
- if (op1 & 0x8000)
- op1 -= 65536;
- if (op2 & 0x8000)
- op2 -= 65536;
- op1 *= op2;
-
- if (AddOverflow (op1, Rn, op1 + Rn))
- SETS;
- state->Reg[BITS (16, 19)] = op1 + Rn;
- break;
- }
-
- if (BITS (4, 11) == 5)
- {
- /* ElSegundo QADD insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (16, 19)];
- ARMword result = op1 + op2;
- if (AddOverflow (op1, op2, result))
- {
- result = POS (result) ? 0x80000000 : 0x7fffffff;
- SETS;
- }
- state->Reg[BITS (12, 15)] = result;
- break;
- }
- }
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, no write-back, down, pre indexed. */
- SHPREDOWN ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- if (BITS (4, 11) == 9)
- {
- /* SWP */
- UNDEF_SWPPC;
- temp = LHS;
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (VECTORACCESS (temp) || ADDREXCEPT (temp))
- {
- INTERNALABORT (temp);
- (void) ARMul_LoadWordN (state, temp);
- (void) ARMul_LoadWordN (state, temp);
- }
- else
-#endif
- dest = ARMul_SwapWord (state, temp, state->Reg[RHSReg]);
- if (temp & 3)
- DEST = ARMul_Align (state, temp, dest);
- else
- DEST = dest;
- if (state->abortSig || state->Aborted)
- TAKEABORT;
- }
- else if ((BITS (0, 11) == 0) && (LHSReg == 15))
- { /* MRS CPSR */
- UNDEF_MRSPC;
- DEST = ECC | EINT | EMODE;
- }
- else
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- UNDEF_Test;
- }
- break;
-
- case 0x11: /* TSTP reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- /* LDR register offset, no write-back, down, pre indexed. */
- LHPREDOWN ();
- /* Continue with remaining instruction decode. */
-#endif
- if (DESTReg == 15)
- {
- /* TSTP reg */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- rhs = DPRegRHS;
- temp = LHS & rhs;
- SETR15PSR (temp);
-#endif
- }
- else
- {
- /* TST reg */
- rhs = DPSRegRHS;
- dest = LHS & rhs;
- ARMul_NegZero (state, dest);
- }
- break;
-
- case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6). */
- if (state->is_v5)
- {
- if (BITS (4, 7) == 3)
- {
- /* BLX(2) */
- if (TFLAG)
- dest = (pc + 2) | 1;
- else
- dest = pc + 4;
-
- WriteR15Branch (state, state->Reg[RHSReg]);
- state->Reg[14] = dest;
- break;
- }
- }
-
- if (state->is_v5e)
- {
- if (BIT (4) == 0 && BIT (7) == 1
- && (BIT (5) == 0 || BITS (12, 15) == 0))
- {
- /* ElSegundo SMLAWy/SMULWy insn. */
- ARMdword op1 = state->Reg[BITS (0, 3)];
- ARMdword op2 = state->Reg[BITS (8, 11)];
- ARMdword result;
-
- if (BIT (6))
- op2 >>= 16;
- if (op1 & 0x80000000)
- op1 -= 1ULL << 32;
- op2 &= 0xFFFF;
- if (op2 & 0x8000)
- op2 -= 65536;
- result = (op1 * op2) >> 16;
-
- if (BIT (5) == 0)
- {
- ARMword Rn = state->Reg[BITS (12, 15)];
-
- if (AddOverflow (result, Rn, result + Rn))
- SETS;
- result += Rn;
- }
- state->Reg[BITS (16, 19)] = result;
- break;
- }
-
- if (BITS (4, 11) == 5)
- {
- /* ElSegundo QSUB insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (16, 19)];
- ARMword result = op1 - op2;
-
- if (SubOverflow (op1, op2, result))
- {
- result = POS (result) ? 0x80000000 : 0x7fffffff;
- SETS;
- }
-
- state->Reg[BITS (12, 15)] = result;
- break;
- }
- }
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, write-back, down, pre indexed. */
- SHPREDOWNWB ();
- break;
- }
- if (BITS (4, 27) == 0x12FFF1)
- {
- /* BX */
- WriteR15Branch (state, state->Reg[RHSReg]);
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- if (state->is_v5)
- {
- if (BITS (4, 7) == 0x7)
- {
- extern int SWI_vector_installed;
-
- /* Hardware is allowed to optionally override this
- instruction and treat it as a breakpoint. Since
- this is a simulator not hardware, we take the position
- that if a SWI vector was not installed, then an Abort
- vector was probably not installed either, and so
- normally this instruction would be ignored, even if an
- Abort is generated. This is a bad thing, since GDB
- uses this instruction for its breakpoints (at least in
- Thumb mode it does). So intercept the instruction here
- and generate a breakpoint SWI instead. */
- if (! SWI_vector_installed)
- ARMul_OSHandleSWI (state, SWI_Breakpoint);
- else
- {
- /* BKPT - normally this will cause an abort, but on the
- XScale we must check the DCSR. */
- XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, pc);
- if (!XScale_debug_moe (state, ARMul_CP14_R10_MOE_BT))
- break;
- }
-
- /* Force the next instruction to be refetched. */
- state->NextInstr = RESUME;
- break;
- }
- }
- if (DESTReg == 15)
- {
- /* MSR reg to CPSR. */
- UNDEF_MSRPC;
- temp = DPRegRHS;
-#ifdef MODET
- /* Don't allow TBIT to be set by MSR. */
- temp &= ~ TBIT;
-#endif
- ARMul_FixCPSR (state, instr, temp);
- }
-#ifdef MODE32
- else if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- else
- UNDEF_Test;
-
- break;
-
- case 0x13: /* TEQP reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- /* LDR register offset, write-back, down, pre indexed. */
- LHPREDOWNWB ();
- /* Continue with remaining instruction decode. */
-#endif
- if (DESTReg == 15)
- {
- /* TEQP reg */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- rhs = DPRegRHS;
- temp = LHS ^ rhs;
- SETR15PSR (temp);
-#endif
- }
- else
- {
- /* TEQ Reg. */
- rhs = DPSRegRHS;
- dest = LHS ^ rhs;
- ARMul_NegZero (state, dest);
- }
- break;
-
- case 0x14: /* CMP reg and MRS SPSR and SWP byte. */
- if (state->is_v5e)
- {
- if (BIT (4) == 0 && BIT (7) == 1)
- {
- /* ElSegundo SMLALxy insn. */
- ARMdword op1 = state->Reg[BITS (0, 3)];
- ARMdword op2 = state->Reg[BITS (8, 11)];
- ARMdword result;
-
- if (BIT (5))
- op1 >>= 16;
- if (BIT (6))
- op2 >>= 16;
- op1 &= 0xFFFF;
- if (op1 & 0x8000)
- op1 -= 65536;
- op2 &= 0xFFFF;
- if (op2 & 0x8000)
- op2 -= 65536;
-
- result = (ARMdword) state->Reg[BITS (16, 19)] << 32;
- result |= state->Reg[BITS (12, 15)];
- result += op1 * op2;
- state->Reg[BITS (12, 15)] = result;
- state->Reg[BITS (16, 19)] = result >> 32;
- break;
- }
-
- if (BITS (4, 11) == 5)
- {
- /* ElSegundo QDADD insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (16, 19)];
- ARMword op2d = op2 + op2;
- ARMword result;
-
- if (AddOverflow (op2, op2, op2d))
- {
- SETS;
- op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
- }
-
- result = op1 + op2d;
- if (AddOverflow (op1, op2d, result))
- {
- SETS;
- result = POS (result) ? 0x80000000 : 0x7fffffff;
- }
-
- state->Reg[BITS (12, 15)] = result;
- break;
- }
- }
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, no write-back, down, pre indexed. */
- SHPREDOWN ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- if (BITS (4, 11) == 9)
- {
- /* SWP */
- UNDEF_SWPPC;
- temp = LHS;
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (VECTORACCESS (temp) || ADDREXCEPT (temp))
- {
- INTERNALABORT (temp);
- (void) ARMul_LoadByte (state, temp);
- (void) ARMul_LoadByte (state, temp);
- }
- else
-#endif
- DEST = ARMul_SwapByte (state, temp, state->Reg[RHSReg]);
- if (state->abortSig || state->Aborted)
- TAKEABORT;
- }
- else if ((BITS (0, 11) == 0) && (LHSReg == 15))
- {
- /* MRS SPSR */
- UNDEF_MRSPC;
- DEST = GETSPSR (state->Bank);
- }
-#ifdef MODE32
- else if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- else
- UNDEF_Test;
-
- break;
-
- case 0x15: /* CMPP reg. */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- /* LDR immediate offset, no write-back, down, pre indexed. */
- LHPREDOWN ();
- /* Continue with remaining instruction decode. */
-#endif
- if (DESTReg == 15)
- {
- /* CMPP reg. */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- rhs = DPRegRHS;
- temp = LHS - rhs;
- SETR15PSR (temp);
-#endif
- }
- else
- {
- /* CMP reg. */
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs - rhs;
- ARMul_NegZero (state, dest);
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- }
- break;
-
- case 0x16: /* CMN reg and MSR reg to SPSR */
- if (state->is_v5e)
- {
- if (BIT (4) == 0 && BIT (7) == 1 && BITS (12, 15) == 0)
- {
- /* ElSegundo SMULxy insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (8, 11)];
-
- if (BIT (5))
- op1 >>= 16;
- if (BIT (6))
- op2 >>= 16;
- op1 &= 0xFFFF;
- op2 &= 0xFFFF;
- if (op1 & 0x8000)
- op1 -= 65536;
- if (op2 & 0x8000)
- op2 -= 65536;
-
- state->Reg[BITS (16, 19)] = op1 * op2;
- break;
- }
-
- if (BITS (4, 11) == 5)
- {
- /* ElSegundo QDSUB insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- ARMword op2 = state->Reg[BITS (16, 19)];
- ARMword op2d = op2 + op2;
- ARMword result;
-
- if (AddOverflow (op2, op2, op2d))
- {
- SETS;
- op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
- }
-
- result = op1 - op2d;
- if (SubOverflow (op1, op2d, result))
- {
- SETS;
- result = POS (result) ? 0x80000000 : 0x7fffffff;
- }
-
- state->Reg[BITS (12, 15)] = result;
- break;
- }
- }
-
- if (state->is_v5)
- {
- if (BITS (4, 11) == 0xF1 && BITS (16, 19) == 0xF)
- {
- /* ARM5 CLZ insn. */
- ARMword op1 = state->Reg[BITS (0, 3)];
- int result = 32;
-
- if (op1)
- for (result = 0; (op1 & 0x80000000) == 0; op1 <<= 1)
- result++;
-
- state->Reg[BITS (12, 15)] = result;
- break;
- }
- }
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, write-back, down, pre indexed. */
- SHPREDOWNWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- if (DESTReg == 15)
- {
- /* MSR */
- UNDEF_MSRPC;
- ARMul_FixSPSR (state, instr, DPRegRHS);
- }
- else
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- UNDEF_Test;
- }
- break;
-
- case 0x17: /* CMNP reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- /* LDR immediate offset, write-back, down, pre indexed. */
- LHPREDOWNWB ();
- /* Continue with remaining instruction decoding. */
-#endif
- if (DESTReg == 15)
- {
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- rhs = DPRegRHS;
- temp = LHS + rhs;
- SETR15PSR (temp);
-#endif
- break;
- }
- else
- {
- /* CMN reg. */
- lhs = LHS;
- rhs = DPRegRHS;
- dest = lhs + rhs;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- {
- /* Possible C,V,N to set. */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- }
- break;
-
- case 0x18: /* ORR reg */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, no write-back, up, pre indexed. */
- SHPREUP ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS | rhs;
- WRITEDEST (dest);
- break;
-
- case 0x19: /* ORRS reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- /* LDR register offset, no write-back, up, pre indexed. */
- LHPREUP ();
- /* Continue with remaining instruction decoding. */
-#endif
- rhs = DPSRegRHS;
- dest = LHS | rhs;
- WRITESDEST (dest);
- break;
-
- case 0x1a: /* MOV reg */
-#ifdef MODET
- if (BITS (4, 11) == 0xB)
- {
- /* STRH register offset, write-back, up, pre indexed. */
- SHPREUPWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- dest = DPRegRHS;
- WRITEDEST (dest);
- break;
-
- case 0x1b: /* MOVS reg */
-#ifdef MODET
- if ((BITS (4, 11) & 0xF9) == 0x9)
- /* LDR register offset, write-back, up, pre indexed. */
- LHPREUPWB ();
- /* Continue with remaining instruction decoding. */
-#endif
- dest = DPSRegRHS;
- WRITESDEST (dest);
- break;
-
- case 0x1c: /* BIC reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, no write-back, up, pre indexed. */
- SHPREUP ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- else if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- rhs = DPRegRHS;
- dest = LHS & ~rhs;
- WRITEDEST (dest);
- break;
-
- case 0x1d: /* BICS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- /* LDR immediate offset, no write-back, up, pre indexed. */
- LHPREUP ();
- /* Continue with instruction decoding. */
-#endif
- rhs = DPSRegRHS;
- dest = LHS & ~rhs;
- WRITESDEST (dest);
- break;
-
- case 0x1e: /* MVN reg */
-#ifdef MODET
- if (BITS (4, 7) == 0xB)
- {
- /* STRH immediate offset, write-back, up, pre indexed. */
- SHPREUPWB ();
- break;
- }
- if (BITS (4, 7) == 0xD)
- {
- Handle_Load_Double (state, instr);
- break;
- }
- if (BITS (4, 7) == 0xF)
- {
- Handle_Store_Double (state, instr);
- break;
- }
-#endif
- dest = ~DPRegRHS;
- WRITEDEST (dest);
- break;
-
- case 0x1f: /* MVNS reg */
-#ifdef MODET
- if ((BITS (4, 7) & 0x9) == 0x9)
- /* LDR immediate offset, write-back, up, pre indexed. */
- LHPREUPWB ();
- /* Continue instruction decoding. */
-#endif
- dest = ~DPSRegRHS;
- WRITESDEST (dest);
- break;
-
-
- /* Data Processing Immediate RHS Instructions. */
-
- case 0x20: /* AND immed */
- dest = LHS & DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x21: /* ANDS immed */
- DPSImmRHS;
- dest = LHS & rhs;
- WRITESDEST (dest);
- break;
-
- case 0x22: /* EOR immed */
- dest = LHS ^ DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x23: /* EORS immed */
- DPSImmRHS;
- dest = LHS ^ rhs;
- WRITESDEST (dest);
- break;
-
- case 0x24: /* SUB immed */
- dest = LHS - DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x25: /* SUBS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = lhs - rhs;
-
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x26: /* RSB immed */
- dest = DPImmRHS - LHS;
- WRITEDEST (dest);
- break;
-
- case 0x27: /* RSBS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = rhs - lhs;
-
- if ((rhs >= lhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, rhs, lhs, dest);
- ARMul_SubOverflow (state, rhs, lhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x28: /* ADD immed */
- dest = LHS + DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x29: /* ADDS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = lhs + rhs;
- ASSIGNZ (dest == 0);
-
- if ((lhs | rhs) >> 30)
- {
- /* Possible C,V,N to set. */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x2a: /* ADC immed */
- dest = LHS + DPImmRHS + CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x2b: /* ADCS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = lhs + rhs + CFLAG;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- {
- /* Possible C,V,N to set. */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x2c: /* SBC immed */
- dest = LHS - DPImmRHS - !CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x2d: /* SBCS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = lhs - rhs - !CFLAG;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x2e: /* RSC immed */
- dest = DPImmRHS - LHS - !CFLAG;
- WRITEDEST (dest);
- break;
-
- case 0x2f: /* RSCS immed */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = rhs - lhs - !CFLAG;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, rhs, lhs, dest);
- ARMul_SubOverflow (state, rhs, lhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- WRITESDEST (dest);
- break;
-
- case 0x30: /* MOVW immed */
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- dest = BITS (0, 11);
- dest |= (BITS (16, 19) << 12);
- WRITEDEST (dest);
- break;
-
- case 0x31: /* TSTP immed */
- if (DESTReg == 15)
- {
- /* TSTP immed. */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- temp = LHS & DPImmRHS;
- SETR15PSR (temp);
-#endif
- }
- else
- {
- /* TST immed. */
- DPSImmRHS;
- dest = LHS & rhs;
- ARMul_NegZero (state, dest);
- }
- break;
-
- case 0x32: /* TEQ immed and MSR immed to CPSR */
- if (DESTReg == 15)
- /* MSR immed to CPSR. */
- ARMul_FixCPSR (state, instr, DPImmRHS);
-#ifdef MODE32
- else if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- else
- UNDEF_Test;
- break;
-
- case 0x33: /* TEQP immed */
- if (DESTReg == 15)
- {
- /* TEQP immed. */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- temp = LHS ^ DPImmRHS;
- SETR15PSR (temp);
-#endif
- }
- else
- {
- DPSImmRHS; /* TEQ immed */
- dest = LHS ^ rhs;
- ARMul_NegZero (state, dest);
- }
- break;
-
- case 0x34: /* MOVT immed */
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- DEST &= 0xFFFF;
- dest = BITS (0, 11);
- dest |= (BITS (16, 19) << 12);
- DEST |= (dest << 16);
- break;
-
- case 0x35: /* CMPP immed */
- if (DESTReg == 15)
- {
- /* CMPP immed. */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- temp = LHS - DPImmRHS;
- SETR15PSR (temp);
-#endif
- break;
- }
- else
- {
- /* CMP immed. */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = lhs - rhs;
- ARMul_NegZero (state, dest);
-
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, dest);
- ARMul_SubOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- }
- break;
-
- case 0x36: /* CMN immed and MSR immed to SPSR */
- if (DESTReg == 15)
- ARMul_FixSPSR (state, instr, DPImmRHS);
-#ifdef MODE32
- else if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- else
- UNDEF_Test;
- break;
-
- case 0x37: /* CMNP immed. */
- if (DESTReg == 15)
- {
- /* CMNP immed. */
-#ifdef MODE32
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
-#else
- temp = LHS + DPImmRHS;
- SETR15PSR (temp);
-#endif
- break;
- }
- else
- {
- /* CMN immed. */
- lhs = LHS;
- rhs = DPImmRHS;
- dest = lhs + rhs;
- ASSIGNZ (dest == 0);
- if ((lhs | rhs) >> 30)
- {
- /* Possible C,V,N to set. */
- ASSIGNN (NEG (dest));
- ARMul_AddCarry (state, lhs, rhs, dest);
- ARMul_AddOverflow (state, lhs, rhs, dest);
- }
- else
- {
- CLEARN;
- CLEARC;
- CLEARV;
- }
- }
- break;
-
- case 0x38: /* ORR immed. */
- dest = LHS | DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x39: /* ORRS immed. */
- DPSImmRHS;
- dest = LHS | rhs;
- WRITESDEST (dest);
- break;
-
- case 0x3a: /* MOV immed. */
- dest = DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x3b: /* MOVS immed. */
- DPSImmRHS;
- WRITESDEST (rhs);
- break;
-
- case 0x3c: /* BIC immed. */
- dest = LHS & ~DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x3d: /* BICS immed. */
- DPSImmRHS;
- dest = LHS & ~rhs;
- WRITESDEST (dest);
- break;
-
- case 0x3e: /* MVN immed. */
- dest = ~DPImmRHS;
- WRITEDEST (dest);
- break;
-
- case 0x3f: /* MVNS immed. */
- DPSImmRHS;
- WRITESDEST (~rhs);
- break;
-
-
- /* Single Data Transfer Immediate RHS Instructions. */
-
- case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */
- lhs = LHS;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs - LSImmRHS;
- break;
-
- case 0x41: /* Load Word, No WriteBack, Post Dec, Immed. */
- lhs = LHS;
- if (LoadWord (state, instr, lhs))
- LSBase = lhs - LSImmRHS;
- break;
-
- case 0x42: /* Store Word, WriteBack, Post Dec, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- temp = lhs - LSImmRHS;
- state->NtransSig = LOW;
- if (StoreWord (state, instr, lhs))
- LSBase = temp;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x43: /* Load Word, WriteBack, Post Dec, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (LoadWord (state, instr, lhs))
- LSBase = lhs - LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed. */
- lhs = LHS;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs - LSImmRHS;
- break;
-
- case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed. */
- lhs = LHS;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs - LSImmRHS;
- break;
-
- case 0x46: /* Store Byte, WriteBack, Post Dec, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs - LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x47: /* Load Byte, WriteBack, Post Dec, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs - LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x48: /* Store Word, No WriteBack, Post Inc, Immed. */
- lhs = LHS;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- break;
-
- case 0x49: /* Load Word, No WriteBack, Post Inc, Immed. */
- lhs = LHS;
- if (LoadWord (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- break;
-
- case 0x4a: /* Store Word, WriteBack, Post Inc, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x4b: /* Load Word, WriteBack, Post Inc, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (LoadWord (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed. */
- lhs = LHS;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- break;
-
- case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed. */
- lhs = LHS;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs + LSImmRHS;
- break;
-
- case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs + LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = lhs + LSImmRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
-
- case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */
- (void) StoreWord (state, instr, LHS - LSImmRHS);
- break;
-
- case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed. */
- (void) LoadWord (state, instr, LHS - LSImmRHS);
- break;
-
- case 0x52: /* Store Word, WriteBack, Pre Dec, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS - LSImmRHS;
- if (StoreWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x53: /* Load Word, WriteBack, Pre Dec, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS - LSImmRHS;
- if (LoadWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed. */
- (void) StoreByte (state, instr, LHS - LSImmRHS);
- break;
-
- case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed. */
- (void) LoadByte (state, instr, LHS - LSImmRHS, LUNSIGNED);
- break;
-
- case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS - LSImmRHS;
- if (StoreByte (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS - LSImmRHS;
- if (LoadByte (state, instr, temp, LUNSIGNED))
- LSBase = temp;
- break;
-
- case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed. */
- (void) StoreWord (state, instr, LHS + LSImmRHS);
- break;
-
- case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed. */
- (void) LoadWord (state, instr, LHS + LSImmRHS);
- break;
-
- case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS + LSImmRHS;
- if (StoreWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS + LSImmRHS;
- if (LoadWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed. */
- (void) StoreByte (state, instr, LHS + LSImmRHS);
- break;
-
- case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed. */
- (void) LoadByte (state, instr, LHS + LSImmRHS, LUNSIGNED);
- break;
-
- case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS + LSImmRHS;
- if (StoreByte (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed. */
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- temp = LHS + LSImmRHS;
- if (LoadByte (state, instr, temp, LUNSIGNED))
- LSBase = temp;
- break;
-
-
- /* Single Data Transfer Register RHS Instructions. */
-
- case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
- break;
-
- case 0x61: /* Load Word, No WriteBack, Post Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs - LSRegRHS;
- if (LoadWord (state, instr, lhs))
- LSBase = temp;
- break;
-
- case 0x62: /* Store Word, WriteBack, Post Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x63: /* Load Word, WriteBack, Post Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs - LSRegRHS;
- state->NtransSig = LOW;
- if (LoadWord (state, instr, lhs))
- LSBase = temp;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
- break;
-
- case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs - LSRegRHS;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = temp;
- break;
-
- case 0x66: /* Store Byte, WriteBack, Post Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs - LSRegRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x67: /* Load Byte, WriteBack, Post Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs - LSRegRHS;
- state->NtransSig = LOW;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = temp;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
- break;
-
- case 0x69: /* Load Word, No WriteBack, Post Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs + LSRegRHS;
- if (LoadWord (state, instr, lhs))
- LSBase = temp;
- break;
-
- case 0x6a: /* Store Word, WriteBack, Post Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreWord (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x6b: /* Load Word, WriteBack, Post Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs + LSRegRHS;
- state->NtransSig = LOW;
- if (LoadWord (state, instr, lhs))
- LSBase = temp;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
- break;
-
- case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs + LSRegRHS;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = temp;
- break;
-
- case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- state->NtransSig = LOW;
- if (StoreByte (state, instr, lhs))
- LSBase = lhs + LSRegRHS;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
- case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- lhs = LHS;
- temp = lhs + LSRegRHS;
- state->NtransSig = LOW;
- if (LoadByte (state, instr, lhs, LUNSIGNED))
- LSBase = temp;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- break;
-
-
- case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) StoreWord (state, instr, LHS - LSRegRHS);
- break;
-
- case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) LoadWord (state, instr, LHS - LSRegRHS);
- break;
-
- case 0x72: /* Store Word, WriteBack, Pre Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS - LSRegRHS;
- if (StoreWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x73: /* Load Word, WriteBack, Pre Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS - LSRegRHS;
- if (LoadWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) StoreByte (state, instr, LHS - LSRegRHS);
- break;
-
- case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) LoadByte (state, instr, LHS - LSRegRHS, LUNSIGNED);
- break;
-
- case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS - LSRegRHS;
- if (StoreByte (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS - LSRegRHS;
- if (LoadByte (state, instr, temp, LUNSIGNED))
- LSBase = temp;
- break;
-
- case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) StoreWord (state, instr, LHS + LSRegRHS);
- break;
-
- case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) LoadWord (state, instr, LHS + LSRegRHS);
- break;
-
- case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS + LSRegRHS;
- if (StoreWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS + LSRegRHS;
- if (LoadWord (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) StoreByte (state, instr, LHS + LSRegRHS);
- break;
-
- case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- (void) LoadByte (state, instr, LHS + LSRegRHS, LUNSIGNED);
- break;
-
- case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg. */
- if (BIT (4))
- {
-#ifdef MODE32
- if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS + LSRegRHS;
- if (StoreByte (state, instr, temp))
- LSBase = temp;
- break;
-
- case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg. */
- if (BIT (4))
- {
- /* Check for the special breakpoint opcode.
- This value should correspond to the value defined
- as ARM_BE_BREAKPOINT in gdb/arm/tm-arm.h. */
- if (BITS (0, 19) == 0xfdefe)
- {
- if (!ARMul_OSHandleSWI (state, SWI_Breakpoint))
- ARMul_Abort (state, ARMul_SWIV);
- }
-#ifdef MODE32
- else if (state->is_v6
- && handle_v6_insn (state, instr))
- break;
-#endif
- else
- ARMul_UndefInstr (state, instr);
- break;
- }
- UNDEF_LSRBaseEQOffWb;
- UNDEF_LSRBaseEQDestWb;
- UNDEF_LSRPCBaseWb;
- UNDEF_LSRPCOffWb;
- temp = LHS + LSRegRHS;
- if (LoadByte (state, instr, temp, LUNSIGNED))
- LSBase = temp;
- break;
-
-
- /* Multiple Data Transfer Instructions. */
-
- case 0x80: /* Store, No WriteBack, Post Dec. */
- STOREMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
- break;
-
- case 0x81: /* Load, No WriteBack, Post Dec. */
- LOADMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
- break;
-
- case 0x82: /* Store, WriteBack, Post Dec. */
- temp = LSBase - LSMNumRegs;
- STOREMULT (instr, temp + 4L, temp);
- break;
-
- case 0x83: /* Load, WriteBack, Post Dec. */
- temp = LSBase - LSMNumRegs;
- LOADMULT (instr, temp + 4L, temp);
- break;
-
- case 0x84: /* Store, Flags, No WriteBack, Post Dec. */
- STORESMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
- break;
-
- case 0x85: /* Load, Flags, No WriteBack, Post Dec. */
- LOADSMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
- break;
-
- case 0x86: /* Store, Flags, WriteBack, Post Dec. */
- temp = LSBase - LSMNumRegs;
- STORESMULT (instr, temp + 4L, temp);
- break;
-
- case 0x87: /* Load, Flags, WriteBack, Post Dec. */
- temp = LSBase - LSMNumRegs;
- LOADSMULT (instr, temp + 4L, temp);
- break;
-
- case 0x88: /* Store, No WriteBack, Post Inc. */
- STOREMULT (instr, LSBase, 0L);
- break;
-
- case 0x89: /* Load, No WriteBack, Post Inc. */
- LOADMULT (instr, LSBase, 0L);
- break;
-
- case 0x8a: /* Store, WriteBack, Post Inc. */
- temp = LSBase;
- STOREMULT (instr, temp, temp + LSMNumRegs);
- break;
-
- case 0x8b: /* Load, WriteBack, Post Inc. */
- temp = LSBase;
- LOADMULT (instr, temp, temp + LSMNumRegs);
- break;
-
- case 0x8c: /* Store, Flags, No WriteBack, Post Inc. */
- STORESMULT (instr, LSBase, 0L);
- break;
-
- case 0x8d: /* Load, Flags, No WriteBack, Post Inc. */
- LOADSMULT (instr, LSBase, 0L);
- break;
-
- case 0x8e: /* Store, Flags, WriteBack, Post Inc. */
- temp = LSBase;
- STORESMULT (instr, temp, temp + LSMNumRegs);
- break;
-
- case 0x8f: /* Load, Flags, WriteBack, Post Inc. */
- temp = LSBase;
- LOADSMULT (instr, temp, temp + LSMNumRegs);
- break;
-
- case 0x90: /* Store, No WriteBack, Pre Dec. */
- STOREMULT (instr, LSBase - LSMNumRegs, 0L);
- break;
-
- case 0x91: /* Load, No WriteBack, Pre Dec. */
- LOADMULT (instr, LSBase - LSMNumRegs, 0L);
- break;
-
- case 0x92: /* Store, WriteBack, Pre Dec. */
- temp = LSBase - LSMNumRegs;
- STOREMULT (instr, temp, temp);
- break;
-
- case 0x93: /* Load, WriteBack, Pre Dec. */
- temp = LSBase - LSMNumRegs;
- LOADMULT (instr, temp, temp);
- break;
-
- case 0x94: /* Store, Flags, No WriteBack, Pre Dec. */
- STORESMULT (instr, LSBase - LSMNumRegs, 0L);
- break;
-
- case 0x95: /* Load, Flags, No WriteBack, Pre Dec. */
- LOADSMULT (instr, LSBase - LSMNumRegs, 0L);
- break;
-
- case 0x96: /* Store, Flags, WriteBack, Pre Dec. */
- temp = LSBase - LSMNumRegs;
- STORESMULT (instr, temp, temp);
- break;
-
- case 0x97: /* Load, Flags, WriteBack, Pre Dec. */
- temp = LSBase - LSMNumRegs;
- LOADSMULT (instr, temp, temp);
- break;
-
- case 0x98: /* Store, No WriteBack, Pre Inc. */
- STOREMULT (instr, LSBase + 4L, 0L);
- break;
-
- case 0x99: /* Load, No WriteBack, Pre Inc. */
- LOADMULT (instr, LSBase + 4L, 0L);
- break;
-
- case 0x9a: /* Store, WriteBack, Pre Inc. */
- temp = LSBase;
- STOREMULT (instr, temp + 4L, temp + LSMNumRegs);
- break;
-
- case 0x9b: /* Load, WriteBack, Pre Inc. */
- temp = LSBase;
- LOADMULT (instr, temp + 4L, temp + LSMNumRegs);
- break;
-
- case 0x9c: /* Store, Flags, No WriteBack, Pre Inc. */
- STORESMULT (instr, LSBase + 4L, 0L);
- break;
-
- case 0x9d: /* Load, Flags, No WriteBack, Pre Inc. */
- LOADSMULT (instr, LSBase + 4L, 0L);
- break;
-
- case 0x9e: /* Store, Flags, WriteBack, Pre Inc. */
- temp = LSBase;
- STORESMULT (instr, temp + 4L, temp + LSMNumRegs);
- break;
-
- case 0x9f: /* Load, Flags, WriteBack, Pre Inc. */
- temp = LSBase;
- LOADSMULT (instr, temp + 4L, temp + LSMNumRegs);
- break;
-
-
- /* Branch forward. */
- case 0xa0:
- case 0xa1:
- case 0xa2:
- case 0xa3:
- case 0xa4:
- case 0xa5:
- case 0xa6:
- case 0xa7:
- state->Reg[15] = pc + 8 + POSBRANCH;
- FLUSHPIPE;
- break;
-
-
- /* Branch backward. */
- case 0xa8:
- case 0xa9:
- case 0xaa:
- case 0xab:
- case 0xac:
- case 0xad:
- case 0xae:
- case 0xaf:
- state->Reg[15] = pc + 8 + NEGBRANCH;
- FLUSHPIPE;
- break;
-
- /* Branch and Link forward. */
- case 0xb0:
- case 0xb1:
- case 0xb2:
- case 0xb3:
- case 0xb4:
- case 0xb5:
- case 0xb6:
- case 0xb7:
- /* Put PC into Link. */
-#ifdef MODE32
- state->Reg[14] = pc + 4;
-#else
- state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE;
-#endif
- state->Reg[15] = pc + 8 + POSBRANCH;
- FLUSHPIPE;
- if (trace_funcs)
- fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
- break;
-
- /* Branch and Link backward. */
- case 0xb8:
- case 0xb9:
- case 0xba:
- case 0xbb:
- case 0xbc:
- case 0xbd:
- case 0xbe:
- case 0xbf:
- /* Put PC into Link. */
-#ifdef MODE32
- state->Reg[14] = pc + 4;
-#else
- state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE;
-#endif
- state->Reg[15] = pc + 8 + NEGBRANCH;
- FLUSHPIPE;
- if (trace_funcs)
- fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
- break;
-
- /* Co-Processor Data Transfers. */
- case 0xc4:
- if (state->is_v5)
- {
- if (CPNum == 10 || CPNum == 11)
- handle_VFP_move (state, instr);
- /* Reading from R15 is UNPREDICTABLE. */
- else if (BITS (12, 15) == 15 || BITS (16, 19) == 15)
- ARMul_UndefInstr (state, instr);
- /* Is access to coprocessor 0 allowed ? */
- else if (! CP_ACCESS_ALLOWED (state, CPNum))
- ARMul_UndefInstr (state, instr);
- /* Special treatment for XScale coprocessors. */
- else if (state->is_XScale)
- {
- /* Only opcode 0 is supported. */
- if (BITS (4, 7) != 0x00)
- ARMul_UndefInstr (state, instr);
- /* Only coporcessor 0 is supported. */
- else if (CPNum != 0x00)
- ARMul_UndefInstr (state, instr);
- /* Only accumulator 0 is supported. */
- else if (BITS (0, 3) != 0x00)
- ARMul_UndefInstr (state, instr);
- else
- {
- /* XScale MAR insn. Move two registers into accumulator. */
- state->Accumulator = state->Reg[BITS (12, 15)];
- state->Accumulator += (ARMdword) state->Reg[BITS (16, 19)] << 32;
- }
- }
- else
- /* FIXME: Not sure what to do for other v5 processors. */
- ARMul_UndefInstr (state, instr);
- break;
- }
- ATTRIBUTE_FALLTHROUGH;
-
- case 0xc0: /* Store , No WriteBack , Post Dec. */
- ARMul_STC (state, instr, LHS);
- break;
-
- case 0xc5:
- if (state->is_v5)
- {
- if (CPNum == 10 || CPNum == 11)
- handle_VFP_move (state, instr);
- /* Writes to R15 are UNPREDICATABLE. */
- else if (DESTReg == 15 || LHSReg == 15)
- ARMul_UndefInstr (state, instr);
- /* Is access to the coprocessor allowed ? */
- else if (! CP_ACCESS_ALLOWED (state, CPNum))
- ARMul_UndefInstr (state, instr);
- /* Special handling for XScale coprcoessors. */
- else if (state->is_XScale)
- {
- /* Only opcode 0 is supported. */
- if (BITS (4, 7) != 0x00)
- ARMul_UndefInstr (state, instr);
- /* Only coprocessor 0 is supported. */
- else if (CPNum != 0x00)
- ARMul_UndefInstr (state, instr);
- /* Only accumulator 0 is supported. */
- else if (BITS (0, 3) != 0x00)
- ARMul_UndefInstr (state, instr);
- else
- {
- /* XScale MRA insn. Move accumulator into two registers. */
- ARMword t1 = (state->Accumulator >> 32) & 255;
-
- if (t1 & 128)
- t1 -= 256;
-
- state->Reg[BITS (12, 15)] = state->Accumulator;
- state->Reg[BITS (16, 19)] = t1;
- break;
- }
- }
- else
- /* FIXME: Not sure what to do for other v5 processors. */
- ARMul_UndefInstr (state, instr);
- break;
- }
- ATTRIBUTE_FALLTHROUGH;
-
- case 0xc1: /* Load , No WriteBack , Post Dec. */
- ARMul_LDC (state, instr, LHS);
- break;
-
- case 0xc2:
- case 0xc6: /* Store , WriteBack , Post Dec. */
- lhs = LHS;
- state->Base = lhs - LSCOff;
- ARMul_STC (state, instr, lhs);
- break;
-
- case 0xc3:
- case 0xc7: /* Load , WriteBack , Post Dec. */
- lhs = LHS;
- state->Base = lhs - LSCOff;
- ARMul_LDC (state, instr, lhs);
- break;
-
- case 0xc8:
- case 0xcc: /* Store , No WriteBack , Post Inc. */
- ARMul_STC (state, instr, LHS);
- break;
-
- case 0xc9:
- case 0xcd: /* Load , No WriteBack , Post Inc. */
- ARMul_LDC (state, instr, LHS);
- break;
-
- case 0xca:
- case 0xce: /* Store , WriteBack , Post Inc. */
- lhs = LHS;
- state->Base = lhs + LSCOff;
- ARMul_STC (state, instr, LHS);
- break;
-
- case 0xcb:
- case 0xcf: /* Load , WriteBack , Post Inc. */
- lhs = LHS;
- state->Base = lhs + LSCOff;
- ARMul_LDC (state, instr, LHS);
- break;
-
- case 0xd0:
- case 0xd4: /* Store , No WriteBack , Pre Dec. */
- ARMul_STC (state, instr, LHS - LSCOff);
- break;
-
- case 0xd1:
- case 0xd5: /* Load , No WriteBack , Pre Dec. */
- ARMul_LDC (state, instr, LHS - LSCOff);
- break;
-
- case 0xd2:
- case 0xd6: /* Store , WriteBack , Pre Dec. */
- lhs = LHS - LSCOff;
- state->Base = lhs;
- ARMul_STC (state, instr, lhs);
- break;
-
- case 0xd3:
- case 0xd7: /* Load , WriteBack , Pre Dec. */
- lhs = LHS - LSCOff;
- state->Base = lhs;
- ARMul_LDC (state, instr, lhs);
- break;
-
- case 0xd8:
- case 0xdc: /* Store , No WriteBack , Pre Inc. */
- ARMul_STC (state, instr, LHS + LSCOff);
- break;
-
- case 0xd9:
- case 0xdd: /* Load , No WriteBack , Pre Inc. */
- ARMul_LDC (state, instr, LHS + LSCOff);
- break;
-
- case 0xda:
- case 0xde: /* Store , WriteBack , Pre Inc. */
- lhs = LHS + LSCOff;
- state->Base = lhs;
- ARMul_STC (state, instr, lhs);
- break;
-
- case 0xdb:
- case 0xdf: /* Load , WriteBack , Pre Inc. */
- lhs = LHS + LSCOff;
- state->Base = lhs;
- ARMul_LDC (state, instr, lhs);
- break;
-
-
- /* Co-Processor Register Transfers (MCR) and Data Ops. */
-
- case 0xe2:
- if (! CP_ACCESS_ALLOWED (state, CPNum))
- {
- ARMul_UndefInstr (state, instr);
- break;
- }
- if (state->is_XScale)
- switch (BITS (18, 19))
- {
- case 0x0:
- if (BITS (4, 11) == 1 && BITS (16, 17) == 0)
- {
- /* XScale MIA instruction. Signed multiplication of
- two 32 bit values and addition to 40 bit accumulator. */
- ARMsdword Rm = state->Reg[MULLHSReg];
- ARMsdword Rs = state->Reg[MULACCReg];
-
- if (Rm & (1 << 31))
- Rm -= 1ULL << 32;
- if (Rs & (1 << 31))
- Rs -= 1ULL << 32;
- state->Accumulator += Rm * Rs;
- goto donext;
- }
- break;
-
- case 0x2:
- if (BITS (4, 11) == 1 && BITS (16, 17) == 0)
- {
- /* XScale MIAPH instruction. */
- ARMword t1 = state->Reg[MULLHSReg] >> 16;
- ARMword t2 = state->Reg[MULACCReg] >> 16;
- ARMword t3 = state->Reg[MULLHSReg] & 0xffff;
- ARMword t4 = state->Reg[MULACCReg] & 0xffff;
- ARMsdword t5;
-
- if (t1 & (1 << 15))
- t1 -= 1 << 16;
- if (t2 & (1 << 15))
- t2 -= 1 << 16;
- if (t3 & (1 << 15))
- t3 -= 1 << 16;
- if (t4 & (1 << 15))
- t4 -= 1 << 16;
- t1 *= t2;
- t5 = t1;
- if (t5 & (1 << 31))
- t5 -= 1ULL << 32;
- state->Accumulator += t5;
- t3 *= t4;
- t5 = t3;
- if (t5 & (1 << 31))
- t5 -= 1ULL << 32;
- state->Accumulator += t5;
- goto donext;
- }
- break;
-
- case 0x3:
- if (BITS (4, 11) == 1)
- {
- /* XScale MIAxy instruction. */
- ARMword t1;
- ARMword t2;
- ARMsdword t5;
-
- if (BIT (17))
- t1 = state->Reg[MULLHSReg] >> 16;
- else
- t1 = state->Reg[MULLHSReg] & 0xffff;
-
- if (BIT (16))
- t2 = state->Reg[MULACCReg] >> 16;
- else
- t2 = state->Reg[MULACCReg] & 0xffff;
-
- if (t1 & (1 << 15))
- t1 -= 1 << 16;
- if (t2 & (1 << 15))
- t2 -= 1 << 16;
- t1 *= t2;
- t5 = t1;
- if (t5 & (1 << 31))
- t5 -= 1ULL << 32;
- state->Accumulator += t5;
- goto donext;
- }
- break;
-
- default:
- break;
- }
- ATTRIBUTE_FALLTHROUGH;
-
- case 0xe0:
- case 0xe4:
- case 0xe6:
- case 0xe8:
- case 0xea:
- case 0xec:
- case 0xee:
- if (BIT (4))
- {
- if (CPNum == 10 || CPNum == 11)
- handle_VFP_move (state, instr);
- /* MCR. */
- else if (DESTReg == 15)
- {
- UNDEF_MCRPC;
-#ifdef MODE32
- ARMul_MCR (state, instr, state->Reg[15] + isize);
-#else
- ARMul_MCR (state, instr, ECC | ER15INT | EMODE |
- ((state->Reg[15] + isize) & R15PCBITS));
-#endif
- }
- else
- ARMul_MCR (state, instr, DEST);
- }
- else
- /* CDP Part 1. */
- ARMul_CDP (state, instr);
- break;
-
-
- /* Co-Processor Register Transfers (MRC) and Data Ops. */
- case 0xe1:
- case 0xe3:
- case 0xe5:
- case 0xe7:
- case 0xe9:
- case 0xeb:
- case 0xed:
- case 0xef:
- if (BIT (4))
- {
- if (CPNum == 10 || CPNum == 11)
- {
- switch (BITS (20, 27))
- {
- case 0xEF:
- if (BITS (16, 19) == 0x1
- && BITS (0, 11) == 0xA10)
- {
- /* VMRS */
- if (DESTReg == 15)
- {
- ARMul_SetCPSR (state, (state->FPSCR & 0xF0000000)
- | (ARMul_GetCPSR (state) & 0x0FFFFFFF));
-
- if (trace)
- fprintf (stderr, " VFP: VMRS: set flags to %c%c%c%c\n",
- ARMul_GetCPSR (state) & NBIT ? 'N' : '-',
- ARMul_GetCPSR (state) & ZBIT ? 'Z' : '-',
- ARMul_GetCPSR (state) & CBIT ? 'C' : '-',
- ARMul_GetCPSR (state) & VBIT ? 'V' : '-');
- }
- else
- {
- state->Reg[DESTReg] = state->FPSCR;
-
- if (trace)
- fprintf (stderr, " VFP: VMRS: r%d = %x\n", DESTReg, state->Reg[DESTReg]);
- }
- }
- else
- fprintf (stderr, "SIM: VFP: Unimplemented: Compare op\n");
- break;
-
- case 0xE0:
- case 0xE1:
- /* VMOV reg <-> single precision. */
- if (BITS (0,6) != 0x10 || BITS (8,11) != 0xA)
- fprintf (stderr, "SIM: VFP: Unimplemented: move op\n");
- else if (BIT (20))
- state->Reg[BITS (12, 15)] = VFP_uword (BITS (16, 19) << 1 | BIT (7));
- else
- VFP_uword (BITS (16, 19) << 1 | BIT (7)) = state->Reg[BITS (12, 15)];
- break;
-
- default:
- fprintf (stderr, "SIM: VFP: Unimplemented: CDP op\n");
- break;
- }
- }
- else
- {
- /* MRC */
- temp = ARMul_MRC (state, instr);
- if (DESTReg == 15)
- {
- ASSIGNN ((temp & NBIT) != 0);
- ASSIGNZ ((temp & ZBIT) != 0);
- ASSIGNC ((temp & CBIT) != 0);
- ASSIGNV ((temp & VBIT) != 0);
- }
- else
- DEST = temp;
- }
- }
- else
- /* CDP Part 2. */
- ARMul_CDP (state, instr);
- break;
-
-
- /* SWI instruction. */
- case 0xf0:
- case 0xf1:
- case 0xf2:
- case 0xf3:
- case 0xf4:
- case 0xf5:
- case 0xf6:
- case 0xf7:
- case 0xf8:
- case 0xf9:
- case 0xfa:
- case 0xfb:
- case 0xfc:
- case 0xfd:
- case 0xfe:
- case 0xff:
- if (instr == ARMul_ABORTWORD && state->AbortAddr == pc)
- {
- /* A prefetch abort. */
- XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, pc);
- ARMul_Abort (state, ARMul_PrefetchAbortV);
- break;
- }
-
- if (!ARMul_OSHandleSWI (state, BITS (0, 23)))
- ARMul_Abort (state, ARMul_SWIV);
-
- break;
- }
- }
-
-#ifdef MODET
- donext:
-#endif
-
- if (state->Emulate == ONCE)
- state->Emulate = STOP;
- /* If we have changed mode, allow the PC to advance before stopping. */
- else if (state->Emulate == CHANGEMODE)
- continue;
- else if (state->Emulate != RUN)
- break;
- }
- while (!stop_simulator);
-
- state->decoded = decoded;
- state->loaded = loaded;
- state->pc = pc;
-
- return pc;
-}
-
-/* This routine evaluates most Data Processing register RHS's with the S
- bit clear. It is intended to be called from the macro DPRegRHS, which
- filters the common case of an unshifted register with in line code. */
-
-static ARMword
-GetDPRegRHS (ARMul_State * state, ARMword instr)
-{
- ARMword shamt, base;
-
- base = RHSReg;
- if (BIT (4))
- {
- /* Shift amount in a register. */
- UNDEF_Shift;
- INCPC;
-#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE;
- else
-#endif
- base = state->Reg[base];
- ARMul_Icycles (state, 1, 0L);
- shamt = state->Reg[BITS (8, 11)] & 0xff;
- switch ((int) BITS (5, 6))
- {
- case LSL:
- if (shamt == 0)
- return (base);
- else if (shamt >= 32)
- return (0);
- else
- return (base << shamt);
- case LSR:
- if (shamt == 0)
- return (base);
- else if (shamt >= 32)
- return (0);
- else
- return (base >> shamt);
- case ASR:
- if (shamt == 0)
- return (base);
- else if (shamt >= 32)
- return ((ARMword) ((ARMsword) base >> 31L));
- else
- return ((ARMword) ((ARMsword) base >> (int) shamt));
- case ROR:
- shamt &= 0x1f;
- if (shamt == 0)
- return (base);
- else
- return ((base << (32 - shamt)) | (base >> shamt));
- }
- }
- else
- {
- /* Shift amount is a constant. */
-#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE;
- else
-#endif
- base = state->Reg[base];
- shamt = BITS (7, 11);
- switch ((int) BITS (5, 6))
- {
- case LSL:
- return (base << shamt);
- case LSR:
- if (shamt == 0)
- return (0);
- else
- return (base >> shamt);
- case ASR:
- if (shamt == 0)
- return ((ARMword) ((ARMsword) base >> 31L));
- else
- return ((ARMword) ((ARMsword) base >> (int) shamt));
- case ROR:
- if (shamt == 0)
- /* It's an RRX. */
- return ((base >> 1) | (CFLAG << 31));
- else
- return ((base << (32 - shamt)) | (base >> shamt));
- }
- }
-
- return 0;
-}
-
-/* This routine evaluates most Logical Data Processing register RHS's
- with the S bit set. It is intended to be called from the macro
- DPSRegRHS, which filters the common case of an unshifted register
- with in line code. */
-
-static ARMword
-GetDPSRegRHS (ARMul_State * state, ARMword instr)
-{
- ARMword shamt, base;
-
- base = RHSReg;
- if (BIT (4))
- {
- /* Shift amount in a register. */
- UNDEF_Shift;
- INCPC;
-#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE;
- else
-#endif
- base = state->Reg[base];
- ARMul_Icycles (state, 1, 0L);
- shamt = state->Reg[BITS (8, 11)] & 0xff;
- switch ((int) BITS (5, 6))
- {
- case LSL:
- if (shamt == 0)
- return (base);
- else if (shamt == 32)
- {
- ASSIGNC (base & 1);
- return (0);
- }
- else if (shamt > 32)
- {
- CLEARC;
- return (0);
- }
- else
- {
- ASSIGNC ((base >> (32 - shamt)) & 1);
- return (base << shamt);
- }
- case LSR:
- if (shamt == 0)
- return (base);
- else if (shamt == 32)
- {
- ASSIGNC (base >> 31);
- return (0);
- }
- else if (shamt > 32)
- {
- CLEARC;
- return (0);
- }
- else
- {
- ASSIGNC ((base >> (shamt - 1)) & 1);
- return (base >> shamt);
- }
- case ASR:
- if (shamt == 0)
- return (base);
- else if (shamt >= 32)
- {
- ASSIGNC (base >> 31L);
- return ((ARMword) ((ARMsword) base >> 31L));
- }
- else
- {
- ASSIGNC ((ARMword) ((ARMsword) base >> (int) (shamt - 1)) & 1);
- return ((ARMword) ((ARMsword) base >> (int) shamt));
- }
- case ROR:
- if (shamt == 0)
- return (base);
- shamt &= 0x1f;
- if (shamt == 0)
- {
- ASSIGNC (base >> 31);
- return (base);
- }
- else
- {
- ASSIGNC ((base >> (shamt - 1)) & 1);
- return ((base << (32 - shamt)) | (base >> shamt));
- }
- }
- }
- else
- {
- /* Shift amount is a constant. */
-#ifndef MODE32
- if (base == 15)
- base = ECC | ER15INT | R15PC | EMODE;
- else
-#endif
- base = state->Reg[base];
- shamt = BITS (7, 11);
-
- switch ((int) BITS (5, 6))
- {
- case LSL:
- ASSIGNC ((base >> (32 - shamt)) & 1);
- return (base << shamt);
- case LSR:
- if (shamt == 0)
- {
- ASSIGNC (base >> 31);
- return (0);
- }
- else
- {
- ASSIGNC ((base >> (shamt - 1)) & 1);
- return (base >> shamt);
- }
- case ASR:
- if (shamt == 0)
- {
- ASSIGNC (base >> 31L);
- return ((ARMword) ((ARMsword) base >> 31L));
- }
- else
- {
- ASSIGNC ((ARMword) ((ARMsword) base >> (int) (shamt - 1)) & 1);
- return ((ARMword) ((ARMsword) base >> (int) shamt));
- }
- case ROR:
- if (shamt == 0)
- {
- /* It's an RRX. */
- shamt = CFLAG;
- ASSIGNC (base & 1);
- return ((base >> 1) | (shamt << 31));
- }
- else
- {
- ASSIGNC ((base >> (shamt - 1)) & 1);
- return ((base << (32 - shamt)) | (base >> shamt));
- }
- }
- }
-
- return 0;
-}
-
-/* This routine handles writes to register 15 when the S bit is not set. */
-
-static void
-WriteR15 (ARMul_State * state, ARMword src)
-{
- /* The ARM documentation states that the two least significant bits
- are discarded when setting PC, except in the cases handled by
- WriteR15Branch() below. It's probably an oversight: in THUMB
- mode, the second least significant bit should probably not be
- discarded. */
-#ifdef MODET
- if (TFLAG)
- src &= 0xfffffffe;
- else
-#endif
- src &= 0xfffffffc;
-
-#ifdef MODE32
- state->Reg[15] = src & PCBITS;
-#else
- state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE;
- ARMul_R15Altered (state);
-#endif
-
- FLUSHPIPE;
- if (trace_funcs)
- fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
-}
-
-/* This routine handles writes to register 15 when the S bit is set. */
-
-static void
-WriteSR15 (ARMul_State * state, ARMword src)
-{
-#ifdef MODE32
- if (state->Bank > 0)
- {
- state->Cpsr = state->Spsr[state->Bank];
- ARMul_CPSRAltered (state);
- }
-#ifdef MODET
- if (TFLAG)
- src &= 0xfffffffe;
- else
-#endif
- src &= 0xfffffffc;
- state->Reg[15] = src & PCBITS;
-#else
-#ifdef MODET
- if (TFLAG)
- /* ARMul_R15Altered would have to support it. */
- abort ();
- else
-#endif
- src &= 0xfffffffc;
-
- if (state->Bank == USERBANK)
- state->Reg[15] = (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE;
- else
- state->Reg[15] = src;
-
- ARMul_R15Altered (state);
-#endif
- FLUSHPIPE;
- if (trace_funcs)
- fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
-}
-
-/* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM
- will switch to Thumb mode if the least significant bit is set. */
-
-static void
-WriteR15Branch (ARMul_State * state, ARMword src)
-{
-#ifdef MODET
- if (src & 1)
- {
- /* Thumb bit. */
- SETT;
- state->Reg[15] = src & 0xfffffffe;
- }
- else
- {
- CLEART;
- state->Reg[15] = src & 0xfffffffc;
- }
- FLUSHPIPE;
- if (trace_funcs)
- fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
-#else
- WriteR15 (state, src);
-#endif
-}
-
-/* Before ARM_v5 LDR and LDM of pc did not change mode. */
-
-static void
-WriteR15Load (ARMul_State * state, ARMword src)
-{
- if (state->is_v5)
- WriteR15Branch (state, src);
- else
- WriteR15 (state, src);
-}
-
-/* This routine evaluates most Load and Store register RHS's. It is
- intended to be called from the macro LSRegRHS, which filters the
- common case of an unshifted register with in line code. */
-
-static ARMword
-GetLSRegRHS (ARMul_State * state, ARMword instr)
-{
- ARMword shamt, base;
-
- base = RHSReg;
-#ifndef MODE32
- if (base == 15)
- /* Now forbidden, but ... */
- base = ECC | ER15INT | R15PC | EMODE;
- else
-#endif
- base = state->Reg[base];
-
- shamt = BITS (7, 11);
- switch ((int) BITS (5, 6))
- {
- case LSL:
- return (base << shamt);
- case LSR:
- if (shamt == 0)
- return (0);
- else
- return (base >> shamt);
- case ASR:
- if (shamt == 0)
- return ((ARMword) ((ARMsword) base >> 31L));
- else
- return ((ARMword) ((ARMsword) base >> (int) shamt));
- case ROR:
- if (shamt == 0)
- /* It's an RRX. */
- return ((base >> 1) | (CFLAG << 31));
- else
- return ((base << (32 - shamt)) | (base >> shamt));
- default:
- break;
- }
- return 0;
-}
-
-/* This routine evaluates the ARM7T halfword and signed transfer RHS's. */
-
-static ARMword
-GetLS7RHS (ARMul_State * state, ARMword instr)
-{
- if (BIT (22) == 0)
- {
- /* Register. */
-#ifndef MODE32
- if (RHSReg == 15)
- /* Now forbidden, but ... */
- return ECC | ER15INT | R15PC | EMODE;
-#endif
- return state->Reg[RHSReg];
- }
-
- /* Immediate. */
- return BITS (0, 3) | (BITS (8, 11) << 4);
-}
-
-/* This function does the work of loading a word for a LDR instruction. */
-
-static unsigned
-LoadWord (ARMul_State * state, ARMword instr, ARMword address)
-{
- ARMword dest;
-
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (ADDREXCEPT (address))
- INTERNALABORT (address);
-#endif
-
- dest = ARMul_LoadWordN (state, address);
-
- if (state->Aborted)
- {
- TAKEABORT;
- return state->lateabtSig;
- }
- if (address & 3)
- dest = ARMul_Align (state, address, dest);
- WRITEDESTB (dest);
- ARMul_Icycles (state, 1, 0L);
-
- return (DESTReg != LHSReg);
-}
-
-#ifdef MODET
-/* This function does the work of loading a halfword. */
-
-static unsigned
-LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address,
- int signextend)
-{
- ARMword dest;
-
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (ADDREXCEPT (address))
- INTERNALABORT (address);
-#endif
- dest = ARMul_LoadHalfWord (state, address);
- if (state->Aborted)
- {
- TAKEABORT;
- return state->lateabtSig;
- }
- UNDEF_LSRBPC;
- if (signextend)
- if (dest & 1 << (16 - 1))
- dest = (dest & ((1 << 16) - 1)) - (1 << 16);
-
- WRITEDEST (dest);
- ARMul_Icycles (state, 1, 0L);
- return (DESTReg != LHSReg);
-}
-
-#endif /* MODET */
-
-/* This function does the work of loading a byte for a LDRB instruction. */
-
-static unsigned
-LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend)
-{
- ARMword dest;
-
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (ADDREXCEPT (address))
- INTERNALABORT (address);
-#endif
- dest = ARMul_LoadByte (state, address);
- if (state->Aborted)
- {
- TAKEABORT;
- return state->lateabtSig;
- }
- UNDEF_LSRBPC;
- if (signextend)
- if (dest & 1 << (8 - 1))
- dest = (dest & ((1 << 8) - 1)) - (1 << 8);
-
- WRITEDEST (dest);
- ARMul_Icycles (state, 1, 0L);
-
- return (DESTReg != LHSReg);
-}
-
-/* This function does the work of loading two words for a LDRD instruction. */
-
-static void
-Handle_Load_Double (ARMul_State * state, ARMword instr)
-{
- ARMword dest_reg;
- ARMword addr_reg;
- ARMword write_back = BIT (21);
- ARMword immediate = BIT (22);
- ARMword add_to_base = BIT (23);
- ARMword pre_indexed = BIT (24);
- ARMword offset;
- ARMword addr;
- ARMword sum;
- ARMword base;
- ARMword value1;
- ARMword value2;
-
- BUSUSEDINCPCS;
-
- /* If the writeback bit is set, the pre-index bit must be clear. */
- if (write_back && ! pre_indexed)
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Extract the base address register. */
- addr_reg = LHSReg;
-
- /* Extract the destination register and check it. */
- dest_reg = DESTReg;
-
- /* Destination register must be even. */
- if ((dest_reg & 1)
- /* Destination register cannot be LR. */
- || (dest_reg == 14))
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Compute the base address. */
- base = state->Reg[addr_reg];
-
- /* Compute the offset. */
- offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->Reg[RHSReg];
-
- /* Compute the sum of the two. */
- if (add_to_base)
- sum = base + offset;
- else
- sum = base - offset;
-
- /* If this is a pre-indexed mode use the sum. */
- if (pre_indexed)
- addr = sum;
- else
- addr = base;
-
- if (state->is_v6 && (addr & 0x3) == 0)
- /* Word alignment is enough for v6. */
- ;
- /* The address must be aligned on a 8 byte boundary. */
- else if (addr & 0x7)
- {
-#ifdef ABORTS
- ARMul_DATAABORT (addr);
-#else
- ARMul_UndefInstr (state, instr);
-#endif
- return;
- }
-
- /* For pre indexed or post indexed addressing modes,
- check that the destination registers do not overlap
- the address registers. */
- if ((! pre_indexed || write_back)
- && ( addr_reg == dest_reg
- || addr_reg == dest_reg + 1))
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Load the words. */
- value1 = ARMul_LoadWordN (state, addr);
- value2 = ARMul_LoadWordN (state, addr + 4);
-
- /* Check for data aborts. */
- if (state->Aborted)
- {
- TAKEABORT;
- return;
- }
-
- ARMul_Icycles (state, 2, 0L);
-
- /* Store the values. */
- state->Reg[dest_reg] = value1;
- state->Reg[dest_reg + 1] = value2;
-
- /* Do the post addressing and writeback. */
- if (! pre_indexed)
- addr = sum;
-
- if (! pre_indexed || write_back)
- state->Reg[addr_reg] = addr;
-}
-
-/* This function does the work of storing two words for a STRD instruction. */
-
-static void
-Handle_Store_Double (ARMul_State * state, ARMword instr)
-{
- ARMword src_reg;
- ARMword addr_reg;
- ARMword write_back = BIT (21);
- ARMword immediate = BIT (22);
- ARMword add_to_base = BIT (23);
- ARMword pre_indexed = BIT (24);
- ARMword offset;
- ARMword addr;
- ARMword sum;
- ARMword base;
-
- BUSUSEDINCPCS;
-
- /* If the writeback bit is set, the pre-index bit must be clear. */
- if (write_back && ! pre_indexed)
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Extract the base address register. */
- addr_reg = LHSReg;
-
- /* Base register cannot be PC. */
- if (addr_reg == 15)
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Extract the source register. */
- src_reg = DESTReg;
-
- /* Source register must be even. */
- if (src_reg & 1)
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Compute the base address. */
- base = state->Reg[addr_reg];
-
- /* Compute the offset. */
- offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->Reg[RHSReg];
-
- /* Compute the sum of the two. */
- if (add_to_base)
- sum = base + offset;
- else
- sum = base - offset;
-
- /* If this is a pre-indexed mode use the sum. */
- if (pre_indexed)
- addr = sum;
- else
- addr = base;
-
- /* The address must be aligned on a 8 byte boundary. */
- if (state->is_v6 && (addr & 0x3) == 0)
- /* Word alignment is enough for v6. */
- ;
- else if (addr & 0x7)
- {
-#ifdef ABORTS
- ARMul_DATAABORT (addr);
-#else
- ARMul_UndefInstr (state, instr);
-#endif
- return;
- }
-
- /* For pre indexed or post indexed addressing modes,
- check that the destination registers do not overlap
- the address registers. */
- if ((! pre_indexed || write_back)
- && ( addr_reg == src_reg
- || addr_reg == src_reg + 1))
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- /* Load the words. */
- ARMul_StoreWordN (state, addr, state->Reg[src_reg]);
- ARMul_StoreWordN (state, addr + 4, state->Reg[src_reg + 1]);
-
- if (state->Aborted)
- {
- TAKEABORT;
- return;
- }
-
- /* Do the post addressing and writeback. */
- if (! pre_indexed)
- addr = sum;
-
- if (! pre_indexed || write_back)
- state->Reg[addr_reg] = addr;
-}
-
-/* This function does the work of storing a word from a STR instruction. */
-
-static unsigned
-StoreWord (ARMul_State * state, ARMword instr, ARMword address)
-{
- BUSUSEDINCPCN;
-#ifndef MODE32
- if (DESTReg == 15)
- state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
-#endif
-#ifdef MODE32
- ARMul_StoreWordN (state, address, DEST);
-#else
- if (VECTORACCESS (address) || ADDREXCEPT (address))
- {
- INTERNALABORT (address);
- (void) ARMul_LoadWordN (state, address);
- }
- else
- ARMul_StoreWordN (state, address, DEST);
-#endif
- if (state->Aborted)
- {
- TAKEABORT;
- return state->lateabtSig;
- }
- return TRUE;
-}
-
-#ifdef MODET
-/* This function does the work of storing a byte for a STRH instruction. */
-
-static unsigned
-StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address)
-{
- BUSUSEDINCPCN;
-
-#ifndef MODE32
- if (DESTReg == 15)
- state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
-#endif
-
-#ifdef MODE32
- ARMul_StoreHalfWord (state, address, DEST);
-#else
- if (VECTORACCESS (address) || ADDREXCEPT (address))
- {
- INTERNALABORT (address);
- (void) ARMul_LoadHalfWord (state, address);
- }
- else
- ARMul_StoreHalfWord (state, address, DEST);
-#endif
-
- if (state->Aborted)
- {
- TAKEABORT;
- return state->lateabtSig;
- }
- return TRUE;
-}
-
-#endif /* MODET */
-
-/* This function does the work of storing a byte for a STRB instruction. */
-
-static unsigned
-StoreByte (ARMul_State * state, ARMword instr, ARMword address)
-{
- BUSUSEDINCPCN;
-#ifndef MODE32
- if (DESTReg == 15)
- state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
-#endif
-#ifdef MODE32
- ARMul_StoreByte (state, address, DEST);
-#else
- if (VECTORACCESS (address) || ADDREXCEPT (address))
- {
- INTERNALABORT (address);
- (void) ARMul_LoadByte (state, address);
- }
- else
- ARMul_StoreByte (state, address, DEST);
-#endif
- if (state->Aborted)
- {
- TAKEABORT;
- return state->lateabtSig;
- }
- UNDEF_LSRBPC;
- return TRUE;
-}
-
-/* This function does the work of loading the registers listed in an LDM
- instruction, when the S bit is clear. The code here is always increment
- after, it's up to the caller to get the input address correct and to
- handle base register modification. */
-
-static void
-LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase)
-{
- ARMword dest, temp;
-
- UNDEF_LSMNoRegs;
- UNDEF_LSMPCBase;
- UNDEF_LSMBaseInListWb;
- BUSUSEDINCPCS;
-#ifndef MODE32
- if (ADDREXCEPT (address))
- INTERNALABORT (address);
-#endif
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- /* N cycle first. */
- for (temp = 0; !BIT (temp); temp++)
- ;
-
- dest = ARMul_LoadWordN (state, address);
-
- if (!state->abortSig && !state->Aborted)
- state->Reg[temp++] = dest;
- else if (!state->Aborted)
- {
- XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
-
- /* S cycles from here on. */
- for (; temp < 16; temp ++)
- if (BIT (temp))
- {
- /* Load this register. */
- address += 4;
- dest = ARMul_LoadWordS (state, address);
-
- if (!state->abortSig && !state->Aborted)
- state->Reg[temp] = dest;
- else if (!state->Aborted)
- {
- XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
- }
-
- if (BIT (15) && !state->Aborted)
- /* PC is in the reg list. */
- WriteR15Load (state, PC);
-
- /* To write back the final register. */
- ARMul_Icycles (state, 1, 0L);
-
- if (state->Aborted)
- {
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
- TAKEABORT;
- }
-}
-
-/* This function does the work of loading the registers listed in an LDM
- instruction, when the S bit is set. The code here is always increment
- after, it's up to the caller to get the input address correct and to
- handle base register modification. */
-
-static void
-LoadSMult (ARMul_State * state,
- ARMword instr,
- ARMword address,
- ARMword WBBase)
-{
- ARMword dest, temp;
-
- UNDEF_LSMNoRegs;
- UNDEF_LSMPCBase;
- UNDEF_LSMBaseInListWb;
-
- BUSUSEDINCPCS;
-
-#ifndef MODE32
- if (ADDREXCEPT (address))
- INTERNALABORT (address);
-#endif
-
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- if (!BIT (15) && state->Bank != USERBANK)
- {
- /* Temporary reg bank switch. */
- (void) ARMul_SwitchMode (state, state->Mode, USER26MODE);
- UNDEF_LSMUserBankWb;
- }
-
- /* N cycle first. */
- for (temp = 0; !BIT (temp); temp ++)
- ;
-
- dest = ARMul_LoadWordN (state, address);
-
- if (!state->abortSig)
- state->Reg[temp++] = dest;
- else if (!state->Aborted)
- {
- XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
-
- /* S cycles from here on. */
- for (; temp < 16; temp++)
- if (BIT (temp))
- {
- /* Load this register. */
- address += 4;
- dest = ARMul_LoadWordS (state, address);
-
- if (!state->abortSig && !state->Aborted)
- state->Reg[temp] = dest;
- else if (!state->Aborted)
- {
- XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
- }
-
- if (BIT (15) && !state->Aborted)
- {
- /* PC is in the reg list. */
-#ifdef MODE32
- if (state->Mode != USER26MODE && state->Mode != USER32MODE)
- {
- state->Cpsr = GETSPSR (state->Bank);
- ARMul_CPSRAltered (state);
- }
-
- WriteR15 (state, PC);
-#else
- if (state->Mode == USER26MODE || state->Mode == USER32MODE)
- {
- /* Protect bits in user mode. */
- ASSIGNN ((state->Reg[15] & NBIT) != 0);
- ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
- ASSIGNC ((state->Reg[15] & CBIT) != 0);
- ASSIGNV ((state->Reg[15] & VBIT) != 0);
- }
- else
- ARMul_R15Altered (state);
-
- FLUSHPIPE;
-#endif
- }
-
- if (!BIT (15) && state->Mode != USER26MODE && state->Mode != USER32MODE)
- /* Restore the correct bank. */
- (void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
-
- /* To write back the final register. */
- ARMul_Icycles (state, 1, 0L);
-
- if (state->Aborted)
- {
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- TAKEABORT;
- }
-}
-
-/* This function does the work of storing the registers listed in an STM
- instruction, when the S bit is clear. The code here is always increment
- after, it's up to the caller to get the input address correct and to
- handle base register modification. */
-
-static void
-StoreMult (ARMul_State * state,
- ARMword instr,
- ARMword address,
- ARMword WBBase)
-{
- ARMword temp;
-
- UNDEF_LSMNoRegs;
- UNDEF_LSMPCBase;
- UNDEF_LSMBaseInListWb;
-
- if (!TFLAG)
- /* N-cycle, increment the PC and update the NextInstr state. */
- BUSUSEDINCPCN;
-
-#ifndef MODE32
- if (VECTORACCESS (address) || ADDREXCEPT (address))
- INTERNALABORT (address);
-
- if (BIT (15))
- PATCHR15;
-#endif
-
- /* N cycle first. */
- for (temp = 0; !BIT (temp); temp ++)
- ;
-
-#ifdef MODE32
- ARMul_StoreWordN (state, address, state->Reg[temp++]);
-#else
- if (state->Aborted)
- {
- (void) ARMul_LoadWordN (state, address);
-
- /* Fake the Stores as Loads. */
- for (; temp < 16; temp++)
- if (BIT (temp))
- {
- /* Save this register. */
- address += 4;
- (void) ARMul_LoadWordS (state, address);
- }
-
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
- TAKEABORT;
- return;
- }
- else
- ARMul_StoreWordN (state, address, state->Reg[temp++]);
-#endif
-
- if (state->abortSig && !state->Aborted)
- {
- XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
-
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- /* S cycles from here on. */
- for (; temp < 16; temp ++)
- if (BIT (temp))
- {
- /* Save this register. */
- address += 4;
-
- ARMul_StoreWordS (state, address, state->Reg[temp]);
-
- if (state->abortSig && !state->Aborted)
- {
- XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
- }
-
- if (state->Aborted)
- TAKEABORT;
-}
-
-/* This function does the work of storing the registers listed in an STM
- instruction when the S bit is set. The code here is always increment
- after, it's up to the caller to get the input address correct and to
- handle base register modification. */
-
-static void
-StoreSMult (ARMul_State * state,
- ARMword instr,
- ARMword address,
- ARMword WBBase)
-{
- ARMword temp;
-
- UNDEF_LSMNoRegs;
- UNDEF_LSMPCBase;
- UNDEF_LSMBaseInListWb;
-
- BUSUSEDINCPCN;
-
-#ifndef MODE32
- if (VECTORACCESS (address) || ADDREXCEPT (address))
- INTERNALABORT (address);
-
- if (BIT (15))
- PATCHR15;
-#endif
-
- if (state->Bank != USERBANK)
- {
- /* Force User Bank. */
- (void) ARMul_SwitchMode (state, state->Mode, USER26MODE);
- UNDEF_LSMUserBankWb;
- }
-
- for (temp = 0; !BIT (temp); temp++)
- ; /* N cycle first. */
-
-#ifdef MODE32
- ARMul_StoreWordN (state, address, state->Reg[temp++]);
-#else
- if (state->Aborted)
- {
- (void) ARMul_LoadWordN (state, address);
-
- for (; temp < 16; temp++)
- /* Fake the Stores as Loads. */
- if (BIT (temp))
- {
- /* Save this register. */
- address += 4;
-
- (void) ARMul_LoadWordS (state, address);
- }
-
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- TAKEABORT;
- return;
- }
- else
- ARMul_StoreWordN (state, address, state->Reg[temp++]);
-#endif
-
- if (state->abortSig && !state->Aborted)
- {
- XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
-
- /* S cycles from here on. */
- for (; temp < 16; temp++)
- if (BIT (temp))
- {
- /* Save this register. */
- address += 4;
-
- ARMul_StoreWordS (state, address, state->Reg[temp]);
-
- if (state->abortSig && !state->Aborted)
- {
- XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
- state->Aborted = ARMul_DataAbortV;
- }
- }
-
- if (state->Mode != USER26MODE && state->Mode != USER32MODE)
- /* Restore the correct bank. */
- (void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
-
- if (BIT (21) && LHSReg != 15)
- LSBase = WBBase;
-
- if (state->Aborted)
- TAKEABORT;
-}
-
-/* This function does the work of adding two 32bit values
- together, and calculating if a carry has occurred. */
-
-static ARMword
-Add32 (ARMword a1, ARMword a2, int *carry)
-{
- ARMword result = (a1 + a2);
- unsigned int uresult = (unsigned int) result;
- unsigned int ua1 = (unsigned int) a1;
-
- /* If (result == RdLo) and (state->Reg[nRdLo] == 0),
- or (result > RdLo) then we have no carry. */
- if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1))
- *carry = 1;
- else
- *carry = 0;
-
- return result;
-}
-
-/* This function does the work of multiplying
- two 32bit values to give a 64bit result. */
-
-static unsigned
-Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
-{
- /* Operand register numbers. */
- int nRdHi, nRdLo, nRs, nRm;
- ARMword RdHi = 0, RdLo = 0, Rm;
- /* Cycle count. */
- int scount;
-
- nRdHi = BITS (16, 19);
- nRdLo = BITS (12, 15);
- nRs = BITS (8, 11);
- nRm = BITS (0, 3);
-
- /* Needed to calculate the cycle count. */
- Rm = state->Reg[nRm];
-
- /* Check for illegal operand combinations first. */
- if ( nRdHi != 15
- && nRdLo != 15
- && nRs != 15
- && nRm != 15
- && nRdHi != nRdLo)
- {
- /* Intermediate results. */
- ARMword lo, mid1, mid2, hi;
- int carry;
- ARMword Rs = state->Reg[nRs];
- int sign = 0;
-
-#ifdef MODE32
- if (state->is_v6)
- ;
- else
-#endif
- /* BAD code can trigger this result. So only complain if debugging. */
- if (state->Debug && (nRdHi == nRm || nRdLo == nRm))
- fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS: %d %d %d\n",
- nRdHi, nRdLo, nRm);
- if (msigned)
- {
- /* Compute sign of result and adjust operands if necessary. */
- sign = (Rm ^ Rs) & 0x80000000;
-
- if (((ARMsword) Rm) < 0)
- Rm = -Rm;
-
- if (((ARMsword) Rs) < 0)
- Rs = -Rs;
- }
-
- /* We can split the 32x32 into four 16x16 operations. This
- ensures that we do not lose precision on 32bit only hosts. */
- lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF));
- mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
- mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF));
- hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
-
- /* We now need to add all of these results together, taking
- care to propagate the carries from the additions. */
- RdLo = Add32 (lo, (mid1 << 16), &carry);
- RdHi = carry;
- RdLo = Add32 (RdLo, (mid2 << 16), &carry);
- RdHi +=
- (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
-
- if (sign)
- {
- /* Negate result if necessary. */
- RdLo = ~RdLo;
- RdHi = ~RdHi;
- if (RdLo == 0xFFFFFFFF)
- {
- RdLo = 0;
- RdHi += 1;
- }
- else
- RdLo += 1;
- }
-
- state->Reg[nRdLo] = RdLo;
- state->Reg[nRdHi] = RdHi;
- }
- else if (state->Debug)
- fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS\n");
-
- if (scc)
- /* Ensure that both RdHi and RdLo are used to compute Z,
- but don't let RdLo's sign bit make it to N. */
- ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
-
- /* The cycle count depends on whether the instruction is a signed or
- unsigned multiply, and what bits are clear in the multiplier. */
- if (msigned && (Rm & ((unsigned) 1 << 31)))
- /* Invert the bits to make the check against zero. */
- Rm = ~Rm;
-
- if ((Rm & 0xFFFFFF00) == 0)
- scount = 1;
- else if ((Rm & 0xFFFF0000) == 0)
- scount = 2;
- else if ((Rm & 0xFF000000) == 0)
- scount = 3;
- else
- scount = 4;
-
- return 2 + scount;
-}
-
-/* This function does the work of multiplying two 32bit
- values and adding a 64bit value to give a 64bit result. */
-
-static unsigned
-MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc)
-{
- unsigned scount;
- ARMword RdLo, RdHi;
- int nRdHi, nRdLo;
- int carry = 0;
-
- nRdHi = BITS (16, 19);
- nRdLo = BITS (12, 15);
-
- RdHi = state->Reg[nRdHi];
- RdLo = state->Reg[nRdLo];
-
- scount = Multiply64 (state, instr, msigned, LDEFAULT);
-
- RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry);
- RdHi = (RdHi + state->Reg[nRdHi]) + carry;
-
- state->Reg[nRdLo] = RdLo;
- state->Reg[nRdHi] = RdHi;
-
- if (scc)
- /* Ensure that both RdHi and RdLo are used to compute Z,
- but don't let RdLo's sign bit make it to N. */
- ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
-
- /* Extra cycle for addition. */
- return scount + 1;
-}
+++ /dev/null
-/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-#include "armdefs.h"
-
-extern ARMword isize;
-extern int trace;
-extern int disas;
-extern int trace_funcs;
-extern void print_insn (ARMword);
-
-/* Condition code values. */
-#define EQ 0
-#define NE 1
-#define CS 2
-#define CC 3
-#define MI 4
-#define PL 5
-#define VS 6
-#define VC 7
-#define HI 8
-#define LS 9
-#define GE 10
-#define LT 11
-#define GT 12
-#define LE 13
-#define AL 14
-#define NV 15
-
-/* Shift Opcodes. */
-#define LSL 0
-#define LSR 1
-#define ASR 2
-#define ROR 3
-
-/* Macros to twiddle the status flags and mode. */
-#define NBIT ((unsigned)1L << 31)
-#define ZBIT (1L << 30)
-#define CBIT (1L << 29)
-#define VBIT (1L << 28)
-#define SBIT (1L << 27)
-#define GE0 (1L << 16)
-#define GE1 (1L << 17)
-#define GE2 (1L << 18)
-#define GE3 (1L << 19)
-#define IBIT (1L << 7)
-#define FBIT (1L << 6)
-#define IFBITS (3L << 6)
-#define R15IBIT (1L << 27)
-#define R15FBIT (1L << 26)
-#define R15IFBITS (3L << 26)
-
-#define POS(i) ( (~(i)) >> 31 )
-#define NEG(i) ( (i) >> 31 )
-
-#ifdef MODET /* Thumb support. */
-/* ??? This bit is actually in the low order bit of the PC in the hardware.
- It isn't clear if the simulator needs to model that or not. */
-#define TBIT (1L << 5)
-#define TFLAG state->TFlag
-#define SETT state->TFlag = 1
-#define CLEART state->TFlag = 0
-#define ASSIGNT(res) state->TFlag = res
-#define INSN_SIZE (TFLAG ? 2 : 4)
-#else
-#define INSN_SIZE 4
-#endif
-
-#define NFLAG state->NFlag
-#define SETN state->NFlag = 1
-#define CLEARN state->NFlag = 0
-#define ASSIGNN(res) state->NFlag = res
-
-#define ZFLAG state->ZFlag
-#define SETZ state->ZFlag = 1
-#define CLEARZ state->ZFlag = 0
-#define ASSIGNZ(res) state->ZFlag = res
-
-#define CFLAG state->CFlag
-#define SETC state->CFlag = 1
-#define CLEARC state->CFlag = 0
-#define ASSIGNC(res) state->CFlag = res
-
-#define VFLAG state->VFlag
-#define SETV state->VFlag = 1
-#define CLEARV state->VFlag = 0
-#define ASSIGNV(res) state->VFlag = res
-
-#define SFLAG state->SFlag
-#define SETS state->SFlag = 1
-#define CLEARS state->SFlag = 0
-#define ASSIGNS(res) state->SFlag = res
-
-#define IFLAG (state->IFFlags >> 1)
-#define FFLAG (state->IFFlags & 1)
-#define IFFLAGS state->IFFlags
-#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
-#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
-
-#define PSR_FBITS (0xff000000L)
-#define PSR_SBITS (0x00ff0000L)
-#define PSR_XBITS (0x0000ff00L)
-#define PSR_CBITS (0x000000ffL)
-
-#if defined MODE32 || defined MODET
-#define CCBITS (0xf8000000L)
-#else
-#define CCBITS (0xf0000000L)
-#endif
-
-#define INTBITS (0xc0L)
-
-#if defined MODET && defined MODE32
-#define PCBITS (0xffffffffL)
-#else
-#define PCBITS (0xfffffffcL)
-#endif
-
-#define MODEBITS (0x1fL)
-#define R15INTBITS (3L << 26)
-
-#if defined MODET && defined MODE32
-#define R15PCBITS (0x03ffffffL)
-#else
-#define R15PCBITS (0x03fffffcL)
-#endif
-
-#define R15PCMODEBITS (0x03ffffffL)
-#define R15MODEBITS (0x3L)
-
-#ifdef MODE32
-#define PCMASK PCBITS
-#define PCWRAP(pc) (pc)
-#else
-#define PCMASK R15PCBITS
-#define PCWRAP(pc) ((pc) & R15PCBITS)
-#endif
-
-#define PC (state->Reg[15] & PCMASK)
-#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
-#define R15INT (state->Reg[15] & R15INTBITS)
-#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
-#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
-#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
-#define R15PC (state->Reg[15] & R15PCBITS)
-#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
-#define R15MODE (state->Reg[15] & R15MODEBITS)
-
-#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27))
-#define EINT (IFFLAGS << 6)
-#define ER15INT (IFFLAGS << 26)
-#define EMODE (state->Mode)
-
-#ifdef MODET
-#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
-#else
-#define CPSR (ECC | EINT | EMODE)
-#endif
-
-#ifdef MODE32
-#define PATCHR15
-#else
-#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
-#endif
-
-#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
-#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
-#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
-#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
-#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
-
-#define SETR15PSR(s) \
- do \
- { \
- if (state->Mode == USER26MODE) \
- { \
- state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE; \
- ASSIGNN ((state->Reg[15] & NBIT) != 0); \
- ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \
- ASSIGNC ((state->Reg[15] & CBIT) != 0); \
- ASSIGNV ((state->Reg[15] & VBIT) != 0); \
- } \
- else \
- { \
- state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)); \
- ARMul_R15Altered (state); \
- } \
- } \
- while (0)
-
-#define SETABORT(i, m, d) \
- do \
- { \
- int SETABORT_mode = (m); \
- \
- ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
- ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
- | (i) | SETABORT_mode)); \
- state->Reg[14] = temp - (d); \
- } \
- while (0)
-
-#ifndef MODE32
-#define VECTORS 0x20
-#define LEGALADDR 0x03ffffff
-#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
-#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
-#endif
-
-#define INTERNALABORT(address) \
- do \
- { \
- if (address < VECTORS) \
- state->Aborted = ARMul_DataAbortV; \
- else \
- state->Aborted = ARMul_AddrExceptnV; \
- } \
- while (0)
-
-#ifdef MODE32
-#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV)
-#else
-#define TAKEABORT \
- do \
- { \
- if (state->Aborted == ARMul_AddrExceptnV) \
- ARMul_Abort (state, ARMul_AddrExceptnV); \
- else \
- ARMul_Abort (state, ARMul_DataAbortV); \
- } \
- while (0)
-#endif
-
-#define CPTAKEABORT \
- do \
- { \
- if (!state->Aborted) \
- ARMul_Abort (state, ARMul_UndefinedInstrV); \
- else if (state->Aborted == ARMul_AddrExceptnV) \
- ARMul_Abort (state, ARMul_AddrExceptnV); \
- else \
- ARMul_Abort (state, ARMul_DataAbortV); \
- } \
- while (0);
-
-
-/* Different ways to start the next instruction. */
-#define SEQ 0
-#define NONSEQ 1
-#define PCINCEDSEQ 2
-#define PCINCEDNONSEQ 3
-#define PRIMEPIPE 4
-#define RESUME 8
-
-#define NORMALCYCLE state->NextInstr = 0
-#define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */
-#define BUSUSEDINCPCS \
- do \
- { \
- if (! state->is_v4) \
- { \
- /* A standard PC inc and an S cycle. */ \
- state->Reg[15] += isize; \
- state->NextInstr = (state->NextInstr & 0xff) | 2; \
- } \
- } \
- while (0)
-
-#define BUSUSEDINCPCN \
- do \
- { \
- if (state->is_v4) \
- BUSUSEDN; \
- else \
- { \
- /* A standard PC inc and an N cycle. */ \
- state->Reg[15] += isize; \
- state->NextInstr |= 3; \
- } \
- } \
- while (0)
-
-#define INCPC \
- do \
- { \
- /* A standard PC inc. */ \
- state->Reg[15] += isize; \
- state->NextInstr |= 2; \
- } \
- while (0)
-
-#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
-
-/* Cycle based emulation. */
-
-#define OUTPUTCP(i,a,b)
-#define NCYCLE
-#define SCYCLE
-#define ICYCLE
-#define CCYCLE
-#define NEXTCYCLE(c)
-
-/* Macros to extract parts of instructions. */
-#define DESTReg (BITS (12, 15))
-#define LHSReg (BITS (16, 19))
-#define RHSReg (BITS ( 0, 3))
-
-#define DEST (state->Reg[DESTReg])
-
-#ifdef MODE32
-#ifdef MODET
-#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
-#else
-#define LHS (state->Reg[LHSReg])
-#endif
-#else
-#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]))
-#endif
-
-#define MULDESTReg (BITS (16, 19))
-#define MULLHSReg (BITS ( 0, 3))
-#define MULRHSReg (BITS ( 8, 11))
-#define MULACCReg (BITS (12, 15))
-
-#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)])
-#define DPSImmRHS temp = BITS(0,11) ; \
- rhs = ARMul_ImmedTable[temp] ; \
- if (temp > 255) /* There was a shift. */ \
- ASSIGNC (rhs >> 31) ;
-
-#ifdef MODE32
-#define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
- : GetDPRegRHS (state, instr))
-#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
- : GetDPSRegRHS (state, instr))
-#else
-#define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
- : GetDPRegRHS (state, instr))
-#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
- : GetDPSRegRHS (state, instr))
-#endif
-
-#define LSBase state->Reg[LHSReg]
-#define LSImmRHS (BITS(0,11))
-
-#ifdef MODE32
-#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
- : GetLSRegRHS (state, instr))
-#else
-#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
- : GetLSRegRHS (state, instr))
-#endif
-
-#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \
- (ARMword) ARMul_BitList[BITS (8, 15)] )
-#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \
- (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0))
-
-#define SWAPSRC (state->Reg[RHSReg])
-
-#define LSCOff (BITS (0, 7) << 2)
-#define CPNum BITS (8, 11)
-
-/* Determine if access to coprocessor CP is permitted.
- The XScale has a register in CP15 which controls access to CP0 - CP13. */
-#define CP_ACCESS_ALLOWED(STATE, CP) \
- ( ((CP) >= 14) \
- || (! (STATE)->is_XScale) \
- || (read_cp15_reg (15, 0, 1) & (1 << (CP))))
-
-/* Macro to rotate n right by b bits. */
-#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))
-
-/* Macros to store results of instructions. */
-#define WRITEDEST(d) \
- do \
- { \
- if (DESTReg == 15) \
- WriteR15 (state, d); \
- else \
- DEST = d; \
- } \
- while (0)
-
-#define WRITESDEST(d) \
- do \
- { \
- if (DESTReg == 15) \
- WriteSR15 (state, d); \
- else \
- { \
- DEST = d; \
- ARMul_NegZero (state, d); \
- } \
- } \
- while (0)
-
-#define WRITEDESTB(d) \
- do \
- { \
- if (DESTReg == 15) \
- WriteR15Load (state, d); \
- else \
- DEST = d; \
- } \
- while (0)
-
-#define BYTETOBUS(data) ((data & 0xff) | \
- ((data & 0xff) << 8) | \
- ((data & 0xff) << 16) | \
- ((data & 0xff) << 24))
-
-#define BUSTOBYTE(address, data) \
- do \
- { \
- if (state->bigendSig) \
- temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \
- else \
- temp = (data >> ((address & 3) << 3)) & 0xff; \
- } \
- while (0)
-
-#define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb)
-#define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb)
-#define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb)
-#define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb)
-
-#define POSBRANCH ((instr & 0x7fffff) << 2)
-#define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2)
-
-
-/* Values for Emulate. */
-#define STOP 0 /* stop */
-#define CHANGEMODE 1 /* change mode */
-#define ONCE 2 /* execute just one interation */
-#define RUN 3 /* continuous execution */
-
-/* Stuff that is shared across modes. */
-extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */
-extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */
-extern char ARMul_BitList[]; /* Number of bits in a byte table. */
-
-#define EVENTLISTSIZE 1024L
-
-/* Thumb support. */
-typedef enum
-{
- t_undefined, /* Undefined Thumb instruction. */
- t_decoded, /* Instruction decoded to ARM equivalent. */
- t_branch /* Thumb branch (already processed). */
-}
-tdstate;
-
-#define t_resolved t_branch
-
-/* Macros to scrutinize instructions. The dummy do loop is to keep the compiler
- happy when the statement is used in an otherwise empty else statement. */
-#define UNDEF_Test do { ; } while (0)
-#define UNDEF_Shift do { ; } while (0)
-#define UNDEF_MSRPC do { ; } while (0)
-#define UNDEF_MRSPC do { ; } while (0)
-#define UNDEF_MULPCDest do { ; } while (0)
-#define UNDEF_MULDestEQOp1 do { ; } while (0)
-#define UNDEF_LSRBPC do { ; } while (0)
-#define UNDEF_LSRBaseEQOffWb do { ; } while (0)
-#define UNDEF_LSRBaseEQDestWb do { ; } while (0)
-#define UNDEF_LSRPCBaseWb do { ; } while (0)
-#define UNDEF_LSRPCOffWb do { ; } while (0)
-#define UNDEF_LSMNoRegs do { ; } while (0)
-#define UNDEF_LSMPCBase do { ; } while (0)
-#define UNDEF_LSMUserBankWb do { ; } while (0)
-#define UNDEF_LSMBaseInListWb do { ; } while (0)
-#define UNDEF_SWPPC do { ; } while (0)
-#define UNDEF_CoProHS do { ; } while (0)
-#define UNDEF_MCRPC do { ; } while (0)
-#define UNDEF_LSCPCBaseWb do { ; } while (0)
-#define UNDEF_UndefNotBounced do { ; } while (0)
-#define UNDEF_ShortInt do { ; } while (0)
-#define UNDEF_IllegalMode do { ; } while (0)
-#define UNDEF_Prog32SigChange do { ; } while (0)
-#define UNDEF_Data32SigChange do { ; } while (0)
-
-/* Prototypes for exported functions. */
-extern unsigned ARMul_NthReg (ARMword, unsigned);
-extern int AddOverflow (ARMword, ARMword, ARMword);
-extern int SubOverflow (ARMword, ARMword, ARMword);
-extern ARMword ARMul_Emulate26 (ARMul_State *);
-extern ARMword ARMul_Emulate32 (ARMul_State *);
-extern unsigned IntPending (ARMul_State *);
-extern void ARMul_CPSRAltered (ARMul_State *);
-extern void ARMul_R15Altered (ARMul_State *);
-extern ARMword ARMul_GetPC (ARMul_State *);
-extern ARMword ARMul_GetNextPC (ARMul_State *);
-extern ARMword ARMul_GetR15 (ARMul_State *);
-extern ARMword ARMul_GetCPSR (ARMul_State *);
-extern void ARMul_EnvokeEvent (ARMul_State *);
-extern unsigned long ARMul_Time (ARMul_State *);
-extern void ARMul_NegZero (ARMul_State *, ARMword);
-extern void ARMul_SetPC (ARMul_State *, ARMword);
-extern void ARMul_SetR15 (ARMul_State *, ARMword);
-extern void ARMul_SetCPSR (ARMul_State *, ARMword);
-extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword);
-extern void ARMul_Abort26 (ARMul_State *, ARMword);
-extern void ARMul_Abort32 (ARMul_State *, ARMword);
-extern ARMword ARMul_MRC (ARMul_State *, ARMword);
-extern void ARMul_CDP (ARMul_State *, ARMword);
-extern void ARMul_LDC (ARMul_State *, ARMword, ARMword);
-extern void ARMul_STC (ARMul_State *, ARMword, ARMword);
-extern void ARMul_MCR (ARMul_State *, ARMword, ARMword);
-extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword);
-extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
-extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword);
-extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
-extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword);
-extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword);
-extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword);
-extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword);
-extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
-extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *);
-extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned);
-extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword);
-extern void ARMul_ScheduleEvent (ARMul_State *, unsigned long, unsigned (*) (ARMul_State *));
-/* Coprocessor support functions. */
-extern unsigned ARMul_CoProInit (ARMul_State *);
-extern void ARMul_CoProExit (ARMul_State *);
-extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *,
- ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *,
- ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *);
-extern void ARMul_CoProDetach (ARMul_State *, unsigned);
-extern ARMword read_cp15_reg (unsigned, unsigned, unsigned);
-
-extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword);
-extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword);
-extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *);
-extern unsigned DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *);
-extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword);
-extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword);
-extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *);
-extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword);
-extern unsigned DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *);
-extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword);
-extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword);
-extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *);
-extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword);
+++ /dev/null
-/* Build armemu.c with ARM32 support.
- Copyright (C) 1995-2024 Free Software Foundation, Inc.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <https://www.gnu.org/licenses/>. */
-
-#define MODE32
-#include "armemu.c"
+++ /dev/null
-/* armfpe.h -- ARMulator pre-compiled FPE: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* Array containing the Floating Point Emualtor (FPE). */
-unsigned long fpecode[] =
-{
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00070000, 0x00000000, 0xe92d400e, 0xeb0013ef,
- 0xe28f00d4, 0xe1a00120, 0xe38004ea, 0xe3a01004,
- 0xe5912000, 0xe24f3028, 0xe1500002, 0x15832000,
- 0x15810000, 0xe3a00001, 0xe8bd800e, 0xe28d9040,
- 0xe1a0a00e, 0xe24f7048, 0xe597b000, 0xe20b74ee,
- 0xe14f8000, 0xe2088040, 0xe388809b, 0xe121f008,
- 0xe35704ea, 0x004bb007, 0x01a0b10b, 0x028bf00c,
- 0xe20b733b, 0xe3570339, 0x01a0ba0b, 0x01a0ba2b,
- 0x059bb00c, 0x0249800c, 0x08880e00, 0x0919ff80,
- 0xe24f7094, 0xe1a0f007, 0xe14f8000, 0xe2088040,
- 0xe3888093, 0xe121f008, 0xe8dd7fff, 0xe1a00000,
- 0xe28dd03c, 0xe8fd8000, 0xe14f8000, 0xe2088040,
- 0xe3888093, 0xe121f008, 0xe8bd1fff, 0xe28dd00c,
- 0xe1b0f00e, 0xe14f8000, 0xe2088040, 0xe3888093,
- 0xe121f008, 0xe28dd01c, 0xe8bd1f80, 0xe28dd00c,
- 0xe1b0f00e, 0x00002100, 0xe90d4007, 0xe14f0000,
- 0xe24d1010, 0xe10f2000, 0xe20220c0, 0xe3822003,
- 0xe121f002, 0xe169f000, 0xe8914007, 0xe24dd040,
- 0xe8cd7fff, 0xe24fcf6b, 0xe58de03c, 0xe24ea004,
- 0xe14f9000, 0xe20990c0, 0xe3899003, 0xe121f009,
- 0xe4ba9008, 0xe20987fe, 0xe2197010, 0xe0077aa9,
- 0xe0288a07, 0x02097402, 0x00077509, 0x00888007,
- 0xe2097c0f, 0xe3370c01, 0x0209733e, 0x0337033a,
- 0x008ff8a8, 0xea00009f, 0xea0003b7, 0xea0003b6,
- 0xea000307, 0xea000306, 0xea0003b3, 0xea0003b2,
- 0xea000303, 0xea000302, 0xea0003c3, 0xea0003c2,
- 0xea00030d, 0xea00030c, 0xea0003bf, 0xea0003be,
- 0xea000309, 0xea000308, 0xea0003cf, 0xea0003ce,
- 0xea000314, 0xea000313, 0xea0003cb, 0xea0003ca,
- 0xea000310, 0xea00030f, 0xea0003db, 0xea0003da,
- 0xea00031a, 0xea000319, 0xea0003d7, 0xea0003d6,
- 0xea000316, 0xea000315, 0xea0003e7, 0xea0003e6,
- 0xea000321, 0xea000320, 0xea0003f7, 0xea0003f6,
- 0xea00032b, 0xea00032a, 0xea000449, 0xea000448,
- 0xea000335, 0xea000334, 0xea000459, 0xea000458,
- 0xea000340, 0xea00033f, 0xea000469, 0xea000468,
- 0xea00034b, 0xea00034a, 0xea000479, 0xea000478,
- 0xea000355, 0xea000354, 0xea000489, 0xea000488,
- 0xea00035f, 0xea00035e, 0xea000499, 0xea000498,
- 0xea00036a, 0xea000369, 0xea000ac8, 0xea000ac5,
- 0xea000c3d, 0xea000c3a, 0xea000b7b, 0xea000b78,
- 0xea000b79, 0xea000b76, 0xea000d34, 0xea000d31,
- 0xea000d08, 0xea000d05, 0xea000e34, 0xea000e31,
- 0xea000e1c, 0xea000e19, 0xea000ecf, 0xea000ecc,
- 0xea000c2d, 0xea000c2a, 0xea000d28, 0xea000d25,
- 0xea000cfc, 0xea000cf9, 0xea00123d, 0xea00123a,
- 0xeaffff55, 0xeaffff54, 0xeaffff53, 0xeaffff52,
- 0xeaffff51, 0xeaffff50, 0xea0007b8, 0xea0007ec,
- 0xea00073c, 0xea00073b, 0xea000806, 0xea000805,
- 0xea00080f, 0xea00080e, 0xeaffff47, 0xeaffff46,
- 0xeaffff45, 0xeaffff44, 0xeaffff43, 0xeaffff42,
- 0xeaffff41, 0xeaffff40, 0xeaffff3f, 0xeaffff3e,
- 0xea00086f, 0xea00086e, 0xeaffff3b, 0xeaffff3a,
- 0xea00086b, 0xea00086a, 0xeaffff37, 0xeaffff36,
- 0xea0007ff, 0xea0007fe, 0xeaffff33, 0xeaffff32,
- 0xea0007fb, 0xea0007fa, 0xea000914, 0xea0008f3,
- 0xea00091f, 0xea0008fb, 0xea00092b, 0xea000904,
- 0xea0009dc, 0xea0009d9, 0xea0009fd, 0xea0009fa,
- 0xea000ef8, 0xea000ef5, 0xea000ef6, 0xea000ef3,
- 0xea000f9d, 0xea000f9a, 0xea00111e, 0xea00111b,
- 0xea00111c, 0xea001119, 0xea00104e, 0xea00104b,
- 0xea001147, 0xea001144, 0xea001145, 0xea001142,
- 0xea00125a, 0xea001257, 0xeaffff13, 0xeaffff12,
- 0xeaffff11, 0xeaffff10, 0xe3190c0e, 0x1affff0e,
- 0xe3190c01, 0x13190302, 0x0affff0b, 0xe28fb016,
- 0xe79b7d27, 0xe14fb000, 0xe1a0be2b, 0xe28bb010,
- 0xe1170b37, 0x0affff51, 0xeaffff29, 0x8000f0f0,
- 0x80000f0f, 0x8000cccc, 0x80003333, 0x8000ff00,
- 0x800000ff, 0x8000aaaa, 0x80005555, 0x8000cfcf,
- 0x80003030, 0x800055aa, 0x8000aa55, 0x80005faf,
- 0x8000a050, 0x80000000, 0x8000ffff, 0xe1300007,
- 0x5a000002, 0xea00004a, 0xe3100102, 0x1a000048,
- 0xe053400b, 0x4a00002d, 0xe2745020, 0xda00001b,
- 0xe092243a, 0x20822518, 0x30922518, 0xe0b11438,
- 0xe1a0451a, 0x2a000006, 0xe0922fa4, 0xe2b11000,
- 0x31b0f00e, 0xe3a01102, 0xe2833001, 0xe1a040a4,
- 0xe1b0f00e, 0xe2833001, 0xe1a040a4, 0xe1844f82,
- 0xe1a020a2, 0xe1822f81, 0xe1a01061, 0xe0922fa4,
- 0xe2a11000, 0xe1b0f00e, 0xe1a04538, 0xe0922fa4,
- 0xe2b11000, 0x23a01102, 0x22833001, 0xe1b0f00e,
- 0xe2545040, 0xaafffff7, 0xe2444020, 0xe2645020,
- 0xe0922438, 0xe2b11000, 0xe1a04518, 0xe184443a,
- 0x2affffe7, 0xe0922fa4, 0xe2b11000, 0x31b0f00e,
- 0xe3a01102, 0xe2833001, 0xe1a040a4, 0xe1b0f00e,
- 0xe2644000, 0xe1a0300b, 0xe1a05001, 0xe1a01008,
- 0xe1a08005, 0xe1a05002, 0xe1a0200a, 0xe1a0a005,
- 0xe2745020, 0xdaffffe5, 0xe092243a, 0x20822518,
- 0x30922518, 0xe0b11438, 0xe1a0451a, 0x2affffd0,
- 0xe0922fa4, 0xe2b11000, 0x31b0f00e, 0xe3a01102,
- 0xe2833001, 0xe1a040a4, 0xe1b0f00e, 0xe3100102,
- 0x1affffb6, 0xe053600b, 0x4a00003d, 0x01510008,
- 0x0152000a, 0x0a00004f, 0x3a000039, 0xe3a04000,
- 0xe2765020, 0xda00001a, 0xe054451a, 0xe0d2263a,
- 0x30422518, 0x20522518, 0xe0d11638, 0x5a000002,
- 0xe0922fa4, 0xe2a11000, 0xe1b0f00e, 0xe0944004,
- 0xe0b22002, 0xe0b11001, 0xe2433001, 0x5afffffa,
- 0xe0922fa4, 0xe2b11000, 0x31b0f00e, 0xe3a01102,
- 0xe2833001, 0xe1a040a4, 0xe1b0f00e, 0xe0544538,
- 0x41b0f00e, 0xe2d22000, 0xe2d11000, 0x41b0f00e,
- 0xeaffffed, 0xe3a04000, 0xe2565040, 0xaafffff6,
- 0xe2466020, 0xe2665020, 0xe054751a, 0xe0d4463a,
- 0x30444518, 0x20544518, 0xe0d22638, 0xe2d11000,
- 0x5a000002, 0xe0922fa4, 0xe2a11000, 0xe1b0f00e,
- 0xe0977007, 0xe0b44004, 0xe0b22002, 0xe0b11001,
- 0xe2433001, 0x5afffff9, 0xe0922fa4, 0xe2b11000,
- 0x31b0f00e, 0xe3a01102, 0xe2833001, 0xe1a040a4,
- 0xe1b0f00e, 0xe2666000, 0xe2200102, 0xe1a0300b,
- 0xe1a05001, 0xe1a01008, 0xe1a08005, 0xe1a05002,
- 0xe1a0200a, 0xe1a0a005, 0xe3a04000, 0xe2765020,
- 0xdaffffd7, 0xe054451a, 0xe0d2263a, 0x30422518,
- 0x20522518, 0xe0d11638, 0x5affffbf, 0xe0922fa4,
- 0xe2a11000, 0xe1b0f00e, 0xe3a03000, 0xe3a02000,
- 0xe3a01000, 0xe3a04000, 0xe1b0f00e, 0xe1a07000,
- 0xe1a08001, 0xe1a0a002, 0xe1a0b003, 0xe0200007,
- 0xe1914002, 0x1198400a, 0x0afffff2, 0xe3b054ff,
- 0xe0a3300b, 0xe185b425, 0xe043392b, 0xe92c4209,
- 0xe1a04821, 0xe1c1500b, 0xe1a06822, 0xe1c2700b,
- 0xe1c8900b, 0xe1a08828, 0xe1cab00b, 0xe1a0a82a,
- 0xe0030b96, 0xe0020b94, 0xe0010994, 0xe0000a97,
- 0xe0933000, 0xe0000a95, 0xe0b22000, 0xe0000895,
- 0xe0b11000, 0x33a0e000, 0x23a0e001, 0xe0000996,
- 0xe0922000, 0xe2b11000, 0xe2aee000, 0xe0000897,
- 0xe0922000, 0xe2b11000, 0xe2aee000, 0xe18ee803,
- 0xe1a03823, 0xe1833802, 0xe1a02822, 0xe1822801,
- 0xe1a01821, 0xe181180e, 0xe3cee0ff, 0xe0000b95,
- 0xe00b0b97, 0xe09eb00b, 0xe0b33000, 0xe0000896,
- 0xe0b22000, 0xe0000894, 0xe0a11000, 0xe0000a94,
- 0xe00a0a96, 0xe09aa003, 0xe0b22000, 0xe2a11000,
- 0xe0000997, 0xe09a4000, 0xe0000995, 0xe0b22000,
- 0xe2b11000, 0xe8bc4209, 0x4a000005, 0xe09bb00b,
- 0xe0b44004, 0xe0b22002, 0xe0b11001, 0xe2433001,
- 0x5afffff9, 0xe0922fa4, 0xe2b11000, 0x31b0f00e,
- 0xe3a01102, 0xe2833001, 0xe1a040a4, 0xe1b0f00e,
- 0xe1a07000, 0xe1a08001, 0xe1a0a002, 0xe1a0b003,
- 0xe3a00000, 0xe3a01102, 0xe3b02100, 0xe2e23901,
- 0xe0200007, 0xe1914002, 0x1198400a, 0x0affff9d,
- 0xe043300b, 0xe2833901, 0xe2433001, 0xe3a0b000,
- 0xe052500a, 0xe0d14008, 0x23a01003, 0x2a00000c,
- 0xe1a05002, 0xe1a04001, 0xe3a01001, 0xe2433001,
- 0xe0955005, 0xe0b44004, 0xe2abb000, 0xe055700a,
- 0xe0d46008, 0x31b0b0ab, 0x21a05007, 0x21a04006,
- 0xe0a11001, 0xe0955005, 0xe0b44004, 0xe2abb000,
- 0xe055700a, 0xe0d46008, 0x31b0b0ab, 0x21a05007,
- 0x21a04006, 0xe0a11001, 0xe0955005, 0xe0b44004,
- 0xe2abb000, 0xe055700a, 0xe0d46008, 0x31b0b0ab,
- 0x21a05007, 0x21a04006, 0xe0a11001, 0xe0955005,
- 0xe0b44004, 0xe2abb000, 0xe055700a, 0xe0d46008,
- 0x31b0b0ab, 0x21a05007, 0x21a04006, 0xe0b11001,
- 0x3affffda, 0xe1942005, 0x01b0f00e, 0xe3a02001,
- 0xe0955005, 0xe0b44004, 0xe2abb000, 0xe055700a,
- 0xe0d46008, 0x31b0b0ab, 0x21a05007, 0x21a04006,
- 0xe0a22002, 0xe0955005, 0xe0b44004, 0xe2abb000,
- 0xe055700a, 0xe0d46008, 0x31b0b0ab, 0x21a05007,
- 0x21a04006, 0xe0a22002, 0xe0955005, 0xe0b44004,
- 0xe2abb000, 0xe055700a, 0xe0d46008, 0x31b0b0ab,
- 0x21a05007, 0x21a04006, 0xe0a22002, 0xe0955005,
- 0xe0b44004, 0xe2abb000, 0xe055700a, 0xe0d46008,
- 0x31b0b0ab, 0x21a05007, 0x21a04006, 0xe0b22002,
- 0x3affffda, 0xe0955005, 0xe0b44004, 0x2a000001,
- 0xe1540008, 0x0155000a, 0xe2b22000, 0xe2b11000,
- 0x31b0f00e, 0xe2a33000, 0xe3a01102, 0xe1b0f00e,
- 0xe1b04883, 0x0affff37, 0xe2833901, 0xe2433001,
- 0xe1b030a3, 0xe1a05002, 0x32414102, 0x22414101,
- 0x33a07201, 0x23a07202, 0xe3a01102, 0xe0955005,
- 0xe0b44004, 0xe0216007, 0x31540006, 0x20444006,
- 0x20211087, 0xe1b070e7, 0x5afffff7, 0xe1942005,
- 0x01b0f00e, 0xe3a02000, 0xe0955005, 0xe0b44004,
- 0xe0a00000, 0xe0226007, 0xe055a006, 0xe0d48001,
- 0x31b000a0, 0x21a0500a, 0x21a04008, 0x20222087,
- 0x20211fa7, 0xe1b070a7, 0x1afffff2, 0xe0955005,
- 0xe0b44004, 0xe0b70007, 0xe0d5a002, 0xe0d48001,
- 0x31b000a0, 0x21a0500a, 0x21a04008, 0x22222001,
- 0x23a07102, 0xe3a00000, 0xe0977007, 0xe0b55005,
- 0xe0b44004, 0x2a000002, 0xe1540001, 0x01550002,
- 0x03570101, 0xe2b22000, 0xe2b11000, 0xe2a33000,
- 0x23a01102, 0xe1b0f00e, 0xe1b07004, 0x42644000,
- 0xe3a0b901, 0xe3a0a000, 0xe1a08004, 0xe1b04828,
- 0x01a08808, 0x128bb010, 0xe1b04c28, 0x01a08408,
- 0x128bb008, 0xe1b04e28, 0x01a08208, 0x128bb004,
- 0xe1b04f28, 0x01a08108, 0x128bb002, 0xe1b04fa8,
- 0x01a08088, 0x024bb001, 0xe1b0f00e, 0xe1a07000,
- 0xe1a0b003, 0xe24b40fe, 0xe2544c3f, 0xda000011,
- 0xe2745020, 0x4a000003, 0xe3a0a000, 0xe1a08531,
- 0xe1a08518, 0xe1b0f00e, 0xe1a08001, 0xe1a0a002,
- 0xe2745040, 0x41b0f00e, 0xe1a0a53a, 0xe1a0a51a,
- 0xe1b0f00e, 0x03a04001, 0x03a08102, 0xe3a0a000,
- 0x028bb001, 0x01b0f00e, 0xe3a04000, 0xe3a08000,
- 0xe3a0a000, 0xe3a0b000, 0xe1b0f00e, 0xe1a07000,
- 0xe1a0b003, 0xe24b40fe, 0xe2544c3f, 0xdafffff0,
- 0xe2745020, 0x4a000007, 0xe3a0a000, 0xe1b04531,
- 0xe2a44000, 0xe1b08514, 0x31b0f00e, 0xe1a08068,
- 0xe28bb001, 0xe1b0f00e, 0xe1a08001, 0xe1a0a002,
- 0xe2745040, 0xe3e04000, 0x41b0f00e, 0xe1b0a53a,
- 0xe2aaa000, 0xe1b0a51a, 0xe2b88000, 0x31b0f00e,
- 0xe1a0a0aa, 0xe18aaf88, 0xe1a08068, 0xe28bb001,
- 0xe1b0f00e, 0xe38ee101, 0xe24340fe, 0xe2544c3f,
- 0xda000032, 0xe2745020, 0x4a000018, 0xe1a08411,
- 0x01a08002, 0x11a0a002, 0x03a0a000, 0xe3a02000,
- 0xe1a01531, 0xe2194060, 0x1a000007, 0xe19aa088,
- 0x00088f81, 0xe0911fa8, 0x31b01511, 0x31b0f00e,
- 0xe1a01061, 0xe2833001, 0xe1b0f00e, 0xe3540060,
- 0x1198a00a, 0x0a000003, 0xe0304d04, 0x5a000001,
- 0xe2911001, 0xeafffff3, 0xe1a01511, 0xe1b0f00e,
- 0xe2745040, 0xd1b0f00e, 0xe2444020, 0xe1a08412,
- 0xe1b02532, 0xe2194060, 0x1a00000a, 0xe1b0a088,
- 0x00088f82, 0xe0822fa8, 0xe1b02512, 0xe2b11000,
- 0x31b0f00e, 0xe1a020a2, 0xe1822f81, 0xe1a01061,
- 0xe2833001, 0xe1b0f00e, 0xe3540060, 0x13580000,
- 0x0afffff4, 0xe0304d04, 0x42822001, 0xeafffff1,
- 0x0a000011, 0xe2194060, 0x1a000006, 0xe1918002,
- 0x01b0f00e, 0xe3a01000, 0xe3a02000, 0xe3a03000,
- 0xe3a04008, 0xe1a0f00e, 0xe1918002, 0x13540060,
- 0x0afffff5, 0xe0304d04, 0x5afffff3, 0xe3a01102,
- 0xe3b02100, 0xe2e23901, 0xe1b0f00e, 0xe2194060,
- 0x1afffff4, 0xe1924081, 0x1afffff7, 0xeaffffea,
- 0xe1a04000, 0xe1a00007, 0xe1a07004, 0xe1a04001,
- 0xe1a01008, 0xe1a08004, 0xe1a04002, 0xe1a0200a,
- 0xe1a0a004, 0xe1a04003, 0xe1a0300b, 0xe1a0b004,
- 0xe1b0f00e, 0xe209ba07, 0xe08c542b, 0xe209780f,
- 0xe79da727, 0xe21980ff, 0xe04a8108, 0x178d8727,
- 0xe2199902, 0xe3899901, 0xe1a09789, 0xe4ba6004,
- 0x14ba7004, 0xe88503c0, 0xeafffcae, 0xe209ba07,
- 0xe08c542b, 0xe209780f, 0xe79da727, 0xe21980ff,
- 0xe04a8108, 0x178d8727, 0xe2199902, 0xe3899905,
- 0xe1a09789, 0xe4ba6004, 0xe4ba7004, 0xe4ba8000,
- 0xe88503c0, 0xeafffc9f, 0xe209ba07, 0xe08c542b,
- 0xe209780f, 0xe79da727, 0xe21980ff, 0xe08a8108,
- 0x178d8727, 0xe2199902, 0xe3899901, 0xe1a09789,
- 0xe4ba6004, 0x14ba7004, 0xe88503c0, 0xeafffc91,
- 0xe209ba07, 0xe08c542b, 0xe209780f, 0xe79da727,
- 0xe21980ff, 0xe08a8108, 0x178d8727, 0xe2199902,
- 0xe3899905, 0xe1a09789, 0xe4ba6004, 0xe4ba7004,
- 0xe4ba8000, 0xe88503c0, 0xeafffc82, 0xe209ba07,
- 0xe08cc42b, 0xe209780f, 0xe337080f, 0x179da727,
- 0xe21980ff, 0xe04aa108, 0xe2199902, 0xe3899901,
- 0xe1a0b789, 0xe4ba8004, 0x14ba9004, 0xe88c0f00,
- 0xeafffc83, 0xe209ba07, 0xe08c542b, 0xe209780f,
- 0xe79da727, 0xe21980ff, 0xe04aa108, 0x178da727,
- 0xe2199902, 0xe3899901, 0xe1a09789, 0xe4ba6004,
- 0x14ba7004, 0xe88503c0, 0xeafffc66, 0xe209ba07,
- 0xe08cc42b, 0xe209780f, 0xe337080f, 0x179da727,
- 0xe21980ff, 0xe04aa108, 0xe2199902, 0xe3899905,
- 0xe1a0b789, 0xe4ba8004, 0xe4ba9004, 0xe4baa000,
- 0xe88c0f00, 0xeafffc66, 0xe209ba07, 0xe08c542b,
- 0xe209780f, 0xe79da727, 0xe21980ff, 0xe04aa108,
- 0x178da727, 0xe2199902, 0xe3899905, 0xe1a09789,
- 0xe4ba6004, 0xe4ba7004, 0xe4ba8000, 0xe88503c0,
- 0xeafffc48, 0xe209ba07, 0xe08cc42b, 0xe209780f,
- 0xe337080f, 0x179da727, 0xe21980ff, 0xe08aa108,
- 0xe2199902, 0xe3899901, 0xe1a0b789, 0xe4ba8004,
- 0x14ba9004, 0xe88c0f00, 0xeafffc49, 0xe209ba07,
- 0xe08c542b, 0xe209780f, 0xe79da727, 0xe21980ff,
- 0xe08aa108, 0x178da727, 0xe2199902, 0xe3899901,
- 0xe1a09789, 0xe4ba6004, 0x14ba7004, 0xe88503c0,
- 0xeafffc2c, 0xe209ba07, 0xe08cc42b, 0xe209780f,
- 0xe337080f, 0x179da727, 0xe21980ff, 0xe08aa108,
- 0xe2199902, 0xe3899905, 0xe1a0b789, 0xe4ba8004,
- 0xe4ba9004, 0xe4baa000, 0xe88c0f00, 0xeafffc2c,
- 0xe209ba07, 0xe08c542b, 0xe209780f, 0xe79da727,
- 0xe21980ff, 0xe08aa108, 0x178da727, 0xe2199902,
- 0xe3899905, 0xe1a09789, 0xe4ba6004, 0xe4ba7004,
- 0xe4ba8000, 0xe88503c0, 0xeafffc0e, 0xe2095a07,
- 0xe08c5425, 0xe895000f, 0xe3a04002, 0xe0044729,
- 0xe3844001, 0xe1340ea3, 0xe1844d23, 0xe28f7004,
- 0xe28f5f6f, 0x1085f104, 0xe209780f, 0xe79da727,
- 0xe21980ff, 0xe04a8108, 0x178d8727, 0xe4aa0004,
- 0xe3130101, 0x14aa1000, 0xeafffbfa, 0xe2095a07,
- 0xe08c5425, 0xe895000f, 0xe3a04002, 0xe0044729,
- 0xe3844005, 0xe1340ea3, 0xe1844d23, 0xe28f7004,
- 0xe28f5f5b, 0x1085f104, 0xe209780f, 0xe79da727,
- 0xe21980ff, 0xe04a8108, 0x178d8727, 0xe4aa0004,
- 0xe4aa1004, 0xe4aa2000, 0xeafffbe6, 0xe2095a07,
- 0xe08c5425, 0xe895000f, 0xe3a04002, 0xe0044729,
- 0xe3844001, 0xe1340ea3, 0xe1844d23, 0xe28f7004,
- 0xe28f5f47, 0x1085f104, 0xe209780f, 0xe79da727,
- 0xe21980ff, 0xe08a8108, 0x178d8727, 0xe4aa0004,
- 0xe3130101, 0x14aa1000, 0xeafffbd2, 0xe2095a07,
- 0xe08c5425, 0xe895000f, 0xe3a04002, 0xe0044729,
- 0xe3844005, 0xe1340ea3, 0xe1844d23, 0xe28f7004,
- 0xe28f50cc, 0x1085f104, 0xe209780f, 0xe79da727,
- 0xe21980ff, 0xe08a8108, 0x178d8727, 0xe4aa0004,
- 0xe4aa1004, 0xe4aa2000, 0xeafffbbe, 0xe2095a07,
- 0xe08c5425, 0xe895000f, 0xe3a04002, 0xe0044729,
- 0xe3844001, 0xe1340ea3, 0xe1844d23, 0xe28f7004,
- 0xe28f507c, 0x1085f104, 0xe209780f, 0xe337080f,
- 0x179da727, 0xe21980ff, 0xe04aa108, 0xe4aa0004,
- 0xe3130101, 0x14aa1000, 0xeafffbb2, 0xe2095a07,
- 0xe08c5425, 0xe895000f, 0xe3a04002, 0xe0044729,
- 0xe3844001, 0xe1340ea3, 0xe1844d23, 0xe28f7004,
- 0xe28f502c, 0x1085f104, 0xe209780f, 0xe79da727,
- 0xe21980ff, 0xe04aa108, 0x178da727, 0xe4aa0004,
- 0xe3130101, 0x14aa1000, 0xeafffb96, 0xe08ff104,
- 0xeb00036b, 0xe1a0f007, 0xea0000b6, 0xeb000368,
- 0xea0000ea, 0xeb000366, 0xea000123, 0xeb000364,
- 0xea0001ca, 0xea000124, 0xe1a0f007, 0xeb000360,
- 0xea000134, 0xeb00035e, 0xea00014b, 0xeb00035c,
- 0xea0001bd, 0xeb00035a, 0xeb000359, 0xeb000358,
- 0xeb000357, 0xeb000356, 0xeb000355, 0xeb000354,
- 0xeb000353, 0xea000156, 0xea00016f, 0xeb000350,
- 0xe1a0f007, 0xeb00034e, 0xea00018c, 0xeb00034c,
- 0xea0001ad, 0xeb00034a, 0xeb000349, 0xeb000348,
- 0xeb000347, 0xeb000346, 0xeb000345, 0xeb000344,
- 0xeb000343, 0xea00019f, 0xea00008d, 0xeb000340,
- 0xea0000c1, 0xeb00033e, 0xe1a0f007, 0xeb00033c,
- 0xea00019d, 0xeb00033a, 0xeb000339, 0xeb000338,
- 0xeb000337, 0xeb000336, 0xeb000335, 0xeb000334,
- 0xeb000333, 0xea00024f, 0xea00024e, 0xeb000330,
- 0xea00024c, 0xeb00032e, 0xea00024a, 0xeb00032c,
- 0xe1a0f007, 0xe2095a07, 0xe08c5425, 0xe895000f,
- 0xe3a04002, 0xe0044729, 0xe3844005, 0xe1340ea3,
- 0xe1844d23, 0xe28f7004, 0xe24f5f4b, 0x1085f104,
- 0xe209780f, 0xe337080f, 0x179da727, 0xe21980ff,
- 0xe04aa108, 0xe4aa0004, 0xe4aa1004, 0xe4aa2004,
- 0xeafffb48, 0xe2095a07, 0xe08c5425, 0xe895000f,
- 0xe3a04002, 0xe0044729, 0xe3844005, 0xe1340ea3,
- 0xe1844d23, 0xe28f7004, 0xe24f5f5f, 0x1085f104,
- 0xe209780f, 0xe79da727, 0xe21980ff, 0xe04aa108,
- 0x178da727, 0xe4aa0004, 0xe4aa1004, 0xe4aa2000,
- 0xeafffb2c, 0xe2095a07, 0xe08c5425, 0xe895000f,
- 0xe3a04002, 0xe0044729, 0xe3844001, 0xe1340ea3,
- 0xe1844d23, 0xe28f7004, 0xe24f5f73, 0x1085f104,
- 0xe209780f, 0xe337080f, 0x179da727, 0xe21980ff,
- 0xe08aa108, 0xe4aa0004, 0xe3130101, 0x14aa1000,
- 0xeafffb20, 0xe2095a07, 0xe08c5425, 0xe895000f,
- 0xe3a04002, 0xe0044729, 0xe3844001, 0xe1340ea3,
- 0xe1844d23, 0xe28f7004, 0xe24f5f87, 0x1085f104,
- 0xe209780f, 0xe79da727, 0xe21980ff, 0xe08aa108,
- 0x178da727, 0xe4aa0004, 0xe3130101, 0x14aa1000,
- 0xeafffb04, 0xe2095a07, 0xe08c5425, 0xe895000f,
- 0xe3a04002, 0xe0044729, 0xe3844005, 0xe1340ea3,
- 0xe1844d23, 0xe28f7004, 0xe24f5f9b, 0x1085f104,
- 0xe209780f, 0xe337080f, 0x179da727, 0xe21980ff,
- 0xe08aa108, 0xe4aa0004, 0xe4aa1004, 0xe4aa2004,
- 0xeafffaf8, 0xe2095a07, 0xe08c5425, 0xe895000f,
- 0xe3a04002, 0xe0044729, 0xe3844005, 0xe1340ea3,
- 0xe1844d23, 0xe28f7004, 0xe24f5faf, 0x1085f104,
- 0xe209780f, 0xe79da727, 0xe21980ff, 0xe08aa108,
- 0x178da727, 0xe4aa0004, 0xe4aa1004, 0xe4aa2000,
- 0xeafffadc, 0xe3c03102, 0xe2000102, 0xe1b05883,
- 0x12955802, 0x0a00000e, 0xe3320000, 0x01922c81,
- 0xe2012080, 0x000220a1, 0xe0911002, 0x31a01081,
- 0xe2a33000, 0xe2533dfe, 0x9a00001c, 0xe35300ff,
- 0x31800b83, 0x318004a1, 0x33a03202, 0x31a0f007,
- 0xea000008, 0xe1b04c03, 0xe18000a4, 0xe3a03202,
- 0x13c11102, 0x11800421, 0x11a0f007, 0xe1922001,
- 0x01a0f007, 0xea000015, 0xe380047f, 0xe3800502,
- 0xe3a03202, 0xe3a04004, 0xe59c5080, 0xe1855004,
- 0xe58c5080, 0xe1140825, 0x11a00004, 0x1a000e8a,
- 0xe3540004, 0x11a0f007, 0xe3a04010, 0xeafffff5,
- 0xe3730017, 0xda000005, 0xe1a01521, 0xe3811501,
- 0xe2633000, 0xe1800331, 0xe3a03202, 0xe1a0f007,
- 0xe3a03202, 0xe3a04008, 0xeaffffea, 0xe3c03102,
- 0xe2000102, 0xe1b05883, 0x12955802, 0x0a000012,
- 0xe1b04b02, 0xe2024b01, 0x000440a2, 0xe0922004,
- 0xe2b11000, 0xe2a33000, 0xe0922002, 0xe0a11001,
- 0xe2533b0f, 0x9a000019, 0xe2834001, 0xe3540b02,
- 0x31800a03, 0x31800621, 0x31a01a01, 0x31811622,
- 0x33a03206, 0x31a0f007, 0xea00000a, 0xe1b04a83,
- 0xe18000a4, 0xe3a03206, 0x13c11102, 0x118005a1,
- 0x11a01a81, 0x118115a2, 0x11a0f007, 0xe1922001,
- 0x01a0f007, 0xea000014, 0xe380047f, 0xe380060f,
- 0xe3a01000, 0xe3a03206, 0xe3a04004, 0xeaffffc1,
- 0xe3730034, 0xda00000c, 0xe1a026a2, 0xe1822981,
- 0xe1a016a1, 0xe3811702, 0xe2633000, 0xe2534020,
- 0x21a01431, 0x32634020, 0x31800331, 0x31a01411,
- 0x31811332, 0xe3a03206, 0xe1a0f007, 0xe3a01000,
- 0xe3a03206, 0xe3a04008, 0xeaffffae, 0xe2000102,
- 0xe1800003, 0xe3a0320a, 0xe1a0f007, 0xe3a02000,
- 0xe1a03080, 0xe1b03c23, 0x133300ff, 0x11a01400,
- 0x13811102, 0x12833dfe, 0x11a0f007, 0xe1933383,
- 0x11a01400, 0x13c11102, 0x11a0f007, 0xe1b01480,
- 0x01a0f007, 0xe3a03dfe, 0x52433001, 0x51b01081,
- 0x5afffffc, 0xe1a0f007, 0xe1a01e80, 0xe3c03102,
- 0xe2000102, 0xe18001a3, 0xe3a03206, 0xe21026ff,
- 0x133206ff, 0x1280030e, 0x11a0f007, 0xe1800182,
- 0xe3320000, 0x11a0f007, 0xe1912600, 0x01a0f007,
- 0xe1a01a21, 0xe1911600, 0xe2000102, 0xe380030e,
- 0x52400601, 0x51b01081, 0x5afffffc, 0xe1a01081,
- 0xe1800621, 0xe1a01a01, 0xe1a0f007, 0xe3a02000,
- 0xe1a03080, 0xe1b03c23, 0x133300ff, 0xe1a01400,
- 0x13811102, 0x12833dfe, 0xe2000102, 0xe1800003,
- 0xe3a0320a, 0x11a0f007, 0xe1800380, 0xe31000ff,
- 0x13c11102, 0x11a0f007, 0xe1b01081, 0x01a0f007,
- 0xe3800dfe, 0x52400001, 0x51b01081, 0x5afffffc,
- 0xe1a0f007, 0xe1a03080, 0xe1b03aa3, 0x12834001,
- 0x13340b02, 0xe1a02581, 0xe1a01aa1, 0xe1811580,
- 0x13811102, 0x12833b0f, 0x11a0f007, 0xe1933203,
- 0x11a0f007, 0xe0922002, 0xe0a11001, 0xe1924001,
- 0x01a0f007, 0xe3a03b0f, 0xe1b01001, 0x52433001,
- 0xe3a04000, 0x51844fa2, 0x51844081, 0x51a02082,
- 0x51b01004, 0x5afffff8, 0xe1a0f007, 0xe1a03080,
- 0xe1b03aa3, 0x12834001, 0x13340b02, 0x0a00000f,
- 0xe1b04201, 0xe1a01a21, 0xe1811600, 0xe2014c01,
- 0x000440a1, 0xe0911004, 0xe2a33000, 0xe2000102,
- 0xe2533d0e, 0x9affff49, 0xe35300ff, 0x31800b83,
- 0x318004a1, 0x33a03202, 0x31a0f007, 0xeaffff35,
- 0xe1812600, 0xe1a01a21, 0xe1811600, 0xe2000102,
- 0xe1b04c03, 0xe18000a4, 0xe3a03202, 0x118004a1,
- 0x11a0f007, 0xe3320000, 0x01a0f007, 0xeaffff3f,
- 0xe1a03080, 0xe1b03aa3, 0x12834001, 0x13340b02,
- 0xe1a02581, 0xe1a01aa1, 0xe1811580, 0x13811102,
- 0x12833b0f, 0xe2000102, 0xe1800003, 0xe3a0320a,
- 0x11a0f007, 0xe1800200, 0xe31000ff, 0x11a0f007,
- 0xe0922002, 0xe0a11001, 0xe1924001, 0x01a0f007,
- 0xe3800b0f, 0xe1b01001, 0x52400001, 0xe3a04000,
- 0x51844fa2, 0x51844081, 0x51a02082, 0x51b01004,
- 0x5afffff8, 0xe1a0f007, 0xe3c03102, 0xe1a0f007,
- 0x9a209a84, 0xfbcff799, 0x00003ffd, 0xe92c0080,
- 0xe28f7004, 0xe3c44007, 0xeafffe2b, 0xe8bc0080,
- 0xe1b05883, 0x12955802, 0x0a000099, 0xe3a05901,
- 0xe2455001, 0xe1530005, 0x3a000006, 0xe2855003,
- 0xe1530005, 0x0351020a, 0x33a04000, 0x33a05000,
- 0x392c4ff0, 0x3a000021, 0xe92c4fcf, 0xe3a00902,
- 0xe2404003, 0xe0644083, 0xebfffc46, 0xe24bb001,
- 0xe24f4078, 0xe894000e, 0xebfffb4b, 0xe3a04901,
- 0xe2444002, 0xe0434004, 0xe2644020, 0xe1a09431,
- 0xe1510419, 0x03520000, 0x1210b102, 0x12899001,
- 0xe200b102, 0xe8bc000f, 0xe92c0a00, 0xeb0000bf,
- 0xe59c4004, 0xe1b04004, 0x5bfffb90, 0x4bfffb3a,
- 0xe3a05901, 0xe2455001, 0xe1530005, 0x3a000051,
- 0xe2855003, 0xe1530005, 0x0351020a, 0x2a000040,
- 0xe3a04901, 0xe2844002, 0xe0544003, 0xe2645020,
- 0xe1a03512, 0x11a02432, 0x11822511, 0x11a01431,
- 0xe1a04e21, 0xe3a07003, 0xe3c1120f, 0xe0933003,
- 0xe0b22002, 0xe0a11001, 0xe1a08101, 0xe1888f22,
- 0xe1a0a102, 0xe18aaf23, 0xe092200a, 0xe0a11008,
- 0xe2577001, 0x11a04204, 0x11844e21, 0x1afffff1,
- 0xe1915002, 0x03a06000, 0x0a000019, 0xe3a0700f,
- 0xe1a05205, 0xe1855e26, 0xe1a06206, 0xe1866e21,
- 0xe3c1120f, 0xe0922002, 0xe0a11001, 0xe1a08101,
- 0xe1888f22, 0xe0922102, 0xe0a11008, 0xe2577001,
- 0x1afffff2, 0xe1a05205, 0xe1855e26, 0xe1a06206,
- 0xe1866e21, 0xe1b01281, 0x3a000005, 0xe2866001,
- 0xe1911002, 0x03c66001, 0xe206100f, 0xe351000a,
- 0x02466001, 0xe8bc0008, 0xeb000023, 0xe2000102,
- 0xe1800221, 0xe8bc0080, 0xe18000a7, 0xe1800004,
- 0xe1a01005, 0xe1a02006, 0xe3a0320e, 0xe8bc4fc0,
- 0xe1a0f007, 0xe8bc0030, 0xe3150102, 0x12644000,
- 0xe2844001, 0xe2145102, 0x12644000, 0xe92c0030,
- 0xe3a07901, 0xe3a0820a, 0xe3a0a000, 0xe287b002,
- 0xebfffb3a, 0xeaffffb1, 0xe8bc0030, 0xe3150102,
- 0x12644000, 0xe2444001, 0xe2145102, 0x12644000,
- 0xe92c0030, 0xe3a07901, 0xe3a0820a, 0xe3a0a000,
- 0xe287b002, 0xebfffad8, 0xeaffffa4, 0xe1a02003,
- 0xe3a03010, 0xe0922002, 0x3352020a, 0x2242220a,
- 0xe0b33003, 0x3afffffa, 0xe1a01622, 0xe3530064,
- 0xa2433064, 0xa2811201, 0xaafffffb, 0xe353000a,
- 0xa243300a, 0xa2811401, 0xaafffffb, 0xe1811a03,
- 0xe1b0f00e, 0xe3530000, 0x1a00000a, 0xe1915002,
- 0x03a0320e, 0x03a00000, 0x01a0f007, 0xe3110102,
- 0x1affff5d, 0xe0922002, 0xe0b11001, 0xe2433001,
- 0x5afffffb, 0xeaffff58, 0xe2000102, 0xe1800603,
- 0xe3800302, 0xe18009a1, 0xe1a01681, 0xe18119a2,
- 0xe1a02682, 0xe3a0320e, 0xe1a0f007, 0x9392ee8e,
- 0x921d5d07, 0x00003fc3, 0xe1915002, 0x01b05a00,
- 0x1200540f, 0x1355040f, 0x0a0000ac, 0xe92c4fd0,
- 0xe3a07000, 0xe3a06000, 0xe1a04a00, 0xe3a05003,
- 0xeb00009a, 0xe1a04001, 0xe3a05008, 0xeb000097,
- 0xe1a04002, 0xe3a05008, 0xeb000094, 0xe1a02007,
- 0xe1b01006, 0xe3a0303e, 0xe2833901, 0x4a000003,
- 0xe0922002, 0xe0b11001, 0xe2433001, 0x5afffffb,
- 0xe3a06000, 0xe3a07000, 0xe1a04200, 0xe3a05004,
- 0xeb000086, 0xe1a09007, 0xeb00000c, 0xe3100101,
- 0x1bfffade, 0x0bfffa88, 0xe24f70a4, 0xe8970d00,
- 0xebfffa85, 0xe8bc4fd0, 0xe2935001, 0xda000090,
- 0xe1b057a5, 0x1a0000a7, 0xe2044007, 0xeafffd46,
- 0xe3590014, 0xd28f8084, 0xd0889209, 0xd8990d80,
- 0xd1b0f00e, 0xe92c400f, 0xe3a01102, 0xe3a02000,
- 0xe3a00901, 0xe2403001, 0xe3590000, 0x0a000011,
- 0xe92c000f, 0xe2833003, 0xe3b0120a, 0x3bfffa6a,
- 0xe1b090a9, 0x3afffffc, 0xe8bc0d80, 0x192c000f,
- 0xebfffa69, 0x0a000007, 0xe8bc0d80, 0xe92c000f,
- 0xe1a00007, 0xe1a01008, 0xe1a0200a, 0xe1a0300b,
- 0xebfffa61, 0xeafffff1, 0xe1a07000, 0xe1a08001,
- 0xe1a0a002, 0xe1a0b003, 0xe8bc400f, 0xe1b0f00e,
- 0x00000000, 0x80000000, 0x00000000, 0x00003fff,
- 0x00000000, 0xa0000000, 0x00000000, 0x00004002,
- 0x00000000, 0xc8000000, 0x00000000, 0x00004005,
- 0x00000000, 0xfa000000, 0x00000000, 0x00004008,
- 0x00000000, 0x9c400000, 0x00000000, 0x0000400c,
- 0x00000000, 0xc3500000, 0x00000000, 0x0000400f,
- 0x00000000, 0xf4240000, 0x00000000, 0x00004012,
- 0x00000000, 0x98968000, 0x00000000, 0x00004016,
- 0x00000000, 0xbebc2000, 0x00000000, 0x00004019,
- 0x00000000, 0xee6b2800, 0x00000000, 0x0000401c,
- 0x00000000, 0x9502f900, 0x00000000, 0x00004020,
- 0x00000000, 0xba43b740, 0x00000000, 0x00004023,
- 0x00000000, 0xe8d4a510, 0x00000000, 0x00004026,
- 0x00000000, 0x9184e72a, 0x00000000, 0x0000402a,
- 0x00000000, 0xb5e620f4, 0x80000000, 0x0000402d,
- 0x00000000, 0xe35fa931, 0xa0000000, 0x00004030,
- 0x00000000, 0x8e1bc9bf, 0x04000000, 0x00004034,
- 0x00000000, 0xb1a2bc2e, 0xc5000000, 0x00004037,
- 0x00000000, 0xde0b6b3a, 0x76400000, 0x0000403a,
- 0x00000000, 0x8ac72304, 0x89e80000, 0x0000403e,
- 0x00000000, 0xad78ebc5, 0xac620000, 0x00004041,
- 0xe0977007, 0xe0a66006, 0xe0978107, 0xe0a6af27,
- 0xe08a6106, 0xe1a07008, 0xe0977e24, 0xe2a66000,
- 0xe1a04204, 0xe2555001, 0x1afffff4, 0xe1b0f00e,
- 0xe1a03280, 0xe1a038a3, 0xe1a026a2, 0xe1822981,
- 0xe1a016a1, 0xe1811980, 0xe3c11102, 0xe2044007,
- 0xeafffcb9, 0xe2144007, 0x13540005, 0x0a000003,
- 0xe2000102, 0xe3540001, 0x0afffda0, 0xeafffdda,
- 0xe2633000, 0xe3530040, 0xaa000008, 0xe2735020,
- 0x42435020, 0x41a02531, 0x51a02332, 0x51822511,
- 0xe1a01331, 0xe3a03000, 0xe2044007, 0xeafffca6,
- 0xe2000102, 0xe3a01000, 0xe3a02000, 0xe1a03e84,
- 0xe3a04008, 0xeafffd7b, 0xe2144007, 0x0a000003,
- 0xe3a00000, 0xe3540003, 0x0afffdae, 0xbafffd71,
- 0xe3a01000, 0xe3b02100, 0xe2e23902, 0xe2000102,
- 0xe1800003, 0xe3540000, 0x13a0320a, 0xe3a04004,
- 0xeafffd6c, 0xeafffffe, 0xe209aa0f, 0xe3190008,
- 0x1a000069, 0xe2095007, 0xe08c5205, 0xe895000f,
- 0xe1b04d23, 0xe28f7000, 0x1afffc87, 0xe1b04883,
- 0x12944802, 0x0a00002b, 0x5a000039, 0xe354083e,
- 0xe20448ff, 0x4a000049, 0xe1a048a4, 0xe2199060,
- 0x1a00000e, 0xe2846002, 0xe1922611, 0xe3a02101,
- 0xe0012432, 0x000220a1, 0xe264401f, 0xe1a01431,
- 0xe3320000, 0x12811001, 0xe3100102, 0x12611000,
- 0xe0312000, 0x4a000049, 0xe78d152a, 0xeafff805,
- 0xe3590060, 0x1a000005, 0xe264401f, 0xe1a01431,
- 0xe3100102, 0x12611000, 0xe78d152a, 0xeafff7fd,
- 0xe0307d09, 0x5afffff7, 0xe2846001, 0xe1922611,
- 0x0afffff4, 0xe264401f, 0xe1a01431, 0xe2811001,
- 0xe3100102, 0x12611000, 0xe0312000, 0x4a000033,
- 0xe78d152a, 0xeafff7ef, 0xe31300ff, 0x1a000003,
- 0xe1921001, 0x1a000006, 0xe78d152a, 0xeafff7e9,
- 0xe1921001, 0x0a000029, 0xe28f70bc, 0xe3a04001,
- 0xeafffd28, 0xe02970a9, 0xe3170020, 0x0a000010,
- 0xea000003, 0xe2199060, 0x0a000008, 0xe3590060,
- 0x0a00000b, 0xe0307d09, 0x5a000009, 0xe3a01001,
- 0xe3100102, 0x12611000, 0xe78d152a, 0xeafff7d5,
- 0xe2947802, 0x5a000002, 0xe3510102, 0x03520000,
- 0x8afffff5, 0xe3a01000, 0xe78d152a, 0xea000016,
- 0xe354083e, 0x03510102, 0xe2000102, 0x03500102,
- 0x1a00000a, 0xe3520000, 0x0affffae, 0xe2199060,
- 0x0a000004, 0xe3590060, 0x0affffaa, 0xe0307d09,
- 0x5affffa8, 0xea000001, 0xe3520102, 0x9affffa5,
- 0xe28f7014, 0xe3a04001, 0xeafffcfe, 0xe2091007,
- 0xe3510006, 0xaa000001, 0xe78d152a, 0xeafff7b5,
- 0xe2811003, 0xe351000a, 0x13a01001, 0xe2099060,
- 0x13590020, 0x1affffde, 0xe78d152a, 0xeafff7ad,
- 0xe3190080, 0x1a000034, 0xe2097a0f, 0xe79d8527,
- 0xe209b807, 0xe08cb62b, 0xe1b07008, 0x42688000,
- 0xe3a0a09e, 0xe28aadfe, 0x03a0a01f, 0xe1b0c828,
- 0x01a08808, 0x024aa010, 0xe1b0cc28, 0x01a08408,
- 0x024aa008, 0xe1b0ce28, 0x01a08208, 0x024aa004,
- 0xe1b0cf28, 0x01a08108, 0x024aa002, 0xe1b0cfa8,
- 0x01a08088, 0x024aa001, 0xe1b0cc08, 0x1a000002,
- 0xe3a09000, 0xe88b0780, 0xeafff79d, 0xe2199060,
- 0x1a000008, 0xe1b0c08c, 0xe208c080, 0x000cc0a8,
- 0xe098800c, 0xe2aaa000, 0x23a08102, 0xe3c880ff,
- 0xe88b0780, 0xeafff792, 0xe2399060, 0x0afffffa,
- 0xe027cc89, 0xe20cc102, 0xe0988bac, 0xe2aaa000,
- 0x23a08102, 0xe3a09000, 0xe3c880ff, 0xe88b0780,
- 0xeafff787, 0xe3190080, 0x1afff75f, 0xe2097a0f,
- 0xe79d8527, 0xe209b807, 0xe08cb62b, 0xe1b07008,
- 0x42688000, 0xe3a0a09e, 0xe28aadfe, 0x03a0a01f,
- 0xe1b09828, 0x01a08808, 0x024aa010, 0xe1b09c28,
- 0x01a08408, 0x024aa008, 0xe1b09e28, 0x01a08208,
- 0x024aa004, 0xe1b09f28, 0x01a08108, 0x024aa002,
- 0xe1b09fa8, 0x01a08088, 0x024aa001, 0xe3a09000,
- 0xe88b0780, 0xeafff76a, 0xe2097a0f, 0xe79da527,
- 0xe3ca801f, 0xe3d8881f, 0x1a000002, 0xe38aa000,
- 0xe58ca080, 0xeafff762, 0xe24f700c, 0xe3a04001,
- 0xeafffc94, 0xe2097a0f, 0xe59ca080, 0xe78da527,
- 0xeafff74c, 0xe1b08e09, 0x4a000037, 0xe08c8c28,
- 0xe898000f, 0xe1b04d23, 0xe28f7000, 0x1afffbae,
- 0xe2097807, 0xe1a0b003, 0xe1a0a002, 0xe0208509,
- 0xe1a09001, 0xe08cc627, 0xe89c000f, 0xe1b04d23,
- 0xe28f7000, 0x1afffba4, 0x188c000f, 0xe3a04803,
- 0xe0945883, 0x3094588b, 0x2a000015, 0xe0305008,
- 0x4a000009, 0xe153000b, 0x01510009, 0x0152000a,
- 0xe10f7000, 0xe2077206, 0x33877102, 0x13100102,
- 0x1227720a, 0xe168f007, 0xeafff72a, 0xe19b4003,
- 0x019a4002, 0x01994001, 0x0a000003, 0xe3100102,
- 0x1368f102, 0x0368f202, 0xeafff722, 0xe368f206,
- 0xeafff720, 0xe0945883, 0x3a000001, 0xe1915002,
- 0x1a000003, 0xe094588b, 0x3affffe3, 0xe199500a,
- 0x0affffe1, 0xe368f201, 0xe24fc0c0, 0xe24ccc24,
- 0xe24f7038, 0xe3a04001, 0xeafffc56, 0xe2097807,
- 0xe2095602, 0xe24f6074, 0xe0866c28, 0xe8960f00,
- 0xe0288505, 0xeaffffca, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x80000000,
- 0x00000000, 0x00003fff, 0x00000000, 0x80000000,
- 0x00000000, 0x00004000, 0x00000000, 0xc0000000,
- 0x00000000, 0x00004000, 0x00000000, 0x80000000,
- 0x00000000, 0x00004001, 0x00000000, 0xa0000000,
- 0x00000000, 0x00004001, 0x00000000, 0x80000000,
- 0x00000000, 0x00003ffe, 0x00000000, 0xa0000000,
- 0x00000000, 0x00004002, 0xe2097807, 0xe2095602,
- 0xe24f6e11, 0xe0866c28, 0xe8960f00, 0xe0288505,
- 0xea00000b, 0xe1b08e09, 0x4afffff6, 0xe08c8c28,
- 0xe898000f, 0xe1b04d23, 0xe28f7000, 0x1afffb46,
- 0xe2097807, 0xe1a0b003, 0xe1a0a002, 0xe0208509,
- 0xe1a09001, 0xe08cc627, 0xe89c000f, 0xe1b04d23,
- 0xe28f7000, 0x1afffb3c, 0x188c000f, 0xe3a04803,
- 0xe0945883, 0x3094588b, 0x2a00000b, 0xe0305008,
- 0x4affffa1, 0xe153000b, 0x01510009, 0x0152000a,
- 0xe10f7000, 0xe2077206, 0x33877102, 0x13100102,
- 0x1227720a, 0xe168f007, 0xeafff6c2, 0xe0945883,
- 0x3a000001, 0xe1915002, 0x1a000003, 0xe094588b,
- 0x3affffed, 0xe199500a, 0x0affffeb, 0xe368f201,
- 0xeafff6b8, 0xe2099060, 0xe3590020, 0x03a07209,
- 0x0a000006, 0xe3a00000, 0xe08cb42a, 0xe28f708c,
- 0xe2877c05, 0xea0000de, 0xe357020e, 0x0afffff4,
- 0xe24f8c02, 0xe0887c27, 0xe08cb42a, 0xe8970780,
- 0xe88b0780, 0xeafff6b6, 0xe24f8f85, 0xe0887c27,
- 0xe08cb42a, 0xe8970700, 0xe3a07102, 0xe88b0780,
- 0xeafff6af, 0xe24f7e23, 0xe0878c28, 0xe8980d00,
- 0xe3a04000, 0xea0001f3, 0xe24f7f91, 0xe0878c28,
- 0xe8980d00, 0xe3a04000, 0xea0002a5, 0xe3580102,
- 0x0a00040f, 0xe24f7e26, 0xe0878c28, 0xe8980d00,
- 0xea00035f, 0xe3580102, 0x0a00050f, 0xe24f7f9e,
- 0xe0878c28, 0xe8980d00, 0xea000456, 0xe24f7fa3,
- 0xe0876c26, 0xe896000f, 0xea000463, 0xe3580102,
- 0x0a0005b3, 0xe24f7e2a, 0xe0878c28, 0xe8980d00,
- 0xea000546, 0xe24f7fad, 0xe0876c26, 0xe896000f,
- 0xea000549, 0xe24f8fb1, 0xe0888c27, 0xe08cb42a,
- 0xe898000f, 0xe3570209, 0x9a00018e, 0xea000143,
- 0xe24f8e2e, 0xe0888c27, 0xe898000f, 0xea00063a,
- 0xe24f8e2f, 0xe0888c27, 0xe898000f, 0xea0006dd,
- 0xe24f8c03, 0xe0888c27, 0xe898000f, 0xea000790,
- 0xe24f8e31, 0xe0888c27, 0xe898000f, 0xea000858,
- 0xe3570102, 0x13570209, 0x1357020e, 0x1a0008fe,
- 0xe24f8e33, 0xe0888c27, 0xe898000f, 0xea000880,
- 0xe24f8d0d, 0xe0888c27, 0xe898000f, 0xea000992,
- 0xe24f7e35, 0xe0876c26, 0xe896000f, 0xea000937,
- 0xe24f7fd7, 0xe0878c28, 0xe8980d00, 0xea0005b6,
- 0xe3190080, 0x1afff638, 0xe1b07e09, 0xe209aa07,
- 0x4affff9e, 0xe08c7c27, 0xe08cb42a, 0xe8970780,
- 0xe88b0780, 0xeafff656, 0xe3190080, 0x1afff62e,
- 0xe1b07e09, 0xe209aa07, 0x4affff9a, 0xe08c7c27,
- 0xe08cb42a, 0xe8970780, 0xe2277102, 0xe88b0780,
- 0xeafff64b, 0xe3190080, 0x1afff623, 0xe1b07e09,
- 0xe209aa07, 0x4affff89, 0xe08c7c27, 0xe08cb42a,
- 0xe8970780, 0xe3c77102, 0xe88b0780, 0xeafff640,
- 0xe1b07e09, 0xe209aa07, 0x4affff80, 0xe08c7c27,
- 0xe08ca42a, 0xe897000f, 0xe2098080, 0xe3888040,
- 0xe1580ba3, 0x21b04183, 0x3a00001d, 0xe88a000f,
- 0xeafff62c, 0xe1b07e09, 0xe209aa07, 0x4affff79,
- 0xe08c7c27, 0xe08ca42a, 0xe897000f, 0xe2200102,
- 0xe2098080, 0xe3888040, 0xe1580ba3, 0x21b04183,
- 0x3a00000f, 0xe88a000f, 0xeafff61e, 0xe1b07e09,
- 0xe209aa07, 0x4affff65, 0xe08c7c27, 0xe08ca42a,
- 0xe897000f, 0xe3c00102, 0xe2098080, 0xe3888040,
- 0xe1580ba3, 0x21b04183, 0x3a000001, 0xe88a000f,
- 0xeafff610, 0xe1a04328, 0xe1844d23, 0xe24f7018,
- 0xe3540019, 0x0a00006b, 0xc3c03102, 0xe3140002,
- 0x1a000034, 0xe1b05883, 0x12955802, 0x0a00001c,
- 0xe2195060, 0x1a00000c, 0xe1925c81, 0xe2012080,
- 0x000220a1, 0xe0911002, 0x23a01102, 0xe2a33000,
- 0xe3a02000, 0xe3c110ff, 0xe2535dfe, 0x9a00001a,
- 0xe35500ff, 0x31a0f007, 0xea000012, 0xe3550060,
- 0x11922c01, 0x10305d05, 0x5afffff4, 0xe2911c01,
- 0x23a01102, 0xe2a33000, 0xe3a02000, 0xe3c110ff,
- 0xe2535dfe, 0x9a00000c, 0xe35500ff, 0x31a0f007,
- 0xea000004, 0xe31300ff, 0x11a0f007, 0xe1922001,
- 0x01a0f007, 0xea00000a, 0xe3a030ff, 0xe3833c7f,
- 0xe3a01000, 0xe3a04004, 0xeafffb1a, 0xe3750017,
- 0xda000003, 0xe2655009, 0xe1a01531, 0xe1a01511,
- 0xe1a0f007, 0xe3a03000, 0xe3a02000, 0xe3a01000,
- 0xe3a04008, 0xeafffb0f, 0xe1b05883, 0x12955802,
- 0x0a000022, 0xe2195060, 0x1a00000f, 0xe1b04b02,
- 0xe2024b01, 0x000440a2, 0xe0922004, 0xe2b11000,
- 0xe2a33000, 0x23a01102, 0xe1a025a2, 0xe1a02582,
- 0xe2535b0f, 0x9a00001a, 0xe2854001, 0xe3540b02,
- 0x31a0f007, 0xe3a02000, 0xeaffffda, 0xe3550060,
- 0x11b04a82, 0x10305d05, 0x5afffff2, 0xe2922b02,
- 0xe2b11000, 0x23a01102, 0xe2a33000, 0xe1a025a2,
- 0xe1a02582, 0xe2535b0f, 0x9a000009, 0xe2854001,
- 0xe3540b02, 0x31a0f007, 0xe3a02000, 0xeaffffc9,
- 0xe31300ff, 0x11a0f007, 0xe1922001, 0x01a0f007,
- 0xeaffffcf, 0xe3750034, 0xdaffffcd, 0xe265500c,
- 0xe2554020, 0x21a02431, 0x31a02532, 0x21a01412,
- 0xe1a02512, 0xe1a0f007, 0xe1a03080, 0xe1b03aa3,
- 0x12834001, 0x13340b02, 0x0a000023, 0xe2833b0f,
- 0xe2195060, 0x1a00000f, 0xe1b04201, 0xe1a01aa1,
- 0xe1811580, 0xe3811102, 0xe2014080, 0x000440a1,
- 0xe0911004, 0x23a01102, 0xe2a33000, 0xe3c110ff,
- 0xe3a02000, 0xe2535dfe, 0x9affffab, 0xe35500ff,
- 0x31a0f007, 0xeaffffa3, 0xe1b04181, 0xe1a01aa1,
- 0xe1811580, 0xe3811102, 0x13550060, 0x10305d05,
- 0x5afffff1, 0xe2911c01, 0x23a01102, 0xe2a33000,
- 0xe3a02000, 0xe3c110ff, 0xe2535dfe, 0x9affff9a,
- 0xe35500ff, 0x31a0f007, 0xeaffff92, 0xe1833203,
- 0xe1912600, 0x01a0f007, 0xe1a02581, 0xe1a01aa1,
- 0xe1811580, 0xe31300ff, 0x11a0f007, 0xeaffff94,
- 0xe3190080, 0x1afff54c, 0xe1b07e09, 0xe209aa07,
- 0x4afffeb0, 0xe08c7c27, 0xe08cb42a, 0xe897000f,
- 0xe1b04d23, 0xe28f7000, 0x1afff9c3, 0xe1a04883,
- 0xe2944802, 0x0a00000b, 0xe92c4000, 0xebfff83c,
- 0xe8bc4000, 0xe28f7014, 0x1afffa96, 0xe1898629,
- 0xe3180080, 0x0affff4e, 0xe3190080, 0x1affff81,
- 0xe88b000f, 0xeafff553, 0xe1928001, 0x0a000003,
- 0xe3811101, 0xe24f701c, 0xe3a04001, 0xeafffa89,
- 0xe3a02000, 0xe24f702c, 0xeaffff66, 0xe3190080,
- 0x1afff529, 0xe1b07e09, 0xe209aa07, 0x4afffec0,
- 0xe08c8c27, 0xe08cb42a, 0xe898000f, 0xe1b04d23,
- 0xe28f7000, 0x1afff9a0, 0x1888000f, 0xe1b04883,
- 0x12944802, 0x0a000063, 0xe3100102, 0x1a000059,
- 0xe2833901, 0xe2433001, 0xe1b030a3, 0xe1a05002,
- 0x32414102, 0x22414101, 0x33a07201, 0x23a07202,
- 0xe3a01102, 0xe0955005, 0xe0b44004, 0xe0216007,
- 0x31540006, 0x20444006, 0x20211087, 0xe1b070e7,
- 0x5afffff7, 0xe1942005, 0x11892629, 0x12122080,
- 0x03a07000, 0x0a000018, 0xe3a02000, 0xe0955005,
- 0xe0b44004, 0xe0a00000, 0xe0226007, 0xe055a006,
- 0xe0d48001, 0x31b000a0, 0x21a0500a, 0x21a04008,
- 0x20222087, 0x20211fa7, 0xe1b070a7, 0x1afffff2,
- 0xe0955005, 0xe0b44004, 0xe0b70007, 0xe0d5a002,
- 0xe0d48001, 0x31b000a0, 0x21a0500a, 0x21a04008,
- 0x22222001, 0x23a07102, 0xe3a00000, 0xe3190702,
- 0x1a000008, 0xe1954004, 0x01944007, 0x13822001,
- 0xe28f7044, 0xe3530000, 0xdaffff29, 0xe3190080,
- 0x0afffef7, 0xeaffff2b, 0xe2196060, 0x1a000015,
- 0xe0977007, 0xe0b55005, 0xe0b44004, 0x2a000002,
- 0xe1540001, 0x01550002, 0x03570101, 0xe2b22000,
- 0xe2b11000, 0xe2a33000, 0x23a01102, 0xe59c5080,
- 0xe3150010, 0x0a000001, 0xe88b000f, 0xeafff4ed,
- 0xe3855010, 0xe58c5080, 0xe3150601, 0x0afffff9,
- 0xe3a00010, 0xea0008b4, 0xe1945005, 0x01955007,
- 0x13560060, 0x0afffff0, 0xe1300c86, 0x4affffee,
- 0xe2922001, 0xeaffffe9, 0xe3a014c5, 0xe3a02000,
- 0xe3a030ff, 0xe1833383, 0xe3811101, 0xe24f705c,
- 0xe3a04001, 0xeafffa13, 0xe3530000, 0x1a000008,
- 0xe1914002, 0x0affffe3, 0xe1b01001, 0x4affff95,
- 0xe0922002, 0xe0b11001, 0xe2433001, 0x5afffffb,
- 0xeaffff90, 0xe1914002, 0x1affffee, 0xe3100102,
- 0x0affffd5, 0xeaffffe7, 0xe3190080, 0x1afff4a6,
- 0xe1b08e09, 0x4afffe1a, 0xe08c8c28, 0xe898000f,
- 0xe1b04d23, 0x0a00000b, 0xe28f7024, 0xe3540008,
- 0x1afff91d, 0xe3a02000, 0xe1a03080, 0xe1b03c23,
- 0x133300ff, 0x11a01400, 0x13811102, 0x12833dfe,
- 0x0afffa4d, 0xe888000f, 0xe1a0b003, 0xe1a0a002,
- 0xe1a08001, 0xe2004102, 0xe2096807, 0xe08c6626,
- 0xe896000f, 0xe1340000, 0x4a0000b6, 0xe1b04d23,
- 0x0a00000b, 0xe28f7024, 0xe3540008, 0x1afff906,
- 0xe3a02000, 0xe1a03080, 0xe1b03c23, 0x133300ff,
- 0x11a01400, 0x13811102, 0x12833dfe, 0x0afffa36,
- 0xe886000f, 0xe3a06802, 0xe0965883, 0x3096588b,
- 0x2a000061, 0xe053400b, 0x4a000046, 0xe2745020,
- 0xda00000e, 0xe092243a, 0x20822518, 0x30922518,
- 0xe0b11438, 0xe1a0851a, 0xe1a0a088, 0x2a000011,
- 0xe3190702, 0x1a00001d, 0xe19aa008, 0x13822001,
- 0xe28f7090, 0xe3190080, 0x0afffe7d, 0xeafffeb1,
- 0xe3540040, 0xc18aa008, 0xc3a08000, 0xaa00000b,
- 0xe2444020, 0xe2645020, 0xe0922438, 0xe2b11000,
- 0xe1a08518, 0xe18aa088, 0xe2a33000, 0x218aa008,
- 0x21a08f82, 0x21a020a2, 0x21822f81, 0x21a01061,
- 0xe3190702, 0x1a000005, 0xe19aa008, 0x13822001,
- 0xe28f7030, 0xe3190080, 0x0afffe65, 0xeafffe99,
- 0xe2197060, 0x1a000014, 0xe19aa088, 0x00088f82,
- 0xe0922fa8, 0xe2b11000, 0xe2a33000, 0x23a01102,
- 0xe0965883, 0x0a00003b, 0xe59c5080, 0xe3150010,
- 0x0a000003, 0xe2099a07, 0xe08c9429, 0xe889000f,
- 0xeafff45c, 0xe3855010, 0xe58c5080, 0xe3150601,
- 0x0afffff7, 0xe3a00010, 0xea000823, 0xe19aa008,
- 0x13570060, 0x0affffef, 0xe1300c87, 0x4affffed,
- 0xe2922001, 0xeaffffe6, 0xe2644000, 0xe1a0300b,
- 0xe1a05001, 0xe1a01008, 0xe1a08005, 0xe1a05002,
- 0xe1a0200a, 0xe1a0a005, 0xe2745020, 0xdaffffbf,
- 0xe092243a, 0x20822518, 0x30922518, 0xe0b11438,
- 0xe1a0851a, 0xe1a0a088, 0x2affffc2, 0xe3190702,
- 0x1affffce, 0xe19aa008, 0x13822001, 0xe24f70ac,
- 0xe3190080, 0x0afffe2e, 0xeafffe62, 0xe0965883,
- 0x1a000001, 0xe1925001, 0x1a000006, 0xe096588b,
- 0x1affffcc, 0xe1a0300b, 0xe1a01008, 0xe1a0200a,
- 0xe1915002, 0x0affffc7, 0xe3811101, 0xe24f70ec,
- 0xe3a04001, 0xeafff963, 0xe3a030ff, 0xe1833383,
- 0xe3a02000, 0xe3a01000, 0xe24f7f42, 0xe3a04004,
- 0xeafff95c, 0xe1b04d23, 0x0a00000b, 0xe28f7024,
- 0xe3540008, 0x1afff87c, 0xe3a02000, 0xe1a03080,
- 0xe1b03c23, 0x133300ff, 0x11a01400, 0x13811102,
- 0x12833dfe, 0x0afff9ac, 0xe886000f, 0xe0200589,
- 0xeaffff73, 0xe3190080, 0x1afff3ef, 0xe1b08e09,
- 0x4afffd68, 0xe08c8c28, 0xe898000f, 0xe1b04d23,
- 0x0a00000b, 0xe28f7024, 0xe3540008, 0x1afff866,
- 0xe3a02000, 0xe1a03080, 0xe1b03c23, 0x133300ff,
- 0x11a01400, 0x13811102, 0x12833dfe, 0x0afff996,
- 0xe888000f, 0xe1a0b003, 0xe1a0a002, 0xe1a08001,
- 0xe2004102, 0xe2096807, 0xe08c6626, 0xe896000f,
- 0xe1340000, 0x4affffd2, 0xe1b04d23, 0x0a00000b,
- 0xe28f7024, 0xe3540008, 0x1afff84f, 0xe3a02000,
- 0xe1a03080, 0xe1b03c23, 0x133300ff, 0x11a01400,
- 0x13811102, 0x12833dfe, 0x0afff97f, 0xe886000f,
- 0xe0200589, 0xe3a06802, 0xe0965883, 0x3096588b,
- 0x2a00006b, 0xe053400b, 0x01510008, 0x0152000a,
- 0x0a000078, 0x3a00004c, 0xe3a07000, 0xe2745020,
- 0xda000015, 0xe057651a, 0xe0d2243a, 0x30422518,
- 0x20522518, 0xe0d11438, 0x5a00001b, 0xe3190702,
- 0x1a000029, 0xe1977006, 0x13822001, 0xe28f70c0,
- 0xe3190080, 0x0afffdc2, 0xeafffdf6, 0x13a06102,
- 0xe3a07001, 0xe198500a, 0x0a000029, 0xe2522001,
- 0xe2d11000, 0x5a00000c, 0xea000011, 0xe3a06000,
- 0xe3540040, 0xaafffff4, 0xe2444020, 0xe2645020,
- 0xe057751a, 0xe0d6643a, 0x30466518, 0x20566518,
- 0xe0d22438, 0xe2d11000, 0x4a000005, 0xe0977007,
- 0xe0b66006, 0xe0b22002, 0xe0b11001, 0xe2433001,
- 0x5afffff9, 0xe3190702, 0x1a000007, 0xe3530000,
- 0xda00004c, 0xe1977006, 0x13822001, 0xe28f7030,
- 0xe3190080, 0x0afffd9e, 0xeafffdd2, 0xe2195060,
- 0x1a00000e, 0xe1977086, 0x00066f82, 0xe0922fa6,
- 0xe2b11000, 0xe2a33000, 0x23a01102, 0xe1b03003,
- 0x4a000042, 0xe59c5080, 0xe3150010, 0x0affff3c,
- 0xe2099a07, 0xe08c9429, 0xe889000f, 0xeafff395,
- 0xe1977006, 0x13550060, 0x0afffff3, 0xe1300c85,
- 0x4afffff1, 0xe2922001, 0xeaffffec, 0xe2644000,
- 0xe2200102, 0xe1a0300b, 0xe1a05001, 0xe1a01008,
- 0xe1a08005, 0xe1a05002, 0xe1a0200a, 0xe1a0a005,
- 0xe3a07000, 0xe2745020, 0xdaffffbf, 0xe057651a,
- 0xe0d2243a, 0x30422518, 0x20522518, 0xe0d11438,
- 0x5affffc5, 0xe3190702, 0x1affffd3, 0xe1977006,
- 0x13822001, 0xe24f7098, 0xe3190080, 0x0afffd6c,
- 0xeafffda0, 0xe0965883, 0x1a000005, 0xe1925001,
- 0x1affff44, 0xe153000b, 0x0198500a, 0x03a014c1,
- 0x0affff40, 0xe096588b, 0x1affffcd, 0xe2200102,
- 0xe1a0300b, 0xe1a01008, 0xe1a0200a, 0xe1915002,
- 0x0affffc7, 0xeaffff37, 0xe3a03000, 0xe3a02000,
- 0xe3a01000, 0xeaffffc2, 0xe3a03000, 0xe3a02000,
- 0xe3a01000, 0xe24f7f42, 0xe3a04008, 0xeafff895,
- 0xe2633000, 0xe2734020, 0x42435020, 0x41a02531,
- 0x51a02332, 0x51822411, 0xe1a01331, 0xe3a03000,
- 0xeaffffb3, 0xe3190080, 0x1afff32f, 0xe1b08e09,
- 0x4afffcad, 0xe08c8c28, 0xe898000f, 0xe1b04d23,
- 0x0a00000b, 0xe28f7024, 0xe3540008, 0x1afff7a6,
- 0xe3a02000, 0xe1a03080, 0xe1b03c23, 0x133300ff,
- 0x11a01400, 0x13811102, 0x12833dfe, 0x0afff8d6,
- 0xe888000f, 0xe2000102, 0xe183b000, 0xe1a0a002,
- 0xe1a08001, 0xe2096807, 0xe08c6626, 0xe896000f,
- 0xe1b04d23, 0x0a00000b, 0xe28f7024, 0xe3540008,
- 0x1afff791, 0xe3a02000, 0xe1a03080, 0xe1b03c23,
- 0x133300ff, 0x11a01400, 0x13811102, 0x12833dfe,
- 0x0afff8c1, 0xe886000f, 0xe020000b, 0xe3cbb102,
- 0xe3a06802, 0xe3530000, 0x135b0000, 0x0a00008c,
- 0xe0965883, 0x3096588b, 0x2afffee7, 0xe3b054ff,
- 0xe0a3300b, 0xe185b425, 0xe043392b, 0xe19a4088,
- 0x11924081, 0x0a000064, 0xe92c4209, 0xe1a04821,
- 0xe1c1500b, 0xe1a06822, 0xe1c2700b, 0xe1c8900b,
- 0xe1a08828, 0xe1cab00b, 0xe1a0a82a, 0xe0030b96,
- 0xe0020b94, 0xe0010994, 0xe0000a97, 0xe0933000,
- 0xe0000a95, 0xe0b22000, 0xe0000895, 0xe0b11000,
- 0x33a0e000, 0x23a0e001, 0xe0000996, 0xe0922000,
- 0xe2b11000, 0xe2aee000, 0xe0000897, 0xe0922000,
- 0xe2b11000, 0xe2aee000, 0xe18ee803, 0xe1a03823,
- 0xe1833802, 0xe1a02822, 0xe1822801, 0xe1a01821,
- 0xe181180e, 0xe3cee0ff, 0xe0000b95, 0xe00b0b97,
- 0xe09eb00b, 0xe0b33000, 0xe0000896, 0xe0b22000,
- 0xe0000894, 0xe0a11000, 0xe0000a94, 0xe00a0a96,
- 0xe09aa003, 0xe0b22000, 0xe2a11000, 0xe0000997,
- 0xe09aa000, 0xe0000995, 0xe0b22000, 0xe2b11000,
- 0xe8bc4209, 0x5a000009, 0xe3190702, 0x1a000017,
- 0xe19bb00a, 0x13822001, 0xe3530000, 0xdaffff79,
- 0xe28f7078, 0xe3190080, 0x0afffccd, 0xeafffd01,
- 0xe09bb00b, 0xe0baa00a, 0xe0b22002, 0xe0b11001,
- 0xe2433001, 0x5afffff9, 0xe3190702, 0x1a000007,
- 0xe3530000, 0xdaffff6b, 0xe19bb00a, 0x13822001,
- 0xe28f7038, 0xe3190080, 0x0afffcbd, 0xeafffcf1,
- 0xe2195060, 0x1a00001c, 0xe19bb08a, 0x000aaf82,
- 0xe0922faa, 0xe2b11000, 0xe2a33000, 0x23a01102,
- 0xe2934001, 0xda00001b, 0xe1b047a4, 0x1afffe91,
- 0xe59c5080, 0xe3150010, 0x0afffe59, 0xe2099a07,
- 0xe08c9429, 0xe889000f, 0xeafff2b2, 0xe19a4088,
- 0x11a0200a, 0x11a01008, 0xe2433001, 0xe3190702,
- 0x1affffee, 0xe3530000, 0xdaffff4a, 0xe24f7044,
- 0xe3190080, 0x0afffc9e, 0xeafffcd2, 0xe19bb00a,
- 0x13550060, 0x0affffe5, 0xe1300c85, 0x4affffe3,
- 0xe2922001, 0xeaffffde, 0xe2633000, 0xe3530040,
- 0xaaffff3c, 0xe2734020, 0x42435020, 0x41a02531,
- 0x51a02332, 0x51822411, 0xe1a01331, 0xe3a03000,
- 0xeaffffda, 0xe3530000, 0x1a000003, 0xe1915002,
- 0x0a00000c, 0xe35b0000, 0x1affff6c, 0xe198500a,
- 0x1affff6a, 0xe0965883, 0x33a03000, 0x33a02000,
- 0x33a01000, 0x3affffcd, 0xe1915002, 0x1afffe59,
- 0xe3a014c2, 0xeafffe57, 0xe096588b, 0x3affffc7,
- 0xe198500a, 0x1afffe48, 0xe1a0300b, 0xeafffff7,
- 0xe3190080, 0x1afff25c, 0xe2096807, 0xe08c6626,
- 0xe896000f, 0xe1b04d23, 0x0a00000b, 0xe28f7024,
- 0xe3540008, 0x1afff6d4, 0xe3a02000, 0xe1a03080,
- 0xe1b03c23, 0x133300ff, 0x11a01400, 0x13811102,
- 0x12833dfe, 0x0afff804, 0xe886000f, 0xe2000102,
- 0xe183b000, 0xe1a0a002, 0xe1a08001, 0xe1b06e09,
- 0x4afffbd1, 0xe08c6c26, 0xe896000f, 0xe1b04d23,
- 0x0a000035, 0xe28f7024, 0xe3540008, 0x1afff6be,
- 0xe3a02000, 0xe1a03080, 0xe1b03c23, 0x133300ff,
- 0x11a01400, 0x13811102, 0x12833dfe, 0x0afff7ee,
- 0xe886000f, 0xea000028, 0xe3190080, 0x1afff232,
- 0xe1b08e09, 0x4afffbb6, 0xe08c8c28, 0xe898000f,
- 0xe1b04d23, 0x0a00000b, 0xe28f7024, 0xe3540008,
- 0x1afff6a9, 0xe3a02000, 0xe1a03080, 0xe1b03c23,
- 0x133300ff, 0x11a01400, 0x13811102, 0x12833dfe,
- 0x0afff7d9, 0xe888000f, 0xe2000102, 0xe183b000,
- 0xe1a0a002, 0xe1a08001, 0xe2096807, 0xe08c6626,
- 0xe896000f, 0xe1b04d23, 0x0a00000b, 0xe28f7024,
- 0xe3540008, 0x1afff694, 0xe3a02000, 0xe1a03080,
- 0xe1b03c23, 0x133300ff, 0x11a01400, 0x13811102,
- 0x12833dfe, 0x0afff7c4, 0xe886000f, 0xe020000b,
- 0xe3cbb102, 0xe1b04883, 0x11b0588b, 0x12944802,
- 0x12955802, 0x0a000082, 0xe043300b, 0xe2833901,
- 0xe2433001, 0xe3a0b000, 0xe052500a, 0xe0d14008,
- 0x23a01003, 0x2a00000c, 0xe1a05002, 0xe1a04001,
- 0xe3a01001, 0xe2433001, 0xe0955005, 0xe0b44004,
- 0xe2abb000, 0xe055700a, 0xe0d46008, 0x31b0b0ab,
- 0x21a05007, 0x21a04006, 0xe0a11001, 0xe0955005,
- 0xe0b44004, 0xe2abb000, 0xe055700a, 0xe0d46008,
- 0x31b0b0ab, 0x21a05007, 0x21a04006, 0xe0a11001,
- 0xe0955005, 0xe0b44004, 0xe2abb000, 0xe055700a,
- 0xe0d46008, 0x31b0b0ab, 0x21a05007, 0x21a04006,
- 0xe0a11001, 0xe0955005, 0xe0b44004, 0xe2abb000,
- 0xe055700a, 0xe0d46008, 0x31b0b0ab, 0x21a05007,
- 0x21a04006, 0xe0b11001, 0x3affffda, 0xe1942005,
- 0x11892629, 0x12122080, 0x0a000025, 0xe3a02001,
- 0xe0955005, 0xe0b44004, 0xe2abb000, 0xe055700a,
- 0xe0d46008, 0x31b0b0ab, 0x21a05007, 0x21a04006,
- 0xe0a22002, 0xe0955005, 0xe0b44004, 0xe2abb000,
- 0xe055700a, 0xe0d46008, 0x31b0b0ab, 0x21a05007,
- 0x21a04006, 0xe0a22002, 0xe0955005, 0xe0b44004,
- 0xe2abb000, 0xe055700a, 0xe0d46008, 0x31b0b0ab,
- 0x21a05007, 0x21a04006, 0xe0a22002, 0xe0955005,
- 0xe0b44004, 0xe2abb000, 0xe055700a, 0xe0d46008,
- 0x31b0b0ab, 0x21a05007, 0x21a04006, 0xe0b22002,
- 0x3affffda, 0xe3190702, 0x1a000007, 0xe1954004,
- 0x13822001, 0xe3530000, 0xdafffe62, 0xe28f7048,
- 0xe3190080, 0x0afffbb6, 0xeafffbea, 0xe2197060,
- 0x1a000014, 0xe0955005, 0xe0b44004, 0x2a000002,
- 0xe1540008, 0x0155000a, 0x011500a2, 0xe2b22000,
- 0xe2b11000, 0xe2a33000, 0x23a01102, 0xe2934001,
- 0xdaffff10, 0xe1b047a4, 0x1afffd86, 0xe59c5080,
- 0xe3150010, 0x0afffd4e, 0xe2099a07, 0xe08c9429,
- 0xe889000f, 0xeafff1a7, 0xe1945005, 0x13570060,
- 0x0afffff1, 0xe1300c87, 0x4affffef, 0xe2922001,
- 0xeaffffea, 0xe1b04883, 0x1a000013, 0xe1915002,
- 0x1a00000d, 0xe1b0588b, 0x0198600a, 0x03a014c3,
- 0x03a030ff, 0x01833383, 0x0afffd6a, 0xe2955802,
- 0x1affffe8, 0xe198600a, 0x0affffe6, 0xe1a01008,
- 0xe1a0200a, 0xe1a0300b, 0xeafffd62, 0xe0922002,
- 0xe0b11001, 0xe2433001, 0x5afffffb, 0xe1b0588b,
- 0x1a000010, 0xe198600a, 0x1a00000a, 0xe2944802,
- 0x1a000001, 0xe1916002, 0x1afffd56, 0xe3a01000,
- 0xe3a02000, 0xe3a030ff, 0xe1833383, 0xe24f70bc,
- 0xe3a04002, 0xeafff6b7, 0xe09aa00a, 0xe0b88008,
- 0xe24bb001, 0x5afffffb, 0xe2956802, 0x12946802,
- 0x1affff50, 0xe2946802, 0x1a000006, 0xe1916002,
- 0x1afffd44, 0xe2956802, 0x1affffbf, 0xe198600a,
- 0x03a01331, 0x0afffd3f, 0xe198600a, 0x0afffe09,
- 0xe1a01008, 0xe1a0200a, 0xe1a0300b, 0xeafffd39,
- 0xe3190080, 0x1afff144, 0xe2096807, 0xe08c6626,
- 0xe896000f, 0xe1b04d23, 0xe28f7000, 0x1afff5be,
- 0x1886000f, 0xe2000102, 0xe183b000, 0xe1a0a002,
- 0xe1a08001, 0xe1b06e09, 0x4afffacd, 0xe08c6c26,
- 0xe896000f, 0xe1b04d23, 0xe28f7000, 0x1afff5b2,
- 0x1886000f, 0xea000014, 0xe3190080, 0x1afff12e,
- 0xe1b08e09, 0x4afffabc, 0xe08c8c28, 0xe898000f,
- 0xe1b04d23, 0xe28f7000, 0x1afff5a7, 0x1888000f,
- 0xe2000102, 0xe183b000, 0xe1a0a002, 0xe1a08001,
- 0xe2096807, 0xe08c6626, 0xe896000f, 0xe1b04d23,
- 0xe28f7000, 0x1afff59c, 0x1886000f, 0xe1a0700b,
- 0xe3cbb102, 0xe1b04883, 0x12944802, 0x11b0588b,
- 0x12955802, 0x0a00004e, 0xe92c4200, 0x5a000035,
- 0xe24b4c3f, 0xe24440fe, 0xe3540010, 0xca00002a,
- 0xe19a5418, 0x1a00002f, 0xe2649020, 0xe1a09938,
- 0xe0000f89, 0xe92c0080, 0xe3a08102, 0xe3a0a000,
- 0xe3a07901, 0xe257b001, 0xe92c0d80, 0x3bfff2b6,
- 0xe1b090a9, 0x3afffffc, 0xe8bc0d80, 0x192c000f,
- 0xebfff2b5, 0xe2834001, 0x0a000009, 0xe3540902,
- 0xaa000010, 0xe8bc0d80, 0xe92c000f, 0xe1a00007,
- 0xe1a01008, 0xe1a0200a, 0xe1a0300b, 0xebfff2aa,
- 0xeaffffee, 0xe8bc0080, 0xe3170102, 0x1bfff2f3,
- 0xe8bc4200, 0xe2934001, 0xdafffe6a, 0xe1b047a4,
- 0x1afffce0, 0xea0000cb, 0xe28cc010, 0xe8bc4280,
- 0xe3170102, 0x1afffda3, 0xeafffcda, 0xe3540040,
- 0x2a000012, 0xe2545020, 0x21b0651a, 0x0a000010,
- 0xe19a6418, 0x0a00000e, 0xe3100102, 0x1a00000e,
- 0xe92c0001, 0xe3a00000, 0xe92c0d80, 0xe3c99601,
- 0xeb0000e1, 0xe8bc0d80, 0xebfff28b, 0xeb000166,
- 0xe8bc4201, 0x0a0000b3, 0xe28f7e2f, 0xeafff629,
- 0x13b05100, 0x33a00000, 0xeafffff0, 0xe8bc4200,
- 0xe3a014c7, 0xe3a02000, 0xe3a030ff, 0xe1833383,
- 0xeafffcb8, 0xe3540000, 0x1a00001e, 0xe3530000,
- 0x0a000002, 0xe1916002, 0x1afffcb2, 0xea000001,
- 0xe1916002, 0x1a000010, 0xe1b0588b, 0x1a000006,
- 0xe198600a, 0x03a01102, 0x03a02000, 0x03a00000,
- 0x03a03901, 0x02433001, 0xea000096, 0xe2955802,
- 0x1a000094, 0xe198600a, 0x0a000092, 0xe1a01008,
- 0xe1a0200a, 0xe1a0300b, 0xeafffc9e, 0xe0922002,
- 0xe0b11001, 0xe2433001, 0x5afffffb, 0xe1b0588b,
- 0x12955802, 0x1affff8f, 0xe35b0000, 0x0a000008,
- 0xe1a01008, 0xe1a0200a, 0xe1a00007, 0xe1a0300b,
- 0xe198600a, 0x1afffc8f, 0xe3100102, 0x13a03000,
- 0xea00007c, 0xe198600a, 0x0affffdd, 0xe09aa00a,
- 0xe0b88008, 0xe24bb001, 0x5afffffb, 0xe92c4200,
- 0xeaffffb4, 0xe3190080, 0x1afff08f, 0xe1b08e09,
- 0x4afffa4e, 0xe08c8c28, 0xe898000f, 0xe1b04d23,
- 0xe28f7000, 0x1afff508, 0x1888000f, 0xe2000102,
- 0xe183b000, 0xe1a0a002, 0xe1a08001, 0xe2096807,
- 0xe08c6626, 0xe896000f, 0xe1b04d23, 0xe28f7000,
- 0x1afff4fd, 0x1886000f, 0xe1a0700b, 0xe3cbb102,
- 0xe1b04883, 0x12944802, 0x11b0588b, 0x12955802,
- 0x0a00000a, 0xe92c400f, 0xe92c0d80, 0xebfff27f,
- 0xebfff36f, 0xe8bc0d80, 0xebfff227, 0xe2200102,
- 0xe8bc0d80, 0xebfff178, 0xe8bc4000, 0xea00004d,
- 0xe1b04883, 0x1a000010, 0xe1915002, 0x1a00000a,
- 0xe1b0588b, 0x0198600a, 0x0a000013, 0xe2955802,
- 0x1a000015, 0xe198600a, 0x0a000013, 0xe1a01008,
- 0xe1a0200a, 0xe1a0300b, 0xeafffc4e, 0xe0922002,
- 0xe0b11001, 0xe2433001, 0x5afffffb, 0xe1b0588b,
- 0x1a000012, 0xe198600a, 0x1a00000c, 0xe2944802,
- 0x1a000001, 0xe1916002, 0x1afffc42, 0xe3a01333,
- 0xe3b02100, 0xe2e23902, 0xeafffc3e, 0xe3a00000,
- 0xe3a01000, 0xe3a02000, 0xe3a03000, 0xea000029,
- 0xe09aa00a, 0xe0b88008, 0xe24bb001, 0x5afffffb,
- 0xe2956802, 0x12946802, 0x1affffc9, 0xe2946802,
- 0x1a000008, 0xe1916002, 0x1afffc2e, 0x03a01333,
- 0xe2956802, 0x1afffc2b, 0xe198600a, 0x11a01008,
- 0x11a0200a, 0xeafffc27, 0xe198600a, 0x0a000015,
- 0xe1a01008, 0xe1a0200a, 0xe1a0300b, 0xeafffc21,
- 0xe3190080, 0x1afff02c, 0xe1b07e09, 0x4afff9cb,
- 0xe08c8c27, 0xe898000f, 0xe1b04d23, 0xe28f7000,
- 0x1afff4a5, 0x1888000f, 0xe1b04883, 0x12944802,
- 0x0a00001d, 0xe3100102, 0x1a000016, 0xe92c4000,
- 0xeb000029, 0xe8bc4000, 0xe3190702, 0x1a000005,
- 0xe28f7018, 0xe3530000, 0xdafffa5d, 0xe3190080,
- 0x0afffa2b, 0xeafffa5f, 0xe3530000, 0xba000006,
- 0xe59c5080, 0xe3150010, 0x0afffbd1, 0xe2099a07,
- 0xe08c9429, 0xe889000f, 0xeafff02a, 0xe3730040,
- 0xcafffcce, 0xeafffa4e, 0xe3a014c6, 0xe3a02000,
- 0xe3a030ff, 0xe1833383, 0xeafffbf6, 0xe3530000,
- 0x1a000008, 0xe1914002, 0x0afffff6, 0xe1b01001,
- 0x4affffdb, 0xe0922002, 0xe0b11001, 0xe2433001,
- 0x5afffffb, 0xeaffffd6, 0xe1914002, 0x1afffbe9,
- 0xe3100102, 0x0affffe1, 0xeaffffea, 0xe28f4f52,
- 0xe8940500, 0xe1510008, 0x0152000a, 0xe1a0a0a2,
- 0xe18aaf81, 0xe1a080a1, 0xe3888102, 0xe3a0b0fe,
- 0xe18bb30b, 0xe043400b, 0x92444001, 0xe92c4210,
- 0xe1a0300b, 0x8a000005, 0xe3c88101, 0xe0922002,
- 0xe0b11001, 0xe2433001, 0x5a000003, 0xea000008,
- 0xe3a00102, 0xe2722000, 0xe2f11000, 0x03520000,
- 0x0a000035, 0xe0922002, 0xe0b11001, 0xe2433001,
- 0x5afffff9, 0xe3a07000, 0xebfff1e0, 0xe92c000f,
- 0xebfff185, 0xe92c000f, 0xe28f90c4, 0xe8b90d00,
- 0xebfff125, 0xe89c0d80, 0xebfff183, 0xe8b90d00,
- 0xebfff0d8, 0xe89c0d80, 0xebfff17f, 0xe8b90d00,
- 0xebfff11d, 0xe89c0d80, 0xe92c000f, 0xe3a00102,
- 0xe8b9000e, 0xebfff178, 0xe8b90d00, 0xebfff0cd,
- 0xe28c4010, 0xe8940d80, 0xebfff173, 0xe8b90d00,
- 0xebfff111, 0xe8bc0d80, 0xebfff1c4, 0xe8bc0d80,
- 0xebfff16d, 0xe89c0d80, 0xebfff16b, 0xe8bc0d80,
- 0xebfff0bd, 0xe8bc0010, 0xebfff25e, 0xe92c000f,
- 0xe3a00000, 0xe8b9000e, 0xebfff163, 0xe8bc0d80,
- 0xebfff0b5, 0xe8bc0200, 0xe3190601, 0xe28f7074,
- 0x18970d00, 0x1bfff15c, 0xe8bc8000, 0xe3a00000,
- 0xe3a03000, 0xe28f9050, 0xeaffffed, 0xb504f333,
- 0xf9de6484, 0x8eac025b, 0x3e7076bb, 0x00004004,
- 0x9c041fd0, 0xa933ef60, 0x00004007, 0xc05ff4e0,
- 0x6c83bb96, 0x00004008, 0xca20ad9a, 0xb5e946e9,
- 0x00003ffe, 0x83125100, 0xb57f6509, 0x00004003,
- 0x803ff895, 0x9dacd228, 0x00004005, 0xb17217f7,
- 0xd1cf79ac, 0x00003ffe, 0xde5bd8a9, 0x37287195,
- 0x00003ffd, 0xe3190080, 0x1affef83, 0xe1b07e09,
- 0x4afff926, 0xe08c8c27, 0xe898000f, 0xe1b04d23,
- 0xe28f7000, 0x1afff3fc, 0x1888000f, 0xe1a04883,
- 0xe2944802, 0x0a000005, 0xe92c4000, 0xeb00000a,
- 0xe8bc4000, 0x0affff57, 0xe24f7d0a, 0xeafff4cd,
- 0xe1914002, 0x1afffb63, 0xe3100102, 0x0affff5b,
- 0xe3a00000, 0xe3a03000, 0xeaffff58, 0xe28f4f6e,
- 0xe3100102, 0x128f4f72, 0xe8b40d00, 0xe153000b,
- 0x01510008, 0x0152000a, 0x8a00005d, 0xe8940d00,
- 0xe153000b, 0x01510008, 0x0152000a, 0x3a000052,
- 0xe92c421f, 0xe28f9e1b, 0xe3a07000, 0xe8b90d00,
- 0xebfff111, 0xebfff238, 0xe3170102, 0x12644000,
- 0xe58c4010, 0xe92c0d80, 0xe3a00000, 0xe8b9000e,
- 0xebfff109, 0xe8bc0d80, 0xe92c000f, 0xe8b9000e,
- 0xe3a00102, 0xebfff104, 0xe92c000f, 0xe28c4020,
- 0xe894000f, 0xebfff20c, 0xe3170102, 0x0bfff09e,
- 0x1bfff054, 0xe1a0400c, 0xe92c000f, 0xe894000f,
- 0xebfff04d, 0xe8bc0d80, 0xebfff04b, 0xe28cc010,
- 0xe8bc0d80, 0xebfff048, 0xe88c000f, 0xebfff0ee,
- 0xe92c000f, 0xe3a07000, 0xe8b90d00, 0xebfff0ee,
- 0xe8b90d00, 0xebfff043, 0xe89c0d80, 0xebfff0ea,
- 0xe8b90d00, 0xebfff03f, 0xe89c0d80, 0xebfff0e6,
- 0xe8b90d00, 0xebfff03b, 0xe89c0d80, 0xe92c000f,
- 0xe3a00000, 0xe8b9000e, 0xebfff0df, 0xe8b90d00,
- 0xebfff034, 0xe28c7010, 0xe8970d80, 0xebfff0da,
- 0xe8b90d00, 0xebfff02f, 0xe28c7020, 0xe8970d80,
- 0xebfff0d5, 0xe8bc0d80, 0xe92c000f, 0xe2200102,
- 0xebfff025, 0xe1a07000, 0xe1a08001, 0xe1a0a002,
- 0xe1a0b003, 0xe8bc000f, 0xebfff120, 0xe8b90d00,
- 0xebfff020, 0xe28cc020, 0xe8bc4210, 0xe2844001,
- 0xe0833004, 0xe3b04000, 0xe1a0f00e, 0xe3b00000,
- 0xe3a01102, 0xe3a02000, 0xe3a03901, 0xe2433001,
- 0xe1a0f00e, 0xe3100102, 0xe3a00000, 0xe3a01000,
- 0xe3a02000, 0x13a03000, 0x13a04008, 0x03a030ff,
- 0x01833383, 0x03b04004, 0xe1a0f00e, 0xb17217f7,
- 0xd1cf79ab, 0x0000400c, 0x80000000, 0x00000000,
- 0x00003fbe, 0xb21dfe7f, 0x09e2baa9, 0x0000400c,
- 0x80000000, 0x00000000, 0x00003fbe, 0xb8aa3b29,
- 0x5c17f0bc, 0x00003fff, 0xde8082e3, 0x08654362,
- 0x00003ff2, 0xb1800000, 0x00000000, 0x00003ffe,
- 0xc99b1867, 0x2822a93e, 0x00003fea, 0xa57862e1,
- 0x46a6fb39, 0x00003ff4, 0xe8b9428e, 0xfecff592,
- 0x00003ffa, 0x80000000, 0x00000000, 0x00003ffe,
- 0x845a2157, 0x3490f106, 0x00003ff0, 0xf83a5f91,
- 0x50952c99, 0x00003ff7, 0x80000000, 0x00000000,
- 0x00003ffd, 0x80000000, 0x00000000, 0x00003ffe,
- 0xe3190080, 0x1affeecc, 0xe1b07e09, 0x4afff873,
- 0xe08c8c27, 0xe898000f, 0xe1b04d23, 0xe28f7000,
- 0x1afff345, 0x1888000f, 0xe1a04883, 0xe2944802,
- 0x0a000006, 0xe92c4000, 0xeb000007, 0xe8bc4000,
- 0x0afffea0, 0xe24f705c, 0xe2477c05, 0xeafff415,
- 0xe1914002, 0x03a01332, 0xeafffaaa, 0xe28f4f8f,
- 0xe8b40d00, 0xe153000b, 0x01510008, 0x0152000a,
- 0x8a00006c, 0xe1b01001, 0x5a000063, 0xe92c421f,
- 0xe3190601, 0xe28f9e22, 0xe3a07000, 0xe8b90d00,
- 0xebfff061, 0xebfff188, 0x1b00006d, 0xe58c4010,
- 0xe92c0d80, 0xe3a00000, 0xe8b9000e, 0xebfff05a,
- 0xe8bc0d80, 0xe92c000f, 0xe8b9000e, 0xe3a00102,
- 0xebfff055, 0xe92c000f, 0xe28c4020, 0xe894000f,
- 0xebfff15d, 0xe3170102, 0x0bffefef, 0x1bffefa5,
- 0xe1a0400c, 0xe92c000f, 0xe894000f, 0xebffef9e,
- 0xe8bc0d80, 0xebffef9c, 0xe28cc010, 0xe8bc0d80,
- 0xebffef99, 0xe3a04c3f, 0xe38440df, 0xe1530004,
- 0xba000037, 0xe88c000f, 0xebfff03b, 0xe92c000f,
- 0xe3a07000, 0xe8b90d00, 0xebfff03b, 0xe8b90d00,
- 0xebffefd9, 0xe89c0d80, 0xebfff037, 0xe8b90d00,
- 0xebffef8c, 0xe89c0d80, 0xebfff033, 0xe8b90d00,
- 0xebffefd1, 0xe89c0d80, 0xebfff02f, 0xe8b90d00,
- 0xebffef84, 0xe89c0d80, 0xe92c000f, 0xe3a00102,
- 0xe8b9000e, 0xebfff028, 0xe8b90d00, 0xebffef7d,
- 0xe28c7010, 0xe8970d80, 0xebfff023, 0xe8b90d00,
- 0xebffefc1, 0xe28c7010, 0xe8970d80, 0xebfff01e,
- 0xe28c7020, 0xe8970d80, 0xebfff01b, 0xe28c7020,
- 0xe8970d80, 0xebffef6c, 0xe8bc0d80, 0xe28cc020,
- 0xe8bc0010, 0xe3140001, 0x12200102, 0x1bfff1a7,
- 0xe29b4902, 0x4a000018, 0xe35b0000, 0x0198400a,
- 0x0a000015, 0xebfff061, 0xe8bc4200, 0xe3b04000,
- 0xe1a0f00e, 0xe24cc010, 0xe3a07000, 0xe3a08102,
- 0xe3b0a100, 0xe2eab901, 0xeaffffeb, 0xe1914002,
- 0x0affff99, 0xe2433001, 0xe0922002, 0xe0b11001,
- 0x5afffffb, 0xeaffff94, 0xe3a01332, 0xe3b02100,
- 0xe2f23902, 0xe3a04001, 0xe1a0f00e, 0xe3a01000,
- 0xe3b02100, 0xe2f33902, 0xe3a04004, 0xe8bc4200,
- 0xe1a0f00e, 0xe2844001, 0xe35b0000, 0x03a08102,
- 0xe3a06901, 0x0246b002, 0x01a0f00e, 0xe2466002,
- 0xe04b6006, 0xe3a05102, 0xe153000b, 0x01510008,
- 0x0152000a, 0x20888635, 0x21a0f00e, 0xe0588635,
- 0x51a08088, 0x524bb001, 0xe2444001, 0xe1a0f00e,
- 0xc90fdaa2, 0x00000000, 0x0000401d, 0xa2f9836e,
- 0x4e44152a, 0x00003ffe, 0x95777a5c, 0xf72cece6,
- 0x00003fed, 0xc9100000, 0x00000000, 0x00003fff,
- 0x85bba783, 0xb3c748a9, 0x00003fea, 0xa37b24c8,
- 0x4a42092e, 0x00003ff3, 0xd23cf50b, 0xf10aca84,
- 0x00003ff9, 0xeef5823f, 0xdecea969, 0x00003ffd,
- 0x80000000, 0x00000000, 0x00003fff, 0x95d5b975,
- 0x16391da8, 0x00003fef, 0xe0741531, 0xdd56f650,
- 0x00003ff6, 0x8895af2a, 0x6847fcd5, 0x00003ffc,
- 0xe3190080, 0x1affee00, 0xe1b07e09, 0x4afff7ab,
- 0xe08c8c27, 0xe898000f, 0xe1b04d23, 0xe28f7000,
- 0x1afff279, 0x1888000f, 0xe1a04883, 0xe2944802,
- 0x0a000015, 0xe1c00589, 0xe92c4000, 0xe1914002,
- 0x12433001, 0xebffff38, 0x1a000012, 0xe92c000f,
- 0xebffefa1, 0xe3a08102, 0xe3b0a100, 0xe2eab901,
- 0xebffeef8, 0xe1a07000, 0xe1a08001, 0xe1a0a002,
- 0xe1a0b003, 0xe8bc000f, 0xebffeff0, 0xe1914002,
- 0x12833001, 0xe8bc4000, 0xeafffdc2, 0xe1914002,
- 0x03a014c9, 0xeafff9cf, 0xe8bc4000, 0xe3540004,
- 0x03a03000, 0x03a00000, 0x0afffdba, 0xe3a014c9,
- 0xe3b02100, 0xe2e23902, 0xeafff9c6, 0xe3190080,
- 0x1affedd1, 0xe1b07e09, 0x4afff780, 0xe08c8c27,
- 0xe898000f, 0xe1b04d23, 0xe28f7000, 0x1afff24a,
- 0x1888000f, 0xe1b04883, 0x0a00006b, 0x52944802,
- 0x4a000072, 0xe92c4201, 0xe3a00000, 0xe3a05901,
- 0xe2455002, 0xe1530005, 0xaa000009, 0xe2094501,
- 0xe92c0010, 0xe3a04901, 0xe2444021, 0xe1530004,
- 0xba000049, 0xe92c000f, 0xebffef6b, 0xe92c000f,
- 0xea000012, 0xe2094501, 0xe2244501, 0xe92c0010,
- 0xe3a00102, 0xe3a08102, 0xe3b0a100, 0xe2eab901,
- 0xebffeebc, 0xe1914002, 0x0a00003b, 0xe2433001,
- 0xe24cc010, 0xe92c000f, 0xebfff01c, 0xe2200102,
- 0xe2833001, 0xe28c4010, 0xe884000f, 0xe89c000f,
- 0xe28f9f59, 0xe8b90d00, 0xebffeef7, 0xe89c0d80,
- 0xebffef55, 0xe8b90d00, 0xebffeeaa, 0xe89c0d80,
- 0xebffef51, 0xe8b90d00, 0xebffeeef, 0xe89c0d80,
- 0xebffef4d, 0xe8b90d00, 0xebffeea2, 0xe89c0d80,
- 0xebffef49, 0xe8b90d00, 0xebffeee7, 0xe89c0d80,
- 0xe92c000f, 0xe3a00102, 0xe8b9000e, 0xebffef42,
- 0xe8b90d00, 0xebffee97, 0xe28c7010, 0xe8970d80,
- 0xebffef3d, 0xe8b90d00, 0xebffeedb, 0xe28c7010,
- 0xe8970d80, 0xebffef38, 0xe8b90d00, 0xebffee8d,
- 0xe28c7010, 0xe8970d80, 0xebffef33, 0xe8b90d00,
- 0xebffeed1, 0xe28c7010, 0xe8970d80, 0xebffef2e,
- 0xe8bc0d80, 0xe28cc010, 0xebffef80, 0xe89c0d80,
- 0xebffef29, 0xe8bc0d80, 0xebffee7b, 0xe8bc0230,
- 0xe3190501, 0x0a000008, 0xe3150102, 0x028f5c01,
- 0x128f5f46, 0xe0855924, 0x02200102, 0xe8950d00,
- 0xebffee74, 0xe8bc4000, 0xeafffd46, 0xe3150102,
- 0xe28f50dc, 0xe0855924, 0xe8950d00, 0xebffee6d,
- 0x12200102, 0xe8bc4000, 0xeafffd3e, 0xe1915002,
- 0x0affff93, 0xe1b01001, 0x4affff91, 0xe2433001,
- 0xe0922002, 0xe0b11001, 0x5afffffb, 0xeaffff8c,
- 0xe2f35901, 0x01925081, 0x0affff89, 0xe2944802,
- 0x1a000001, 0xe1914002, 0x1afff93e, 0xe3a014ca,
- 0xe3b02100, 0xe2e23902, 0xeafff93a, 0xbe974377,
- 0xcc30f9e6, 0x00004003, 0x96f3e4b2, 0xc8e37cbc,
- 0x00004006, 0xbeee77e2, 0xb5423cf3, 0x00004007,
- 0xd0927880, 0xf5c2170b, 0x00004007, 0xa43601f1,
- 0x5c3e6196, 0x00004006, 0xb25dedaf, 0x30f3242c,
- 0x00003ffe, 0xa270bb27, 0x61c93957, 0x00004002,
- 0x9ec1654d, 0x36d4f820, 0x00004004, 0xe4d539b0,
- 0x56a451ad, 0x00004004, 0xdaf2ad41, 0xd05311c4,
- 0x00004003, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0xc90fdaa2, 0x2168c235, 0x00003fff,
- 0xc90fdaa2, 0x2168c235, 0x00004000, 0x00000000,
- 0xc90fdaa2, 0x2168c235, 0x00003fff, 0xe3190080,
- 0x1affed19, 0xe2096807, 0xe08c6626, 0xe896000f,
- 0xe1b04d23, 0xe28f7000, 0x1afff193, 0x1886000f,
- 0xe2000102, 0xe183b000, 0xe1a0a002, 0xe1a08001,
- 0xe1b06e09, 0x4afff6c9, 0xe08c6c26, 0xe896000f,
- 0xe1b04d23, 0xe28f7000, 0x1afff187, 0x1886000f,
- 0xe1a0700b, 0xe3cbb102, 0xe1b04883, 0x12944802,
- 0x11b0588b, 0x12955802, 0x192c4281, 0x1bffef0b,
- 0x1a00004e, 0xe1b04883, 0x1a000010, 0xe1915002,
- 0x1a00000a, 0xe1b0588b, 0x0198600a, 0x0a00001f,
- 0xe2955802, 0x1a000016, 0xe198600a, 0x0a000014,
- 0xe1a01008, 0xe1a0200a, 0xe1a0300b, 0xeafff8e1,
- 0xe0922002, 0xe0b11001, 0xe2433001, 0x5afffffb,
- 0xe1b0588b, 0x1a000019, 0xe198600a, 0x1a000013,
- 0xe2944802, 0x1a000001, 0xe1916002, 0x1afff8d5,
- 0xe1a04000, 0xe1a05007, 0xe28f0fbd, 0xe890000e,
- 0xea00008c, 0xe1a04000, 0xe1a05007, 0xe3a00000,
- 0xe3a01000, 0xe3a02000, 0xe3a03000, 0xea00007d,
- 0xe3a014cb, 0xe3b02100, 0xe2e23902, 0xeafff8c5,
- 0xe09aa00a, 0xe0b88008, 0xe24bb001, 0x5afffffb,
- 0xe2956802, 0x12946802, 0x1affffca, 0xe2946802,
- 0x1a000006, 0xe1916002, 0x1afff8ba, 0xe2956802,
- 0x1affffe2, 0xe198600a, 0x03a014cb, 0x0afff8b5,
- 0xe198600a, 0x0affffe2, 0xe1a01008, 0xe1a0200a,
- 0xe1a0300b, 0xeafff8af, 0xe3190080, 0x1affecba,
- 0xe1b07e09, 0x4afff671, 0xe08c8c27, 0xe898000f,
- 0xe1b04d23, 0xe28f7000, 0x1afff133, 0x1888000f,
- 0xe1b04883, 0x12944802, 0x0a000060, 0xe92c4281,
- 0xe3b00100, 0xe2f34901, 0xdbffeeb0, 0xd3a04002,
- 0xc3a04000, 0xe28f9d06, 0xe8b90d00, 0xe153000b,
- 0x01510008, 0x0152000a, 0xc2844001, 0xe92c0010,
- 0xda00000d, 0xe92c000f, 0xe8990d00, 0xebffedad,
- 0xe8bc0d80, 0xe92c000f, 0xe3a00000, 0xe8b9000e,
- 0xebffee51, 0xe3a08102, 0xe3b0a100, 0xe2eab901,
- 0xebffeded, 0xe8bc0d80, 0xebffeea0, 0xe3a04901,
- 0xe2444021, 0xe1530004, 0xba00002c, 0xe92c000f,
- 0xebffee41, 0xe92c000f, 0xe28f9f49, 0xe8b90d00,
- 0xebffed98, 0xe89c0d80, 0xebffee3f, 0xe8b90d00,
- 0xebffed94, 0xe89c0d80, 0xebffee3b, 0xe8b90d00,
- 0xebffed90, 0xe89c0d80, 0xebffee37, 0xe8b90d00,
- 0xebffed8c, 0xe89c0d80, 0xe92c000f, 0xe3a00102,
- 0xe8b9000e, 0xebffee30, 0xe8b90d00, 0xebffedce,
- 0xe28c7010, 0xe8970d80, 0xebffee2b, 0xe8b90d00,
- 0xebffedc9, 0xe28c7010, 0xe8970d80, 0xebffee26,
- 0xe8b90d00, 0xebffedc4, 0xe28c7010, 0xe8970d80,
- 0xebffee21, 0xe8bc0d80, 0xe28cc010, 0xebffee73,
- 0xe89c0d80, 0xebffee1c, 0xe8bc0d80, 0xebffed6e,
- 0xe28f90dc, 0xe8bc0010, 0xe0200f04, 0xe0899204,
- 0xe8990d00, 0xebffed6b, 0xe8bc4230, 0xe3190601,
- 0x10200004, 0x1afffc3b, 0xe3150102, 0x0a000005,
- 0xe92c4010, 0xe2200102, 0xe24f7d0d, 0xe8970d00,
- 0xebffed60, 0xe8bc4010, 0xe0200004, 0xeafffc31,
- 0xe3530000, 0x0afffc2f, 0xe1914002, 0x1afff83d,
- 0xe28f009c, 0xe890000e, 0xeafffc2a, 0x8930a2f4,
- 0xf66ab18a, 0x00003ffd, 0xddb3d742, 0xc265539e,
- 0x00003fff, 0xf0624f0a, 0x56388310, 0x00004002,
- 0xee505190, 0x6d1eb4e8, 0x00004004, 0xac509020,
- 0x5b6d243b, 0x00004005, 0xa443e5e6, 0x24ad4b90,
- 0x00004004, 0xd66bd6cd, 0x8c3de934, 0x00003ffe,
- 0x87e9fae4, 0x6b531a29, 0x00004002, 0xa40bfdcf,
- 0x15e65691, 0x00004003, 0xdb053288, 0x30e70eb4,
- 0x00004002, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x860a91c1, 0x6b9b2c23, 0x00003ffe,
- 0x00000000, 0xc90fdaa2, 0x2168c235, 0x00003fff,
- 0x00000000, 0x860a91c1, 0x6b9b2c23, 0x00003fff,
- 0xe92d5001, 0xe24fc05c, 0xe24ccc50, 0xe3a00807,
- 0xe58c0080, 0xe8bd9001, 0xe1a00000, 0xe3100001,
- 0x128f0e15, 0x1a00000a, 0xe3100004, 0x128f0f47,
- 0x1a000007, 0xe3100002, 0x128f00e0, 0x1a000004,
- 0xe3100008, 0x128f00a8, 0x1a000001, 0xe28f0070,
- 0xeaffffff, 0xe28f101c, 0xe14fb000, 0xe8bd07f8,
- 0xe8a107f8, 0xe8bd07f8, 0xe24aa004, 0xe8a10ff8,
- 0xe28f1000, 0xef000071, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x00002278,
- 0xffffffff, 0x80000204, 0x616f6c46, 0x676e6974,
- 0x696f5020, 0x4520746e, 0x70656378, 0x6e6f6974,
- 0x49203a20, 0x6178656e, 0x52207463, 0x6c757365,
- 0x00000074, 0x80000203, 0x616f6c46, 0x676e6974,
- 0x696f5020, 0x4520746e, 0x70656378, 0x6e6f6974,
- 0x55203a20, 0x7265646e, 0x776f6c66, 0x00000000,
- 0x80000202, 0x616f6c46, 0x676e6974, 0x696f5020,
- 0x4520746e, 0x70656378, 0x6e6f6974, 0x44203a20,
- 0x64697669, 0x79422065, 0x72655a20, 0x0000006f,
- 0x80000201, 0x616f6c46, 0x676e6974, 0x696f5020,
- 0x4520746e, 0x70656378, 0x6e6f6974, 0x4f203a20,
- 0x66726576, 0x00776f6c, 0x80000200, 0x616f6c46,
- 0x676e6974, 0x696f5020, 0x4520746e, 0x70656378,
- 0x6e6f6974, 0x49203a20, 0x6c61766e, 0x4f206469,
- 0x61726570, 0x6e6f6974, 0x00000000, 0xfefefeff, 0
-};
-
-unsigned long fpesize = 0x00005300;
+++ /dev/null
-/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* This must come before any other includes. */
-#include "defs.h"
-
-#include <string.h>
-
-#include "armdefs.h"
-#include "armemu.h"
-#include "dbg_rdi.h"
-
-/***************************************************************************\
-* Definitions for the emulator architecture *
-\***************************************************************************/
-
-void ARMul_EmulateInit (void);
-ARMul_State *ARMul_NewState (void);
-void ARMul_Reset (ARMul_State * state);
-ARMword ARMul_DoCycle (ARMul_State * state);
-unsigned ARMul_DoCoPro (ARMul_State * state);
-ARMword ARMul_DoProg (ARMul_State * state);
-ARMword ARMul_DoInstr (ARMul_State * state);
-void ARMul_Abort (ARMul_State * state, ARMword address);
-
-unsigned ARMul_MultTable[32] =
- { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
- 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
-};
-ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */
-char ARMul_BitList[256]; /* number of bits in a byte table */
-
-/* The PC pipeline value depends on whether ARM
- or Thumb instructions are being executed. */
-ARMword isize;
-
-/***************************************************************************\
-* Call this routine once to set up the emulator's tables. *
-\***************************************************************************/
-
-void
-ARMul_EmulateInit (void)
-{
- unsigned long i, j;
-
- for (i = 0; i < 4096; i++)
- { /* the values of 12 bit dp rhs's */
- ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL);
- }
-
- for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */
- for (j = 1; j < 256; j <<= 1)
- for (i = 0; i < 256; i++)
- if ((i & j) > 0)
- ARMul_BitList[i]++;
-
- for (i = 0; i < 256; i++)
- ARMul_BitList[i] *= 4; /* you always need 4 times these values */
-
-}
-
-/***************************************************************************\
-* Returns a new instantiation of the ARMulator's state *
-\***************************************************************************/
-
-ARMul_State *
-ARMul_NewState (void)
-{
- ARMul_State *state;
- unsigned i, j;
-
- state = (ARMul_State *) malloc (sizeof (ARMul_State));
- memset (state, 0, sizeof (ARMul_State));
-
- state->Emulate = RUN;
- for (i = 0; i < 16; i++)
- {
- state->Reg[i] = 0;
- for (j = 0; j < 7; j++)
- state->RegBank[j][i] = 0;
- }
- for (i = 0; i < 7; i++)
- state->Spsr[i] = 0;
-
- /* state->Mode = USER26MODE; */
- state->Mode = USER32MODE;
-
- state->CallDebug = FALSE;
- state->Debug = FALSE;
- state->VectorCatch = 0;
- state->Aborted = FALSE;
- state->Reseted = FALSE;
- state->Inted = 3;
- state->LastInted = 3;
-
- state->MemDataPtr = NULL;
- state->MemInPtr = NULL;
- state->MemOutPtr = NULL;
- state->MemSparePtr = NULL;
- state->MemSize = 0;
-
- state->OSptr = NULL;
- state->CommandLine = NULL;
-
- state->CP14R0_CCD = -1;
- state->LastTime = 0;
-
- state->EventSet = 0;
- state->Now = 0;
- state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
- sizeof (struct EventNode
- *));
- for (i = 0; i < EVENTLISTSIZE; i++)
- *(state->EventPtr + i) = NULL;
-
- state->prog32Sig = HIGH;
- state->data32Sig = HIGH;
-
- state->lateabtSig = LOW;
- state->bigendSig = LOW;
-
- state->is_v4 = LOW;
- state->is_v5 = LOW;
- state->is_v5e = LOW;
- state->is_XScale = LOW;
- state->is_iWMMXt = LOW;
- state->is_v6 = LOW;
-
- ARMul_Reset (state);
-
- return state;
-}
-
-/***************************************************************************\
- Call this routine to set ARMulator to model certain processor properities
-\***************************************************************************/
-
-void
-ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
-{
- if (properties & ARM_Fix26_Prop)
- {
- state->prog32Sig = LOW;
- state->data32Sig = LOW;
- }
- else
- {
- state->prog32Sig = HIGH;
- state->data32Sig = HIGH;
- }
-
- state->lateabtSig = LOW;
-
- state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW;
- state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
- state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
- state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW;
- state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW;
- state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW;
- state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW;
-
- /* Only initialse the coprocessor support once we
- know what kind of chip we are dealing with. */
- ARMul_CoProInit (state);
-}
-
-/***************************************************************************\
-* Call this routine to set up the initial machine state (or perform a RESET *
-\***************************************************************************/
-
-void
-ARMul_Reset (ARMul_State * state)
-{
- state->NextInstr = 0;
-
- if (state->prog32Sig)
- {
- state->Reg[15] = 0;
- state->Cpsr = INTBITS | SVC32MODE;
- state->Mode = SVC32MODE;
- }
- else
- {
- state->Reg[15] = R15INTBITS | SVC26MODE;
- state->Cpsr = INTBITS | SVC26MODE;
- state->Mode = SVC26MODE;
- }
-
- ARMul_CPSRAltered (state);
- state->Bank = SVCBANK;
-
- FLUSHPIPE;
-
- state->EndCondition = 0;
-
- state->Exception = FALSE;
- state->NresetSig = HIGH;
- state->NfiqSig = HIGH;
- state->NirqSig = HIGH;
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- state->abortSig = LOW;
- state->AbortAddr = 1;
-
- state->NumInstrs = 0;
- state->NumNcycles = 0;
- state->NumScycles = 0;
- state->NumIcycles = 0;
- state->NumCcycles = 0;
- state->NumFcycles = 0;
-#ifdef ASIM
- (void) ARMul_MemoryInit ();
- ARMul_OSInit (state);
-#endif
-}
-
-
-/***************************************************************************\
-* Emulate the execution of an entire program. Start the correct emulator *
-* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
-* address of the last instruction that is executed. *
-\***************************************************************************/
-
-ARMword
-ARMul_DoProg (ARMul_State * state)
-{
- ARMword pc = 0;
-
- state->Emulate = RUN;
- while (state->Emulate != STOP)
- {
- state->Emulate = RUN;
- if (state->prog32Sig && ARMul_MODE32BIT)
- pc = ARMul_Emulate32 (state);
- else
- pc = ARMul_Emulate26 (state);
- }
- return (pc);
-}
-
-/***************************************************************************\
-* Emulate the execution of one instruction. Start the correct emulator *
-* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
-* address of the instruction that is executed. *
-\***************************************************************************/
-
-ARMword
-ARMul_DoInstr (ARMul_State * state)
-{
- ARMword pc = 0;
-
- state->Emulate = ONCE;
- if (state->prog32Sig && ARMul_MODE32BIT)
- pc = ARMul_Emulate32 (state);
- else
- pc = ARMul_Emulate26 (state);
-
- return (pc);
-}
-
-/***************************************************************************\
-* This routine causes an Abort to occur, including selecting the correct *
-* mode, register bank, and the saving of registers. Call with the *
-* appropriate vector's memory address (0,4,8 ....) *
-\***************************************************************************/
-
-void
-ARMul_Abort (ARMul_State * state, ARMword vector)
-{
- ARMword temp;
- int isize = INSN_SIZE;
- int esize = (TFLAG ? 0 : 4);
- int e2size = (TFLAG ? -4 : 0);
-
- state->Aborted = FALSE;
-
- if (state->prog32Sig)
- if (ARMul_MODE26BIT)
- temp = R15PC;
- else
- temp = state->Reg[15];
- else
- temp = R15PC | ECC | ER15INT | EMODE;
-
- switch (vector)
- {
- case ARMul_ResetV: /* RESET */
- SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0);
- break;
- case ARMul_UndefinedInstrV: /* Undefined Instruction */
- SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize);
- break;
- case ARMul_SWIV: /* Software Interrupt */
- SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize);
- break;
- case ARMul_PrefetchAbortV: /* Prefetch Abort */
- state->AbortAddr = 1;
- SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize);
- break;
- case ARMul_DataAbortV: /* Data Abort */
- SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size);
- break;
- case ARMul_AddrExceptnV: /* Address Exception */
- SETABORT (IBIT, SVC26MODE, isize);
- break;
- case ARMul_IRQV: /* IRQ */
- if ( ! state->is_XScale
- || ! state->CPRead[13] (state, 0, & temp)
- || (temp & ARMul_CP13_R0_IRQ))
- SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
- break;
- case ARMul_FIQV: /* FIQ */
- if ( ! state->is_XScale
- || ! state->CPRead[13] (state, 0, & temp)
- || (temp & ARMul_CP13_R0_FIQ))
- SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
- break;
- }
- if (ARMul_MODE32BIT)
- ARMul_SetR15 (state, vector);
- else
- ARMul_SetR15 (state, R15CCINTMODE | vector);
-
- if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0)
- {
- /* No vector has been installed. Rather than simulating whatever
- random bits might happen to be at address 0x20 onwards we elect
- to stop. */
- switch (vector)
- {
- case ARMul_ResetV: state->EndCondition = RDIError_Reset; break;
- case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break;
- case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break;
- case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break;
- case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break;
- case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break;
- case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break;
- case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break;
- default: break;
- }
- state->Emulate = FALSE;
- }
-}
+++ /dev/null
-/* armos.c -- ARMulator OS interface: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* This file contains a model of Demon, ARM Ltd's Debug Monitor,
- including all the SWI's required to support the C library. The code in
- it is not really for the faint-hearted (especially the abort handling
- code), but it is a complete example. Defining NOOS will disable all the
- fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI
- 0x11 to halt the emulator. */
-
-/* This must come before any other includes. */
-#include "defs.h"
-
-#include "ansidecl.h"
-#include "libiberty.h"
-
-#include <time.h>
-#include <errno.h>
-#include <limits.h>
-#include <string.h>
-#include <unistd.h> /* For SEEK_SET etc. */
-
-#include "armdefs.h"
-#include "armos.h"
-#include "armemu.h"
-
-#ifndef NOOS
-#ifndef VALIDATE
-/* #ifndef ASIM */
-#include "armfpe.h"
-/* #endif */
-#endif
-#endif
-
-/* For RDIError_BreakpointReached. */
-#include "dbg_rdi.h"
-
-#include "sim/callback.h"
-extern host_callback *sim_callback;
-
-extern unsigned ARMul_OSInit (ARMul_State *);
-extern unsigned ARMul_OSHandleSWI (ARMul_State *, ARMword);
-
-#ifndef FOPEN_MAX
-#define FOPEN_MAX 64
-#endif
-#ifndef PATH_MAX
-#define PATH_MAX 1024
-#endif
-
-/* OS private Information. */
-
-struct OSblock
-{
- ARMword ErrorNo;
-};
-
-/* Bit mask of enabled SWI implementations. */
-unsigned int swi_mask = -1;
-
-
-static ARMword softvectorcode[] =
-{
- /* Installed instructions:
- swi tidyexception + event;
- mov lr, pc;
- ldmia fp, {fp, pc};
- swi generateexception + event. */
- 0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */
- 0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */
- 0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */
- 0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /* Prefetch abort */
- 0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /* Data abort */
- 0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /* Address exception */
- 0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /* IRQ */
- 0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /* FIQ */
- 0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /* Error */
- 0xe1a0f00e /* Default handler */
-};
-
-/* Time for the Operating System to initialise itself. */
-
-unsigned
-ARMul_OSInit (ARMul_State * state)
-{
-#ifndef NOOS
-#ifndef VALIDATE
- ARMword instr, i, j;
-
- if (state->OSptr == NULL)
- {
- state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock));
- if (state->OSptr == NULL)
- {
- perror ("OS Memory");
- exit (15);
- }
- }
-
- state->Reg[13] = ADDRSUPERSTACK; /* Set up a stack for the current mode... */
- ARMul_SetReg (state, SVC32MODE, 13, ADDRSUPERSTACK);/* ...and for supervisor mode... */
- ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK);/* ...and for abort 32 mode... */
- ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK);/* ...and for undef 32 mode... */
- ARMul_SetReg (state, SYSTEMMODE, 13, ADDRSUPERSTACK);/* ...and for system mode. */
- instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* Load pc from soft vector */
-
- for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
- /* Write hardware vectors. */
- ARMul_WriteWord (state, i, instr);
-
- SWI_vector_installed = 0;
-
- for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4)
- {
- ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4);
- ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L,
- SOFTVECTORCODE + sizeof (softvectorcode) - 4L);
- }
-
- for (i = 0; i < sizeof (softvectorcode); i += 4)
- ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]);
-
- ARMul_ConsolePrint (state, ", Demon 1.01");
-
-/* #ifndef ASIM */
-
- /* Install FPE. */
- for (i = 0; i < fpesize; i += 4)
- /* Copy the code. */
- ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]);
-
- /* Scan backwards from the end of the code. */
- for (i = FPESTART + fpesize;; i -= 4)
- {
- /* When we reach the marker value, break out of
- the loop, leaving i pointing at the maker. */
- if ((j = ARMul_ReadWord (state, i)) == 0xffffffff)
- break;
-
- /* If necessary, reverse the error strings. */
- if (state->bigendSig && j < 0x80000000)
- {
- /* It's part of the string so swap it. */
- j = ((j >> 0x18) & 0x000000ff) |
- ((j >> 0x08) & 0x0000ff00) |
- ((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000);
- ARMul_WriteWord (state, i, j);
- }
- }
-
- /* Copy old illegal instr vector. */
- ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV));
- /* Install new vector. */
- ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4)));
- ARMul_ConsolePrint (state, ", FPE");
-
-/* #endif ASIM */
-#endif /* VALIDATE */
-#endif /* NOOS */
-
- /* Intel do not want DEMON SWI support. */
- if (state->is_XScale)
- swi_mask = SWI_MASK_ANGEL;
-
- return TRUE;
-}
-
-/* These are libgloss defines, but seem to be common across all supported ARM
- targets at the moment. These should get moved to the callback open_map. */
-#define TARGET_O_BINARY 0
-#define TARGET_O_APPEND 0x8
-#define TARGET_O_CREAT 0x200
-#define TARGET_O_RDONLY 0x0
-#define TARGET_O_RDWR 0x2
-#define TARGET_O_TRUNC 0x400
-#define TARGET_O_WRONLY 0x1
-
-static const int translate_open_mode[] =
-{
- TARGET_O_RDONLY, /* "r" */
- TARGET_O_RDONLY + TARGET_O_BINARY, /* "rb" */
- TARGET_O_RDWR, /* "r+" */
- TARGET_O_RDWR + TARGET_O_BINARY, /* "r+b" */
- TARGET_O_WRONLY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w" */
- TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "wb" */
- TARGET_O_RDWR + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+" */
- TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+b" */
- TARGET_O_WRONLY + TARGET_O_APPEND + TARGET_O_CREAT, /* "a" */
- TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT, /* "ab" */
- TARGET_O_RDWR + TARGET_O_APPEND + TARGET_O_CREAT, /* "a+" */
- TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT /* "a+b" */
-};
-
-static void
-SWIWrite0 (ARMul_State * state, ARMword addr)
-{
- ARMword temp;
- struct OSblock *OSptr = (struct OSblock *) state->OSptr;
-
- while ((temp = ARMul_SafeReadByte (state, addr++)) != 0)
- {
- char buffer = temp;
- /* Note - we cannot just cast 'temp' to a (char *) here,
- since on a big-endian host the byte value will end
- up in the wrong place and a nul character will be printed. */
- (void) sim_callback->write_stdout (sim_callback, & buffer, 1);
- }
-
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
-}
-
-static void
-WriteCommandLineTo (ARMul_State * state, ARMword addr)
-{
- ARMword temp;
- char *cptr = state->CommandLine;
-
- if (cptr == NULL)
- cptr = "\0";
- do
- {
- temp = (ARMword) * cptr++;
- ARMul_SafeWriteByte (state, addr++, temp);
- }
- while (temp != 0);
-}
-
-static int
-ReadFileName (ARMul_State * state, char *buf, ARMword src, size_t n)
-{
- struct OSblock *OSptr = (struct OSblock *) state->OSptr;
- char *p = buf;
-
- while (n--)
- if ((*p++ = ARMul_SafeReadByte (state, src++)) == '\0')
- return 0;
- OSptr->ErrorNo = cb_host_to_target_errno (sim_callback, ENAMETOOLONG);
- state->Reg[0] = -1;
- return -1;
-}
-
-static void
-SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
-{
- struct OSblock *OSptr = (struct OSblock *) state->OSptr;
- char buf[PATH_MAX];
- int flags;
-
- if (ReadFileName (state, buf, name, sizeof buf) == -1)
- return;
-
- /* Now we need to decode the Demon open mode. */
- if (SWIflags >= ARRAY_SIZE (translate_open_mode))
- flags = 0;
- else
- flags = translate_open_mode[SWIflags];
-
- /* Filename ":tt" is special: it denotes stdin/out. */
- if (strcmp (buf, ":tt") == 0)
- {
- if (flags == TARGET_O_RDONLY) /* opening tty "r" */
- state->Reg[0] = 0; /* stdin */
- else
- state->Reg[0] = 1; /* stdout */
- }
- else
- {
- state->Reg[0] = sim_callback->open (sim_callback, buf, flags);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- }
-}
-
-static void
-SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
-{
- struct OSblock *OSptr = (struct OSblock *) state->OSptr;
- int res;
- int i;
- char *local = malloc (len);
-
- if (local == NULL)
- {
- sim_callback->printf_filtered
- (sim_callback,
- "sim: Unable to read 0x%lx bytes - out of memory\n",
- (long)len);
- return;
- }
-
- res = sim_callback->read (sim_callback, f, local, len);
- if (res > 0)
- for (i = 0; i < res; i++)
- ARMul_SafeWriteByte (state, ptr + i, local[i]);
-
- free (local);
- state->Reg[0] = res == -1 ? -1 : len - res;
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
-}
-
-static void
-SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
-{
- struct OSblock *OSptr = (struct OSblock *) state->OSptr;
- int res;
- ARMword i;
- char *local = malloc (len);
-
- if (local == NULL)
- {
- sim_callback->printf_filtered
- (sim_callback,
- "sim: Unable to write 0x%lx bytes - out of memory\n",
- (long) len);
- return;
- }
-
- for (i = 0; i < len; i++)
- local[i] = ARMul_SafeReadByte (state, ptr + i);
-
- res = sim_callback->write (sim_callback, f, local, len);
- state->Reg[0] = res == -1 ? -1 : len - res;
- free (local);
-
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
-}
-
-static void
-SWIflen (ARMul_State * state, ARMword fh)
-{
- struct OSblock *OSptr = (struct OSblock *) state->OSptr;
- ARMword addr;
-
- if (fh > FOPEN_MAX)
- {
- OSptr->ErrorNo = EBADF;
- state->Reg[0] = -1L;
- return;
- }
-
- addr = sim_callback->lseek (sim_callback, fh, 0, SEEK_CUR);
-
- state->Reg[0] = sim_callback->lseek (sim_callback, fh, 0L, SEEK_END);
- (void) sim_callback->lseek (sim_callback, fh, addr, SEEK_SET);
-
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
-}
-
-static void
-SWIremove (ARMul_State * state, ARMword path)
-{
- char buf[PATH_MAX];
-
- if (ReadFileName (state, buf, path, sizeof buf) != -1)
- {
- struct OSblock *OSptr = (struct OSblock *) state->OSptr;
- state->Reg[0] = sim_callback->unlink (sim_callback, buf);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- }
-}
-
-static void
-SWIrename (ARMul_State * state, ARMword old, ARMword new)
-{
- char oldbuf[PATH_MAX], newbuf[PATH_MAX];
-
- if (ReadFileName (state, oldbuf, old, sizeof oldbuf) != -1
- && ReadFileName (state, newbuf, new, sizeof newbuf) != -1)
- {
- struct OSblock *OSptr = (struct OSblock *) state->OSptr;
- state->Reg[0] = sim_callback->rename (sim_callback, oldbuf, newbuf);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- }
-}
-
-/* The emulator calls this routine when a SWI instruction is encuntered.
- The parameter passed is the SWI number (lower 24 bits of the instruction). */
-
-unsigned
-ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
-{
- struct OSblock * OSptr = (struct OSblock *) state->OSptr;
- int unhandled = FALSE;
-
- switch (number)
- {
- case SWI_Read:
- if (swi_mask & SWI_MASK_DEMON)
- SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]);
- else
- unhandled = TRUE;
- break;
-
- case SWI_Write:
- if (swi_mask & SWI_MASK_DEMON)
- SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]);
- else
- unhandled = TRUE;
- break;
-
- case SWI_Open:
- if (swi_mask & SWI_MASK_DEMON)
- SWIopen (state, state->Reg[0], state->Reg[1]);
- else
- unhandled = TRUE;
- break;
-
- case SWI_Clock:
- if (swi_mask & SWI_MASK_DEMON)
- {
- /* Return number of centi-seconds. */
- state->Reg[0] =
-#ifdef CLOCKS_PER_SEC
- (CLOCKS_PER_SEC >= 100)
- ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
- : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
-#else
- /* Presume unix... clock() returns microseconds. */
- (ARMword) (clock () / 10000);
-#endif
- OSptr->ErrorNo = errno;
- }
- else
- unhandled = TRUE;
- break;
-
- case SWI_Time:
- if (swi_mask & SWI_MASK_DEMON)
- {
- state->Reg[0] = (ARMword) sim_callback->time (sim_callback);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- }
- else
- unhandled = TRUE;
- break;
-
- case SWI_Close:
- if (swi_mask & SWI_MASK_DEMON)
- {
- state->Reg[0] = sim_callback->close (sim_callback, state->Reg[0]);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- }
- else
- unhandled = TRUE;
- break;
-
- case SWI_Flen:
- if (swi_mask & SWI_MASK_DEMON)
- SWIflen (state, state->Reg[0]);
- else
- unhandled = TRUE;
- break;
-
- case SWI_Exit:
- if (swi_mask & SWI_MASK_DEMON)
- state->Emulate = FALSE;
- else
- unhandled = TRUE;
- break;
-
- case SWI_Seek:
- if (swi_mask & SWI_MASK_DEMON)
- {
- /* We must return non-zero for failure. */
- state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- }
- else
- unhandled = TRUE;
- break;
-
- case SWI_WriteC:
- if (swi_mask & SWI_MASK_DEMON)
- {
- char tmp = state->Reg[0];
- (void) sim_callback->write_stdout (sim_callback, &tmp, 1);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- }
- else
- unhandled = TRUE;
- break;
-
- case SWI_Write0:
- if (swi_mask & SWI_MASK_DEMON)
- SWIWrite0 (state, state->Reg[0]);
- else
- unhandled = TRUE;
- break;
-
- case SWI_GetErrno:
- if (swi_mask & SWI_MASK_DEMON)
- state->Reg[0] = OSptr->ErrorNo;
- else
- unhandled = TRUE;
- break;
-
- case SWI_GetEnv:
- if (swi_mask & SWI_MASK_DEMON)
- {
- state->Reg[0] = ADDRCMDLINE;
- if (state->MemSize)
- state->Reg[1] = state->MemSize;
- else
- state->Reg[1] = ADDRUSERSTACK;
-
- WriteCommandLineTo (state, state->Reg[0]);
- }
- else
- unhandled = TRUE;
- break;
-
- case SWI_Breakpoint:
- state->EndCondition = RDIError_BreakpointReached;
- state->Emulate = FALSE;
- break;
-
- case SWI_Remove:
- if (swi_mask & SWI_MASK_DEMON)
- SWIremove (state, state->Reg[0]);
- else
- unhandled = TRUE;
- break;
-
- case SWI_Rename:
- if (swi_mask & SWI_MASK_DEMON)
- SWIrename (state, state->Reg[0], state->Reg[1]);
- else
- unhandled = TRUE;
- break;
-
- case SWI_IsTTY:
- if (swi_mask & SWI_MASK_DEMON)
- {
- state->Reg[0] = sim_callback->isatty (sim_callback, state->Reg[0]);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- }
- else
- unhandled = TRUE;
- break;
-
- /* Handle Angel SWIs as well as Demon ones. */
- case AngelSWI_ARM:
- case AngelSWI_Thumb:
- if (swi_mask & SWI_MASK_ANGEL)
- {
- ARMword addr;
- ARMword temp;
-
- /* R1 is almost always a parameter block. */
- addr = state->Reg[1];
- /* R0 is a reason code. */
- switch (state->Reg[0])
- {
- case -1:
- /* This can happen when a SWI is interrupted (eg receiving a
- ctrl-C whilst processing SWIRead()). The SWI will complete
- returning -1 in r0 to the caller. If GDB is then used to
- resume the system call the reason code will now be -1. */
- return TRUE;
-
- /* Unimplemented reason codes. */
- case AngelSWI_Reason_ReadC:
- case AngelSWI_Reason_TmpNam:
- case AngelSWI_Reason_System:
- case AngelSWI_Reason_EnterSVC:
- default:
- state->Emulate = FALSE;
- return FALSE;
-
- case AngelSWI_Reason_Clock:
- /* Return number of centi-seconds. */
- state->Reg[0] =
-#ifdef CLOCKS_PER_SEC
- (CLOCKS_PER_SEC >= 100)
- ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
- : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
-#else
- /* Presume unix... clock() returns microseconds. */
- (ARMword) (clock () / 10000);
-#endif
- OSptr->ErrorNo = errno;
- break;
-
- case AngelSWI_Reason_Time:
- state->Reg[0] = (ARMword) sim_callback->time (sim_callback);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- break;
-
- case AngelSWI_Reason_WriteC:
- {
- char tmp = ARMul_SafeReadByte (state, addr);
- (void) sim_callback->write_stdout (sim_callback, &tmp, 1);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- break;
- }
-
- case AngelSWI_Reason_Write0:
- SWIWrite0 (state, addr);
- break;
-
- case AngelSWI_Reason_Close:
- state->Reg[0] = sim_callback->close (sim_callback, ARMul_ReadWord (state, addr));
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- break;
-
- case AngelSWI_Reason_Seek:
- state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, ARMul_ReadWord (state, addr),
- ARMul_ReadWord (state, addr + 4),
- SEEK_SET);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- break;
-
- case AngelSWI_Reason_FLen:
- SWIflen (state, ARMul_ReadWord (state, addr));
- break;
-
- case AngelSWI_Reason_GetCmdLine:
- WriteCommandLineTo (state, ARMul_ReadWord (state, addr));
- break;
-
- case AngelSWI_Reason_HeapInfo:
- /* R1 is a pointer to a pointer. */
- addr = ARMul_ReadWord (state, addr);
-
- /* Pick up the right memory limit. */
- if (state->MemSize)
- temp = state->MemSize;
- else
- temp = ADDRUSERSTACK;
-
- ARMul_WriteWord (state, addr, 0); /* Heap base. */
- ARMul_WriteWord (state, addr + 4, temp); /* Heap limit. */
- ARMul_WriteWord (state, addr + 8, temp); /* Stack base. */
- ARMul_WriteWord (state, addr + 12, temp); /* Stack limit. */
- break;
-
- case AngelSWI_Reason_ReportException:
- if (state->Reg[1] == ADP_Stopped_ApplicationExit)
- state->Reg[0] = 0;
- else
- state->Reg[0] = -1;
- state->Emulate = FALSE;
- break;
-
- case ADP_Stopped_ApplicationExit:
- state->Reg[0] = 0;
- state->Emulate = FALSE;
- break;
-
- case ADP_Stopped_RunTimeError:
- state->Reg[0] = -1;
- state->Emulate = FALSE;
- break;
-
- case AngelSWI_Reason_Errno:
- state->Reg[0] = OSptr->ErrorNo;
- break;
-
- case AngelSWI_Reason_Open:
- SWIopen (state,
- ARMul_ReadWord (state, addr),
- ARMul_ReadWord (state, addr + 4));
- break;
-
- case AngelSWI_Reason_Read:
- SWIread (state,
- ARMul_ReadWord (state, addr),
- ARMul_ReadWord (state, addr + 4),
- ARMul_ReadWord (state, addr + 8));
- break;
-
- case AngelSWI_Reason_Write:
- SWIwrite (state,
- ARMul_ReadWord (state, addr),
- ARMul_ReadWord (state, addr + 4),
- ARMul_ReadWord (state, addr + 8));
- break;
-
- case AngelSWI_Reason_IsTTY:
- state->Reg[0] = sim_callback->isatty (sim_callback,
- ARMul_ReadWord (state, addr));
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- break;
-
- case AngelSWI_Reason_Remove:
- SWIremove (state,
- ARMul_ReadWord (state, addr));
- break;
-
- case AngelSWI_Reason_Rename:
- SWIrename (state,
- ARMul_ReadWord (state, addr),
- ARMul_ReadWord (state, addr + 4));
- break;
- }
- }
- else
- unhandled = TRUE;
- break;
-
- /* The following SWIs are generated by the softvectorcode[]
- installed by default by the simulator. */
- case 0x91: /* Undefined Instruction. */
- {
- ARMword addr = state->RegBank[UNDEFBANK][14] - 4;
-
- sim_callback->printf_filtered
- (sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x. Stopping.\n",
- ARMul_ReadWord (state, addr), addr);
- state->EndCondition = RDIError_SoftwareInterrupt;
- state->Emulate = FALSE;
- return FALSE;
- }
-
- case 0x90: /* Reset. */
- case 0x92: /* SWI. */
- /* These two can be safely ignored. */
- break;
-
- case 0x93: /* Prefetch Abort. */
- case 0x94: /* Data Abort. */
- case 0x95: /* Address Exception. */
- case 0x96: /* IRQ. */
- case 0x97: /* FIQ. */
- case 0x98: /* Error. */
- unhandled = TRUE;
- break;
-
- case -1:
- /* This can happen when a SWI is interrupted (eg receiving a
- ctrl-C whilst processing SWIRead()). The SWI will complete
- returning -1 in r0 to the caller. If GDB is then used to
- resume the system call the reason code will now be -1. */
- return TRUE;
-
- case 0x180001: /* RedBoot's Syscall SWI in ARM mode. */
- if (swi_mask & SWI_MASK_REDBOOT)
- {
- switch (state->Reg[0])
- {
- /* These numbers are defined in libgloss/syscall.h
- but the simulator should not be dependend upon
- libgloss being installed. */
- case 1: /* Exit. */
- state->Emulate = FALSE;
- /* Copy exit code into r0. */
- state->Reg[0] = state->Reg[1];
- break;
-
- case 2: /* Open. */
- SWIopen (state, state->Reg[1], state->Reg[2]);
- break;
-
- case 3: /* Close. */
- state->Reg[0] = sim_callback->close (sim_callback, state->Reg[1]);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- break;
-
- case 4: /* Read. */
- SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]);
- break;
-
- case 5: /* Write. */
- SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]);
- break;
-
- case 6: /* Lseek. */
- state->Reg[0] = sim_callback->lseek (sim_callback,
- state->Reg[1],
- state->Reg[2],
- state->Reg[3]);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- break;
-
- case 17: /* Utime. */
- state->Reg[0] = state->Reg[1] = (ARMword) sim_callback->time (sim_callback);
- OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
- break;
-
- case 7: /* Unlink. */
- case 8: /* Getpid. */
- case 9: /* Kill. */
- case 10: /* Fstat. */
- case 11: /* Sbrk. */
- case 12: /* Argvlen. */
- case 13: /* Argv. */
- case 14: /* ChDir. */
- case 15: /* Stat. */
- case 16: /* Chmod. */
- case 18: /* Time. */
- sim_callback->printf_filtered
- (sim_callback,
- "sim: unhandled RedBoot syscall `%d' encountered - "
- "returning ENOSYS\n",
- state->Reg[0]);
- state->Reg[0] = -1;
- OSptr->ErrorNo = cb_host_to_target_errno
- (sim_callback, ENOSYS);
- break;
- case 1001: /* Meminfo. */
- {
- ARMword totmem = state->Reg[1],
- topmem = state->Reg[2];
- ARMword stack = state->MemSize > 0
- ? state->MemSize : ADDRUSERSTACK;
- if (totmem != 0)
- ARMul_WriteWord (state, totmem, stack);
- if (topmem != 0)
- ARMul_WriteWord (state, topmem, stack);
- state->Reg[0] = 0;
- break;
- }
-
- default:
- sim_callback->printf_filtered
- (sim_callback,
- "sim: unknown RedBoot syscall '%d' encountered - ignoring\n",
- state->Reg[0]);
- return FALSE;
- }
- break;
- }
- ATTRIBUTE_FALLTHROUGH;
-
- default:
- unhandled = TRUE;
- }
-
- if (unhandled)
- {
- if (SWI_vector_installed)
- {
- ARMword cpsr;
- ARMword i_size;
-
- cpsr = ARMul_GetCPSR (state);
- i_size = INSN_SIZE;
-
- ARMul_SetSPSR (state, SVC32MODE, cpsr);
-
- cpsr &= ~0xbf;
- cpsr |= SVC32MODE | 0x80;
- ARMul_SetCPSR (state, cpsr);
-
- state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size;
- state->NextInstr = RESUME;
- state->Reg[15] = state->pc = ARMSWIV;
- FLUSHPIPE;
- }
- else
- {
- sim_callback->printf_filtered
- (sim_callback,
- "sim: unknown SWI encountered - %x - ignoring\n",
- number);
- return FALSE;
- }
- }
-
- return TRUE;
-}
+++ /dev/null
-/* armos.h -- ARMulator OS definitions: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* Define the initial layout of memory. */
-
-#define ADDRSUPERSTACK 0x800L /* Supervisor stack space. */
-#define ADDRUSERSTACK 0x80000L/* Default user stack start. */
-#define ADDRSOFTVECTORS 0x840L /* Soft vectors are here. */
-#define ADDRCMDLINE 0xf00L /* Command line is here after a SWI GetEnv. */
-#define ADDRSOFHANDLERS 0xad0L /* Address and workspace for installed handlers. */
-#define SOFTVECTORCODE 0xb80L /* Default handlers. */
-
-/* SWI numbers. */
-
-#define SWI_WriteC 0x0
-#define SWI_Write0 0x2
-#define SWI_ReadC 0x4
-#define SWI_CLI 0x5
-#define SWI_GetEnv 0x10
-#define SWI_Exit 0x11
-#define SWI_EnterOS 0x16
-
-#define SWI_GetErrno 0x60
-#define SWI_Clock 0x61
-#define SWI_Time 0x63
-#define SWI_Remove 0x64
-#define SWI_Rename 0x65
-#define SWI_Open 0x66
-
-#define SWI_Close 0x68
-#define SWI_Write 0x69
-#define SWI_Read 0x6a
-#define SWI_Seek 0x6b
-#define SWI_Flen 0x6c
-
-#define SWI_IsTTY 0x6e
-#define SWI_TmpNam 0x6f
-#define SWI_InstallHandler 0x70
-#define SWI_GenerateError 0x71
-
-#define SWI_Breakpoint 0x180000 /* See gdb's tm-arm.h */
-
-#define AngelSWI_ARM 0x123456
-#define AngelSWI_Thumb 0xAB
-
-/* The reason codes: */
-#define AngelSWI_Reason_Open 0x01
-#define AngelSWI_Reason_Close 0x02
-#define AngelSWI_Reason_WriteC 0x03
-#define AngelSWI_Reason_Write0 0x04
-#define AngelSWI_Reason_Write 0x05
-#define AngelSWI_Reason_Read 0x06
-#define AngelSWI_Reason_ReadC 0x07
-#define AngelSWI_Reason_IsTTY 0x09
-#define AngelSWI_Reason_Seek 0x0A
-#define AngelSWI_Reason_FLen 0x0C
-#define AngelSWI_Reason_TmpNam 0x0D
-#define AngelSWI_Reason_Remove 0x0E
-#define AngelSWI_Reason_Rename 0x0F
-#define AngelSWI_Reason_Clock 0x10
-#define AngelSWI_Reason_Time 0x11
-#define AngelSWI_Reason_System 0x12
-#define AngelSWI_Reason_Errno 0x13
-#define AngelSWI_Reason_GetCmdLine 0x15
-#define AngelSWI_Reason_HeapInfo 0x16
-#define AngelSWI_Reason_EnterSVC 0x17
-#define AngelSWI_Reason_ReportException 0x18
-#define ADP_Stopped_ApplicationExit ((2 << 16) + 38)
-#define ADP_Stopped_RunTimeError ((2 << 16) + 35)
-
-/* Floating Point Emulator address space. */
-#define FPESTART 0x2000L
-#define FPEEND 0x8000L
-#define FPEOLDVECT FPESTART + 0x100L + 8L * 16L + 4L /* Stack + 8 regs + fpsr. */
-#define FPENEWVECT(addr) 0xea000000L + ((addr) >> 2) - 3L /* Branch from 4 to 0x2400. */
-
-extern unsigned long fpecode[];
-extern unsigned long fpesize;
-
-extern int SWI_vector_installed;
+++ /dev/null
-/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* This must come before any other includes. */
-#include "defs.h"
-
-#include "armdefs.h"
-#include "armemu.h"
-#include "ansidecl.h"
-#include "libiberty.h"
-#include <math.h>
-
-/* Definitions for the support routines. */
-
-static ARMword ModeToBank (ARMword);
-static void EnvokeList (ARMul_State *, unsigned long, unsigned long);
-
-struct EventNode
-{ /* An event list node. */
- unsigned (*func) (ARMul_State *); /* The function to call. */
- struct EventNode *next;
-};
-
-/* This routine returns the value of a register from a mode. */
-
-ARMword
-ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg)
-{
- mode &= MODEBITS;
- if (mode != state->Mode)
- return (state->RegBank[ModeToBank ((ARMword) mode)][reg]);
- else
- return (state->Reg[reg]);
-}
-
-/* This routine sets the value of a register for a mode. */
-
-void
-ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value)
-{
- mode &= MODEBITS;
- if (mode != state->Mode)
- state->RegBank[ModeToBank ((ARMword) mode)][reg] = value;
- else
- state->Reg[reg] = value;
-}
-
-/* This routine returns the value of the PC, mode independently. */
-
-ARMword
-ARMul_GetPC (ARMul_State * state)
-{
- if (state->Mode > SVC26MODE)
- return state->Reg[15];
- else
- return R15PC;
-}
-
-/* This routine returns the value of the PC, mode independently. */
-
-ARMword
-ARMul_GetNextPC (ARMul_State * state)
-{
- if (state->Mode > SVC26MODE)
- return state->Reg[15] + isize;
- else
- return (state->Reg[15] + isize) & R15PCBITS;
-}
-
-/* This routine sets the value of the PC. */
-
-void
-ARMul_SetPC (ARMul_State * state, ARMword value)
-{
- if (ARMul_MODE32BIT)
- state->Reg[15] = value & PCBITS;
- else
- state->Reg[15] = R15CCINTMODE | (value & R15PCBITS);
- FLUSHPIPE;
-}
-
-/* This routine returns the value of register 15, mode independently. */
-
-ARMword
-ARMul_GetR15 (ARMul_State * state)
-{
- if (state->Mode > SVC26MODE)
- return (state->Reg[15]);
- else
- return (R15PC | ECC | ER15INT | EMODE);
-}
-
-/* This routine sets the value of Register 15. */
-
-void
-ARMul_SetR15 (ARMul_State * state, ARMword value)
-{
- if (ARMul_MODE32BIT)
- state->Reg[15] = value & PCBITS;
- else
- {
- state->Reg[15] = value;
- ARMul_R15Altered (state);
- }
- FLUSHPIPE;
-}
-
-/* This routine returns the value of the CPSR. */
-
-ARMword
-ARMul_GetCPSR (ARMul_State * state)
-{
- return (CPSR | state->Cpsr);
-}
-
-/* This routine sets the value of the CPSR. */
-
-void
-ARMul_SetCPSR (ARMul_State * state, ARMword value)
-{
- state->Cpsr = value;
- ARMul_CPSRAltered (state);
-}
-
-/* This routine does all the nasty bits involved in a write to the CPSR,
- including updating the register bank, given a MSR instruction. */
-
-void
-ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
-{
- state->Cpsr = ARMul_GetCPSR (state);
-
- if (state->Mode != USER26MODE
- && state->Mode != USER32MODE)
- {
- /* In user mode, only write flags. */
- if (BIT (16))
- SETPSR_C (state->Cpsr, rhs);
- if (BIT (17))
- SETPSR_X (state->Cpsr, rhs);
- if (BIT (18))
- SETPSR_S (state->Cpsr, rhs);
- }
- if (BIT (19))
- SETPSR_F (state->Cpsr, rhs);
- ARMul_CPSRAltered (state);
-}
-
-/* Get an SPSR from the specified mode. */
-
-ARMword
-ARMul_GetSPSR (ARMul_State * state, ARMword mode)
-{
- ARMword bank = ModeToBank (mode & MODEBITS);
-
- if (! BANK_CAN_ACCESS_SPSR (bank))
- return ARMul_GetCPSR (state);
-
- return state->Spsr[bank];
-}
-
-/* This routine does a write to an SPSR. */
-
-void
-ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value)
-{
- ARMword bank = ModeToBank (mode & MODEBITS);
-
- if (BANK_CAN_ACCESS_SPSR (bank))
- state->Spsr[bank] = value;
-}
-
-/* This routine does a write to the current SPSR, given an MSR instruction. */
-
-void
-ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs)
-{
- if (BANK_CAN_ACCESS_SPSR (state->Bank))
- {
- if (BIT (16))
- SETPSR_C (state->Spsr[state->Bank], rhs);
- if (BIT (17))
- SETPSR_X (state->Spsr[state->Bank], rhs);
- if (BIT (18))
- SETPSR_S (state->Spsr[state->Bank], rhs);
- if (BIT (19))
- SETPSR_F (state->Spsr[state->Bank], rhs);
- }
-}
-
-/* This routine updates the state of the emulator after the Cpsr has been
- changed. Both the processor flags and register bank are updated. */
-
-void
-ARMul_CPSRAltered (ARMul_State * state)
-{
- ARMword oldmode;
-
- if (state->prog32Sig == LOW)
- state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS);
-
- oldmode = state->Mode;
-
- if (state->Mode != (state->Cpsr & MODEBITS))
- {
- state->Mode =
- ARMul_SwitchMode (state, state->Mode, state->Cpsr & MODEBITS);
-
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- }
- state->Cpsr &= ~MODEBITS;
-
- ASSIGNINT (state->Cpsr & INTBITS);
- state->Cpsr &= ~INTBITS;
- ASSIGNN ((state->Cpsr & NBIT) != 0);
- state->Cpsr &= ~NBIT;
- ASSIGNZ ((state->Cpsr & ZBIT) != 0);
- state->Cpsr &= ~ZBIT;
- ASSIGNC ((state->Cpsr & CBIT) != 0);
- state->Cpsr &= ~CBIT;
- ASSIGNV ((state->Cpsr & VBIT) != 0);
- state->Cpsr &= ~VBIT;
- ASSIGNS ((state->Cpsr & SBIT) != 0);
- state->Cpsr &= ~SBIT;
-#ifdef MODET
- ASSIGNT ((state->Cpsr & TBIT) != 0);
- state->Cpsr &= ~TBIT;
-#endif
-
- if (oldmode > SVC26MODE)
- {
- if (state->Mode <= SVC26MODE)
- {
- state->Emulate = CHANGEMODE;
- state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
- }
- }
- else
- {
- if (state->Mode > SVC26MODE)
- {
- state->Emulate = CHANGEMODE;
- state->Reg[15] = R15PC;
- }
- else
- state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
- }
-}
-
-/* This routine updates the state of the emulator after register 15 has
- been changed. Both the processor flags and register bank are updated.
- This routine should only be called from a 26 bit mode. */
-
-void
-ARMul_R15Altered (ARMul_State * state)
-{
- if (state->Mode != R15MODE)
- {
- state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE);
- state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
- }
-
- if (state->Mode > SVC26MODE)
- state->Emulate = CHANGEMODE;
-
- ASSIGNR15INT (R15INT);
-
- ASSIGNN ((state->Reg[15] & NBIT) != 0);
- ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
- ASSIGNC ((state->Reg[15] & CBIT) != 0);
- ASSIGNV ((state->Reg[15] & VBIT) != 0);
-}
-
-/* This routine controls the saving and restoring of registers across mode
- changes. The regbank matrix is largely unused, only rows 13 and 14 are
- used across all modes, 8 to 14 are used for FIQ, all others use the USER
- column. It's easier this way. old and new parameter are modes numbers.
- Notice the side effect of changing the Bank variable. */
-
-ARMword
-ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
-{
- unsigned i;
- ARMword oldbank;
- ARMword newbank;
-
- oldbank = ModeToBank (oldmode);
- newbank = state->Bank = ModeToBank (newmode);
-
- /* Do we really need to do it? */
- if (oldbank != newbank)
- {
- /* Save away the old registers. */
- switch (oldbank)
- {
- case USERBANK:
- case IRQBANK:
- case SVCBANK:
- case ABORTBANK:
- case UNDEFBANK:
- if (newbank == FIQBANK)
- for (i = 8; i < 13; i++)
- state->RegBank[USERBANK][i] = state->Reg[i];
- state->RegBank[oldbank][13] = state->Reg[13];
- state->RegBank[oldbank][14] = state->Reg[14];
- break;
- case FIQBANK:
- for (i = 8; i < 15; i++)
- state->RegBank[FIQBANK][i] = state->Reg[i];
- break;
- case DUMMYBANK:
- for (i = 8; i < 15; i++)
- state->RegBank[DUMMYBANK][i] = 0;
- break;
- default:
- abort ();
- }
-
- /* Restore the new registers. */
- switch (newbank)
- {
- case USERBANK:
- case IRQBANK:
- case SVCBANK:
- case ABORTBANK:
- case UNDEFBANK:
- if (oldbank == FIQBANK)
- for (i = 8; i < 13; i++)
- state->Reg[i] = state->RegBank[USERBANK][i];
- state->Reg[13] = state->RegBank[newbank][13];
- state->Reg[14] = state->RegBank[newbank][14];
- break;
- case FIQBANK:
- for (i = 8; i < 15; i++)
- state->Reg[i] = state->RegBank[FIQBANK][i];
- break;
- case DUMMYBANK:
- for (i = 8; i < 15; i++)
- state->Reg[i] = 0;
- break;
- default:
- abort ();
- }
- }
-
- return newmode;
-}
-
-/* Given a processor mode, this routine returns the
- register bank that will be accessed in that mode. */
-
-static ARMword
-ModeToBank (ARMword mode)
-{
- static ARMword bankofmode[] =
- {
- USERBANK, FIQBANK, IRQBANK, SVCBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
- USERBANK, FIQBANK, IRQBANK, SVCBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK,
- DUMMYBANK, DUMMYBANK, DUMMYBANK, SYSTEMBANK
- };
-
- if (mode >= ARRAY_SIZE (bankofmode))
- return DUMMYBANK;
-
- return bankofmode[mode];
-}
-
-/* Returns the register number of the nth register in a reg list. */
-
-unsigned
-ARMul_NthReg (ARMword instr, unsigned number)
-{
- unsigned bit, up_to;
-
- for (bit = 0, up_to = 0; up_to <= number; bit ++)
- if (BIT (bit))
- up_to ++;
-
- return (bit - 1);
-}
-
-/* Assigns the N and Z flags depending on the value of result. */
-
-void
-ARMul_NegZero (ARMul_State * state, ARMword result)
-{
- if (NEG (result))
- {
- SETN;
- CLEARZ;
- }
- else if (result == 0)
- {
- CLEARN;
- SETZ;
- }
- else
- {
- CLEARN;
- CLEARZ;
- }
-}
-
-/* Compute whether an addition of A and B, giving RESULT, overflowed. */
-
-int
-AddOverflow (ARMword a, ARMword b, ARMword result)
-{
- return ((NEG (a) && NEG (b) && POS (result))
- || (POS (a) && POS (b) && NEG (result)));
-}
-
-/* Compute whether a subtraction of A and B, giving RESULT, overflowed. */
-
-int
-SubOverflow (ARMword a, ARMword b, ARMword result)
-{
- return ((NEG (a) && POS (b) && POS (result))
- || (POS (a) && NEG (b) && NEG (result)));
-}
-
-/* Assigns the C flag after an addition of a and b to give result. */
-
-void
-ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
-{
- ASSIGNC ((NEG (a) && NEG (b)) ||
- (NEG (a) && POS (result)) || (NEG (b) && POS (result)));
-}
-
-/* Assigns the V flag after an addition of a and b to give result. */
-
-void
-ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
-{
- ASSIGNV (AddOverflow (a, b, result));
-}
-
-/* Assigns the C flag after an subtraction of a and b to give result. */
-
-void
-ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
-{
- ASSIGNC ((NEG (a) && POS (b)) ||
- (NEG (a) && POS (result)) || (POS (b) && POS (result)));
-}
-
-/* Assigns the V flag after an subtraction of a and b to give result. */
-
-void
-ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
-{
- ASSIGNV (SubOverflow (a, b, result));
-}
-
-static void
-handle_VFP_xfer (ARMul_State * state, ARMword instr)
-{
- if (TOPBITS (28) == NV)
- {
- fprintf (stderr, "SIM: UNDEFINED VFP instruction\n");
- return;
- }
-
- if (BITS (25, 27) != 0x6)
- {
- fprintf (stderr, "SIM: ISE: VFP handler called incorrectly\n");
- return;
- }
-
- switch (BITS (20, 24))
- {
- case 0x04:
- case 0x05:
- {
- /* VMOV double precision to/from two ARM registers. */
- int vm = BITS (0, 3);
- int rt1 = BITS (12, 15);
- int rt2 = BITS (16, 19);
-
- /* FIXME: UNPREDICTABLE if rt1 == 15 or rt2 == 15. */
- if (BIT (20))
- {
- /* Transfer to ARM. */
- /* FIXME: UPPREDICTABLE if rt1 == rt2. */
- state->Reg[rt1] = VFP_dword (vm) & 0xffffffff;
- state->Reg[rt2] = VFP_dword (vm) >> 32;
- }
- else
- {
- VFP_dword (vm) = state->Reg[rt2];
- VFP_dword (vm) <<= 32;
- VFP_dword (vm) |= (state->Reg[rt1] & 0xffffffff);
- }
- return;
- }
-
- case 0x08:
- case 0x0A:
- case 0x0C:
- case 0x0E:
- {
- /* VSTM with PUW=011 or PUW=010. */
- int n = BITS (16, 19);
- int imm8 = BITS (0, 7);
-
- ARMword address = state->Reg[n];
- if (BIT (21))
- state->Reg[n] = address + (imm8 << 2);
-
- if (BIT (8))
- {
- int src = (BIT (22) << 4) | BITS (12, 15);
- imm8 >>= 1;
- while (imm8--)
- {
- if (state->bigendSig)
- {
- ARMul_StoreWordN (state, address, VFP_dword (src) >> 32);
- ARMul_StoreWordN (state, address + 4, VFP_dword (src));
- }
- else
- {
- ARMul_StoreWordN (state, address, VFP_dword (src));
- ARMul_StoreWordN (state, address + 4, VFP_dword (src) >> 32);
- }
- address += 8;
- src += 1;
- }
- }
- else
- {
- int src = (BITS (12, 15) << 1) | BIT (22);
- while (imm8--)
- {
- ARMul_StoreWordN (state, address, VFP_uword (src));
- address += 4;
- src += 1;
- }
- }
- }
- return;
-
- case 0x10:
- case 0x14:
- case 0x18:
- case 0x1C:
- {
- /* VSTR */
- ARMword imm32 = BITS (0, 7) << 2;
- int base = state->Reg[LHSReg];
- ARMword address;
- int dest;
-
- if (LHSReg == 15)
- base = (base + 3) & ~3;
-
- address = base + (BIT (23) ? imm32 : - imm32);
-
- if (CPNum == 10)
- {
- dest = (DESTReg << 1) + BIT (22);
-
- ARMul_StoreWordN (state, address, VFP_uword (dest));
- }
- else
- {
- dest = (BIT (22) << 4) + DESTReg;
-
- if (state->bigendSig)
- {
- ARMul_StoreWordN (state, address, VFP_dword (dest) >> 32);
- ARMul_StoreWordN (state, address + 4, VFP_dword (dest));
- }
- else
- {
- ARMul_StoreWordN (state, address, VFP_dword (dest));
- ARMul_StoreWordN (state, address + 4, VFP_dword (dest) >> 32);
- }
- }
- }
- return;
-
- case 0x12:
- case 0x16:
- if (BITS (16, 19) == 13)
- {
- /* VPUSH */
- ARMword address = state->Reg[13] - (BITS (0, 7) << 2);
- state->Reg[13] = address;
-
- if (BIT (8))
- {
- int dreg = (BIT (22) << 4) | BITS (12, 15);
- int num = BITS (0, 7) >> 1;
- while (num--)
- {
- if (state->bigendSig)
- {
- ARMul_StoreWordN (state, address, VFP_dword (dreg) >> 32);
- ARMul_StoreWordN (state, address + 4, VFP_dword (dreg));
- }
- else
- {
- ARMul_StoreWordN (state, address, VFP_dword (dreg));
- ARMul_StoreWordN (state, address + 4, VFP_dword (dreg) >> 32);
- }
- address += 8;
- dreg += 1;
- }
- }
- else
- {
- int sreg = (BITS (12, 15) << 1) | BIT (22);
- int num = BITS (0, 7);
- while (num--)
- {
- ARMul_StoreWordN (state, address, VFP_uword (sreg));
- address += 4;
- sreg += 1;
- }
- }
- }
- else if (BITS (9, 11) != 0x5)
- break;
- else
- {
- /* VSTM PUW=101 */
- int n = BITS (16, 19);
- int imm8 = BITS (0, 7);
- ARMword address = state->Reg[n] - (imm8 << 2);
- state->Reg[n] = address;
-
- if (BIT (8))
- {
- int src = (BIT (22) << 4) | BITS (12, 15);
-
- imm8 >>= 1;
- while (imm8--)
- {
- if (state->bigendSig)
- {
- ARMul_StoreWordN (state, address, VFP_dword (src) >> 32);
- ARMul_StoreWordN (state, address + 4, VFP_dword (src));
- }
- else
- {
- ARMul_StoreWordN (state, address, VFP_dword (src));
- ARMul_StoreWordN (state, address + 4, VFP_dword (src) >> 32);
- }
- address += 8;
- src += 1;
- }
- }
- else
- {
- int src = (BITS (12, 15) << 1) | BIT (22);
-
- while (imm8--)
- {
- ARMul_StoreWordN (state, address, VFP_uword (src));
- address += 4;
- src += 1;
- }
- }
- }
- return;
-
- case 0x13:
- case 0x17:
- /* VLDM PUW=101 */
- case 0x09:
- case 0x0D:
- /* VLDM PUW=010 */
- {
- int n = BITS (16, 19);
- int imm8 = BITS (0, 7);
-
- ARMword address = state->Reg[n];
- if (BIT (23) == 0)
- address -= imm8 << 2;
- if (BIT (21))
- state->Reg[n] = BIT (23) ? address + (imm8 << 2) : address;
-
- if (BIT (8))
- {
- int dest = (BIT (22) << 4) | BITS (12, 15);
- imm8 >>= 1;
- while (imm8--)
- {
- if (state->bigendSig)
- {
- VFP_dword (dest) = ARMul_LoadWordN (state, address);
- VFP_dword (dest) <<= 32;
- VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
- }
- else
- {
- VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
- VFP_dword (dest) <<= 32;
- VFP_dword (dest) |= ARMul_LoadWordN (state, address);
- }
-
- if (trace)
- fprintf (stderr, " VFP: VLDM: D%d = %g\n", dest, VFP_dval (dest));
-
- address += 8;
- dest += 1;
- }
- }
- else
- {
- int dest = (BITS (12, 15) << 1) | BIT (22);
-
- while (imm8--)
- {
- VFP_uword (dest) = ARMul_LoadWordN (state, address);
- address += 4;
- dest += 1;
- }
- }
- }
- return;
-
- case 0x0B:
- case 0x0F:
- if (BITS (16, 19) == 13)
- {
- /* VPOP */
- ARMword address = state->Reg[13];
- state->Reg[13] = address + (BITS (0, 7) << 2);
-
- if (BIT (8))
- {
- int dest = (BIT (22) << 4) | BITS (12, 15);
- int num = BITS (0, 7) >> 1;
-
- while (num--)
- {
- if (state->bigendSig)
- {
- VFP_dword (dest) = ARMul_LoadWordN (state, address);
- VFP_dword (dest) <<= 32;
- VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
- }
- else
- {
- VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
- VFP_dword (dest) <<= 32;
- VFP_dword (dest) |= ARMul_LoadWordN (state, address);
- }
-
- if (trace)
- fprintf (stderr, " VFP: VPOP: D%d = %g\n", dest, VFP_dval (dest));
-
- address += 8;
- dest += 1;
- }
- }
- else
- {
- int sreg = (BITS (12, 15) << 1) | BIT (22);
- int num = BITS (0, 7);
-
- while (num--)
- {
- VFP_uword (sreg) = ARMul_LoadWordN (state, address);
- address += 4;
- sreg += 1;
- }
- }
- }
- else if (BITS (9, 11) != 0x5)
- break;
- else
- {
- /* VLDM PUW=011 */
- int n = BITS (16, 19);
- int imm8 = BITS (0, 7);
- ARMword address = state->Reg[n];
- state->Reg[n] += imm8 << 2;
-
- if (BIT (8))
- {
- int dest = (BIT (22) << 4) | BITS (12, 15);
-
- imm8 >>= 1;
- while (imm8--)
- {
- if (state->bigendSig)
- {
- VFP_dword (dest) = ARMul_LoadWordN (state, address);
- VFP_dword (dest) <<= 32;
- VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
- }
- else
- {
- VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
- VFP_dword (dest) <<= 32;
- VFP_dword (dest) |= ARMul_LoadWordN (state, address);
- }
-
- if (trace)
- fprintf (stderr, " VFP: VLDM: D%d = %g\n", dest, VFP_dval (dest));
-
- address += 8;
- dest += 1;
- }
- }
- else
- {
- int dest = (BITS (12, 15) << 1) | BIT (22);
- while (imm8--)
- {
- VFP_uword (dest) = ARMul_LoadWordN (state, address);
- address += 4;
- dest += 1;
- }
- }
- }
- return;
-
- case 0x11:
- case 0x15:
- case 0x19:
- case 0x1D:
- {
- /* VLDR */
- ARMword imm32 = BITS (0, 7) << 2;
- int base = state->Reg[LHSReg];
- ARMword address;
- int dest;
-
- if (LHSReg == 15)
- base = (base + 3) & ~3;
-
- address = base + (BIT (23) ? imm32 : - imm32);
-
- if (CPNum == 10)
- {
- dest = (DESTReg << 1) + BIT (22);
-
- VFP_uword (dest) = ARMul_LoadWordN (state, address);
- }
- else
- {
- dest = (BIT (22) << 4) + DESTReg;
-
- if (state->bigendSig)
- {
- VFP_dword (dest) = ARMul_LoadWordN (state, address);
- VFP_dword (dest) <<= 32;
- VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
- }
- else
- {
- VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
- VFP_dword (dest) <<= 32;
- VFP_dword (dest) |= ARMul_LoadWordN (state, address);
- }
-
- if (trace)
- fprintf (stderr, " VFP: VLDR: D%d = %g\n", dest, VFP_dval (dest));
- }
- }
- return;
- }
-
- fprintf (stderr, "SIM: VFP: Unimplemented: %0x\n", BITS (20, 24));
-}
-
-/* This function does the work of generating the addresses used in an
- LDC instruction. The code here is always post-indexed, it's up to the
- caller to get the input address correct and to handle base register
- modification. It also handles the Busy-Waiting. */
-
-void
-ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address)
-{
- unsigned cpab;
- ARMword data;
-
- if (CPNum == 10 || CPNum == 11)
- {
- handle_VFP_xfer (state, instr);
- return;
- }
-
- UNDEF_LSCPCBaseWb;
-
- if (! CP_ACCESS_ALLOWED (state, CPNum))
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- if (ADDREXCEPT (address))
- INTERNALABORT (address);
-
- cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0);
- while (cpab == ARMul_BUSY)
- {
- ARMul_Icycles (state, 1, 0);
-
- if (IntPending (state))
- {
- cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
- return;
- }
- else
- cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr, 0);
- }
- if (cpab == ARMul_CANT)
- {
- CPTAKEABORT;
- return;
- }
-
- cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0);
- data = ARMul_LoadWordN (state, address);
- BUSUSEDINCPCN;
-
- if (BIT (21))
- LSBase = state->Base;
- cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
-
- while (cpab == ARMul_INC)
- {
- address += 4;
- data = ARMul_LoadWordN (state, address);
- cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
- }
-
- if (state->abortSig || state->Aborted)
- TAKEABORT;
-}
-
-/* This function does the work of generating the addresses used in an
- STC instruction. The code here is always post-indexed, it's up to the
- caller to get the input address correct and to handle base register
- modification. It also handles the Busy-Waiting. */
-
-void
-ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
-{
- unsigned cpab;
- ARMword data;
-
- if (CPNum == 10 || CPNum == 11)
- {
- handle_VFP_xfer (state, instr);
- return;
- }
-
- UNDEF_LSCPCBaseWb;
-
- if (! CP_ACCESS_ALLOWED (state, CPNum))
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- if (ADDREXCEPT (address) || VECTORACCESS (address))
- INTERNALABORT (address);
-
- cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data);
- while (cpab == ARMul_BUSY)
- {
- ARMul_Icycles (state, 1, 0);
- if (IntPending (state))
- {
- cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
- return;
- }
- else
- cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr, &data);
- }
-
- if (cpab == ARMul_CANT)
- {
- CPTAKEABORT;
- return;
- }
-#ifndef MODE32
- if (ADDREXCEPT (address) || VECTORACCESS (address))
- INTERNALABORT (address);
-#endif
- BUSUSEDINCPCN;
- if (BIT (21))
- LSBase = state->Base;
- cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
- ARMul_StoreWordN (state, address, data);
-
- while (cpab == ARMul_INC)
- {
- address += 4;
- cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
- ARMul_StoreWordN (state, address, data);
- }
-
- if (state->abortSig || state->Aborted)
- TAKEABORT;
-}
-
-/* This function does the Busy-Waiting for an MCR instruction. */
-
-void
-ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source)
-{
- unsigned cpab;
-
- if (! CP_ACCESS_ALLOWED (state, CPNum))
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source);
-
- while (cpab == ARMul_BUSY)
- {
- ARMul_Icycles (state, 1, 0);
-
- if (IntPending (state))
- {
- cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
- return;
- }
- else
- cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, source);
- }
-
- if (cpab == ARMul_CANT)
- ARMul_Abort (state, ARMul_UndefinedInstrV);
- else
- {
- BUSUSEDINCPCN;
- ARMul_Ccycles (state, 1, 0);
- }
-}
-
-/* This function does the Busy-Waiting for an MRC instruction. */
-
-ARMword
-ARMul_MRC (ARMul_State * state, ARMword instr)
-{
- unsigned cpab;
- ARMword result = 0;
-
- if (! CP_ACCESS_ALLOWED (state, CPNum))
- {
- ARMul_UndefInstr (state, instr);
- return result;
- }
-
- cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result);
- while (cpab == ARMul_BUSY)
- {
- ARMul_Icycles (state, 1, 0);
- if (IntPending (state))
- {
- cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
- return (0);
- }
- else
- cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, &result);
- }
- if (cpab == ARMul_CANT)
- {
- ARMul_Abort (state, ARMul_UndefinedInstrV);
- /* Parent will destroy the flags otherwise. */
- result = ECC;
- }
- else
- {
- BUSUSEDINCPCN;
- ARMul_Ccycles (state, 1, 0);
- ARMul_Icycles (state, 1, 0);
- }
-
- return result;
-}
-
-static void
-handle_VFP_op (ARMul_State * state, ARMword instr)
-{
- int dest;
- int srcN;
- int srcM;
-
- if (BITS (9, 11) != 0x5 || BIT (4) != 0)
- {
- fprintf (stderr, "SIM: VFP: Unimplemented: Float op: %08x\n", BITS (0,31));
- return;
- }
-
- if (BIT (8))
- {
- dest = BITS(12,15) + (BIT (22) << 4);
- srcN = LHSReg + (BIT (7) << 4);
- srcM = BITS (0,3) + (BIT (5) << 4);
- }
- else
- {
- dest = (BITS(12,15) << 1) + BIT (22);
- srcN = (LHSReg << 1) + BIT (7);
- srcM = (BITS (0,3) << 1) + BIT (5);
- }
-
- switch (BITS (20, 27))
- {
- case 0xE0:
- case 0xE4:
- /* VMLA VMLS */
- if (BIT (8))
- {
- ARMdval val = VFP_dval (srcN) * VFP_dval (srcM);
-
- if (BIT (6))
- {
- if (trace)
- fprintf (stderr, " VFP: VMLS: %g = %g - %g * %g\n",
- VFP_dval (dest) - val,
- VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
- VFP_dval (dest) -= val;
- }
- else
- {
- if (trace)
- fprintf (stderr, " VFP: VMLA: %g = %g + %g * %g\n",
- VFP_dval (dest) + val,
- VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
- VFP_dval (dest) += val;
- }
- }
- else
- {
- ARMfval val = VFP_fval (srcN) * VFP_fval (srcM);
-
- if (BIT (6))
- {
- if (trace)
- fprintf (stderr, " VFP: VMLS: %g = %g - %g * %g\n",
- VFP_fval (dest) - val,
- VFP_fval (dest), VFP_fval (srcN), VFP_fval (srcM));
- VFP_fval (dest) -= val;
- }
- else
- {
- if (trace)
- fprintf (stderr, " VFP: VMLA: %g = %g + %g * %g\n",
- VFP_fval (dest) + val,
- VFP_fval (dest), VFP_fval (srcN), VFP_fval (srcM));
- VFP_fval (dest) += val;
- }
- }
- return;
-
- case 0xE1:
- case 0xE5:
- if (BIT (8))
- {
- ARMdval product = VFP_dval (srcN) * VFP_dval (srcM);
-
- if (BIT (6))
- {
- /* VNMLA */
- if (trace)
- fprintf (stderr, " VFP: VNMLA: %g = -(%g + (%g * %g))\n",
- -(VFP_dval (dest) + product),
- VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
- VFP_dval (dest) = -(product + VFP_dval (dest));
- }
- else
- {
- /* VNMLS */
- if (trace)
- fprintf (stderr, " VFP: VNMLS: %g = -(%g + (%g * %g))\n",
- -(VFP_dval (dest) + product),
- VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
- VFP_dval (dest) = product - VFP_dval (dest);
- }
- }
- else
- {
- ARMfval product = VFP_fval (srcN) * VFP_fval (srcM);
-
- if (BIT (6))
- /* VNMLA */
- VFP_fval (dest) = -(product + VFP_fval (dest));
- else
- /* VNMLS */
- VFP_fval (dest) = product - VFP_fval (dest);
- }
- return;
-
- case 0xE2:
- case 0xE6:
- if (BIT (8))
- {
- ARMdval product = VFP_dval (srcN) * VFP_dval (srcM);
-
- if (BIT (6))
- {
- if (trace)
- fprintf (stderr, " VFP: VMUL: %g = %g * %g\n",
- - product, VFP_dval (srcN), VFP_dval (srcM));
- /* VNMUL */
- VFP_dval (dest) = - product;
- }
- else
- {
- if (trace)
- fprintf (stderr, " VFP: VMUL: %g = %g * %g\n",
- product, VFP_dval (srcN), VFP_dval (srcM));
- /* VMUL */
- VFP_dval (dest) = product;
- }
- }
- else
- {
- ARMfval product = VFP_fval (srcN) * VFP_fval (srcM);
-
- if (BIT (6))
- {
- if (trace)
- fprintf (stderr, " VFP: VNMUL: %g = %g * %g\n",
- - product, VFP_fval (srcN), VFP_fval (srcM));
-
- VFP_fval (dest) = - product;
- }
- else
- {
- if (trace)
- fprintf (stderr, " VFP: VMUL: %g = %g * %g\n",
- product, VFP_fval (srcN), VFP_fval (srcM));
-
- VFP_fval (dest) = product;
- }
- }
- return;
-
- case 0xE3:
- case 0xE7:
- if (BIT (6) == 0)
- {
- /* VADD */
- if (BIT(8))
- {
- if (trace)
- fprintf (stderr, " VFP: VADD %g = %g + %g\n",
- VFP_dval (srcN) + VFP_dval (srcM),
- VFP_dval (srcN),
- VFP_dval (srcM));
- VFP_dval (dest) = VFP_dval (srcN) + VFP_dval (srcM);
- }
- else
- VFP_fval (dest) = VFP_fval (srcN) + VFP_fval (srcM);
-
- }
- else
- {
- /* VSUB */
- if (BIT(8))
- {
- if (trace)
- fprintf (stderr, " VFP: VSUB %g = %g - %g\n",
- VFP_dval (srcN) - VFP_dval (srcM),
- VFP_dval (srcN),
- VFP_dval (srcM));
- VFP_dval (dest) = VFP_dval (srcN) - VFP_dval (srcM);
- }
- else
- VFP_fval (dest) = VFP_fval (srcN) - VFP_fval (srcM);
- }
- return;
-
- case 0xE8:
- case 0xEC:
- if (BIT (6) == 1)
- break;
-
- /* VDIV */
- if (BIT (8))
- {
- ARMdval res = VFP_dval (srcN) / VFP_dval (srcM);
- if (trace)
- fprintf (stderr, " VFP: VDIV (64bit): %g = %g / %g\n",
- res, VFP_dval (srcN), VFP_dval (srcM));
- VFP_dval (dest) = res;
- }
- else
- {
- if (trace)
- fprintf (stderr, " VFP: VDIV: %g = %g / %g\n",
- VFP_fval (srcN) / VFP_fval (srcM),
- VFP_fval (srcN), VFP_fval (srcM));
-
- VFP_fval (dest) = VFP_fval (srcN) / VFP_fval (srcM);
- }
- return;
-
- case 0xEB:
- case 0xEF:
- if (BIT (6) != 1)
- break;
-
- switch (BITS (16, 19))
- {
- case 0x0:
- if (BIT (7) == 0)
- {
- if (BIT (8))
- {
- /* VMOV.F64 <Dd>, <Dm>. */
- VFP_dval (dest) = VFP_dval (srcM);
- if (trace)
- fprintf (stderr, " VFP: VMOV d%d, d%d: %g\n", dest, srcM, VFP_dval (srcM));
- }
- else
- {
- /* VMOV.F32 <Sd>, <Sm>. */
- VFP_fval (dest) = VFP_fval (srcM);
- if (trace)
- fprintf (stderr, " VFP: VMOV s%d, s%d: %g\n", dest, srcM, VFP_fval (srcM));
- }
- }
- else
- {
- /* VABS */
- if (BIT (8))
- {
- ARMdval src = VFP_dval (srcM);
-
- VFP_dval (dest) = fabs (src);
- if (trace)
- fprintf (stderr, " VFP: VABS (%g) = %g\n", src, VFP_dval (dest));
- }
- else
- {
- ARMfval src = VFP_fval (srcM);
-
- VFP_fval (dest) = fabsf (src);
- if (trace)
- fprintf (stderr, " VFP: VABS (%g) = %g\n", src, VFP_fval (dest));
- }
- }
- return;
-
- case 0x1:
- if (BIT (7) == 0)
- {
- /* VNEG */
- if (BIT (8))
- VFP_dval (dest) = - VFP_dval (srcM);
- else
- VFP_fval (dest) = - VFP_fval (srcM);
- }
- else
- {
- /* VSQRT */
- if (BIT (8))
- {
- if (trace)
- fprintf (stderr, " VFP: %g = root(%g)\n",
- sqrt (VFP_dval (srcM)), VFP_dval (srcM));
-
- VFP_dval (dest) = sqrt (VFP_dval (srcM));
- }
- else
- {
- if (trace)
- fprintf (stderr, " VFP: %g = root(%g)\n",
- sqrtf (VFP_fval (srcM)), VFP_fval (srcM));
-
- VFP_fval (dest) = sqrtf (VFP_fval (srcM));
- }
- }
- return;
-
- case 0x4:
- case 0x5:
- /* VCMP, VCMPE */
- if (BIT(8))
- {
- ARMdval res = VFP_dval (dest);
-
- if (BIT (16) == 0)
- {
- ARMdval src = VFP_dval (srcM);
-
- if (isinf (res) && isinf (src))
- {
- if (res > 0.0 && src > 0.0)
- res = 0.0;
- else if (res < 0.0 && src < 0.0)
- res = 0.0;
- /* else leave res alone. */
- }
- else
- res -= src;
- }
-
- /* FIXME: Add handling of signalling NaNs and the E bit. */
-
- state->FPSCR &= 0x0FFFFFFF;
- if (res < 0.0)
- state->FPSCR |= NBIT;
- else
- state->FPSCR |= CBIT;
- if (res == 0.0)
- state->FPSCR |= ZBIT;
- if (isnan (res))
- state->FPSCR |= VBIT;
-
- if (trace)
- fprintf (stderr, " VFP: VCMP (64bit) %g vs %g res %g, flags: %c%c%c%c\n",
- VFP_dval (dest), BIT (16) ? 0.0 : VFP_dval (srcM), res,
- state->FPSCR & NBIT ? 'N' : '-',
- state->FPSCR & ZBIT ? 'Z' : '-',
- state->FPSCR & CBIT ? 'C' : '-',
- state->FPSCR & VBIT ? 'V' : '-');
- }
- else
- {
- ARMfval res = VFP_fval (dest);
-
- if (BIT (16) == 0)
- {
- ARMfval src = VFP_fval (srcM);
-
- if (isinf (res) && isinf (src))
- {
- if (res > 0.0 && src > 0.0)
- res = 0.0;
- else if (res < 0.0 && src < 0.0)
- res = 0.0;
- /* else leave res alone. */
- }
- else
- res -= src;
- }
-
- /* FIXME: Add handling of signalling NaNs and the E bit. */
-
- state->FPSCR &= 0x0FFFFFFF;
- if (res < 0.0)
- state->FPSCR |= NBIT;
- else
- state->FPSCR |= CBIT;
- if (res == 0.0)
- state->FPSCR |= ZBIT;
- if (isnan (res))
- state->FPSCR |= VBIT;
-
- if (trace)
- fprintf (stderr, " VFP: VCMP (32bit) %g vs %g res %g, flags: %c%c%c%c\n",
- VFP_fval (dest), BIT (16) ? 0.0 : VFP_fval (srcM), res,
- state->FPSCR & NBIT ? 'N' : '-',
- state->FPSCR & ZBIT ? 'Z' : '-',
- state->FPSCR & CBIT ? 'C' : '-',
- state->FPSCR & VBIT ? 'V' : '-');
- }
- return;
-
- case 0x7:
- if (BIT (8))
- {
- dest = (DESTReg << 1) + BIT (22);
- VFP_fval (dest) = VFP_dval (srcM);
- }
- else
- {
- dest = DESTReg + (BIT (22) << 4);
- VFP_dval (dest) = VFP_fval (srcM);
- }
- return;
-
- case 0x8:
- case 0xC:
- case 0xD:
- /* VCVT integer <-> FP */
- if (BIT (18))
- {
- /* To integer. */
- if (BIT (8))
- {
- dest = (BITS(12,15) << 1) + BIT (22);
- if (BIT (16))
- VFP_sword (dest) = VFP_dval (srcM);
- else
- VFP_uword (dest) = VFP_dval (srcM);
- }
- else
- {
- if (BIT (16))
- VFP_sword (dest) = VFP_fval (srcM);
- else
- VFP_uword (dest) = VFP_fval (srcM);
- }
- }
- else
- {
- /* From integer. */
- if (BIT (8))
- {
- srcM = (BITS (0,3) << 1) + BIT (5);
- if (BIT (7))
- VFP_dval (dest) = VFP_sword (srcM);
- else
- VFP_dval (dest) = VFP_uword (srcM);
- }
- else
- {
- if (BIT (7))
- VFP_fval (dest) = VFP_sword (srcM);
- else
- VFP_fval (dest) = VFP_uword (srcM);
- }
- }
- return;
- }
-
- fprintf (stderr, "SIM: VFP: Unimplemented: Float op3: %03x\n", BITS (16,27));
- return;
- }
-
- fprintf (stderr, "SIM: VFP: Unimplemented: Float op2: %02x\n", BITS (20, 27));
- return;
-}
-
-/* This function does the Busy-Waiting for an CDP instruction. */
-
-void
-ARMul_CDP (ARMul_State * state, ARMword instr)
-{
- unsigned cpab;
-
- if (CPNum == 10 || CPNum == 11)
- {
- handle_VFP_op (state, instr);
- return;
- }
-
- if (! CP_ACCESS_ALLOWED (state, CPNum))
- {
- ARMul_UndefInstr (state, instr);
- return;
- }
-
- cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr);
- while (cpab == ARMul_BUSY)
- {
- ARMul_Icycles (state, 1, 0);
- if (IntPending (state))
- {
- cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT, instr);
- return;
- }
- else
- cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr);
- }
- if (cpab == ARMul_CANT)
- ARMul_Abort (state, ARMul_UndefinedInstrV);
- else
- BUSUSEDN;
-}
-
-/* This function handles Undefined instructions, as CP isntruction. */
-
-void
-ARMul_UndefInstr (ARMul_State * state, ARMword instr ATTRIBUTE_UNUSED)
-{
- ARMul_Abort (state, ARMul_UndefinedInstrV);
-}
-
-/* Return TRUE if an interrupt is pending, FALSE otherwise. */
-
-unsigned
-IntPending (ARMul_State * state)
-{
- if (state->Exception)
- {
- /* Any exceptions. */
- if (state->NresetSig == LOW)
- {
- ARMul_Abort (state, ARMul_ResetV);
- return TRUE;
- }
- else if (!state->NfiqSig && !FFLAG)
- {
- ARMul_Abort (state, ARMul_FIQV);
- return TRUE;
- }
- else if (!state->NirqSig && !IFLAG)
- {
- ARMul_Abort (state, ARMul_IRQV);
- return TRUE;
- }
- }
-
- return FALSE;
-}
-
-/* Align a word access to a non word boundary. */
-
-ARMword
-ARMul_Align (ARMul_State *state ATTRIBUTE_UNUSED, ARMword address, ARMword data)
-{
- /* This code assumes the address is really unaligned,
- as a shift by 32 is undefined in C. */
-
- address = (address & 3) << 3; /* Get the word address. */
- return ((data >> address) | (data << (32 - address))); /* rot right */
-}
-
-/* This routine is used to call another routine after a certain number of
- cycles have been executed. The first parameter is the number of cycles
- delay before the function is called, the second argument is a pointer
- to the function. A delay of zero doesn't work, just call the function. */
-
-void
-ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
- unsigned (*what) (ARMul_State *))
-{
- unsigned long when;
- struct EventNode *event;
-
- if (state->EventSet++ == 0)
- state->Now = ARMul_Time (state);
- when = (state->Now + delay) % EVENTLISTSIZE;
- event = (struct EventNode *) malloc (sizeof (struct EventNode));
- event->func = what;
- event->next = *(state->EventPtr + when);
- *(state->EventPtr + when) = event;
-}
-
-/* This routine is called at the beginning of
- every cycle, to envoke scheduled events. */
-
-void
-ARMul_EnvokeEvent (ARMul_State * state)
-{
- static unsigned long then;
-
- then = state->Now;
- state->Now = ARMul_Time (state) % EVENTLISTSIZE;
- if (then < state->Now)
- /* Schedule events. */
- EnvokeList (state, then, state->Now);
- else if (then > state->Now)
- {
- /* Need to wrap around the list. */
- EnvokeList (state, then, EVENTLISTSIZE - 1L);
- EnvokeList (state, 0L, state->Now);
- }
-}
-
-/* Envokes all the entries in a range. */
-
-static void
-EnvokeList (ARMul_State * state, unsigned long from, unsigned long to)
-{
- for (; from <= to; from++)
- {
- struct EventNode *anevent;
-
- anevent = *(state->EventPtr + from);
- while (anevent)
- {
- (anevent->func) (state);
- state->EventSet--;
- anevent = anevent->next;
- }
- *(state->EventPtr + from) = NULL;
- }
-}
-
-/* This routine is returns the number of clock ticks since the last reset. */
-
-unsigned long
-ARMul_Time (ARMul_State * state)
-{
- return (state->NumScycles + state->NumNcycles +
- state->NumIcycles + state->NumCcycles + state->NumFcycles);
-}
+++ /dev/null
-/* armvirt.c -- ARMulator virtual memory interace: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* This file contains a complete ARMulator memory model, modelling a
- "virtual memory" system. A much simpler model can be found in armfast.c,
- and that model goes faster too, but has a fixed amount of memory. This
- model's memory has 64K pages, allocated on demand from a 64K entry page
- table. The routines PutWord and GetWord implement this. Pages are never
- freed as they might be needed again. A single area of memory may be
- defined to generate aborts. */
-
-/* This must come before any other includes. */
-#include "defs.h"
-
-#include "armos.h"
-#include "armdefs.h"
-#include "ansidecl.h"
-
-#ifdef VALIDATE /* for running the validate suite */
-#define TUBE 48 * 1024 * 1024 /* write a char on the screen */
-#define ABORTS 1
-#endif
-
-/* #define ABORTS */
-
-#ifdef ABORTS /* the memory system will abort */
-/* For the old test suite Abort between 32 Kbytes and 32 Mbytes
- For the new test suite Abort between 8 Mbytes and 26 Mbytes */
-/* #define LOWABORT 32 * 1024
-#define HIGHABORT 32 * 1024 * 1024 */
-#define LOWABORT 8 * 1024 * 1024
-#define HIGHABORT 26 * 1024 * 1024
-
-#endif
-
-#undef PAGESIZE /* Cleanup system headers. */
-#define NUMPAGES 64 * 1024
-#define PAGESIZE 64 * 1024
-#define PAGEBITS 16
-#define OFFSETBITS 0xffff
-
-int SWI_vector_installed = FALSE;
-
-/***************************************************************************\
-* Get a Word from Virtual Memory, maybe allocating the page *
-\***************************************************************************/
-
-static ARMword
-GetWord (ARMul_State * state, ARMword address, int check)
-{
- ARMword page;
- ARMword offset;
- ARMword **pagetable;
- ARMword *pageptr;
-
- if (check && state->is_XScale)
- XScale_check_memacc (state, &address, 0);
-
- page = address >> PAGEBITS;
- offset = (address & OFFSETBITS) >> 2;
- pagetable = (ARMword **) state->MemDataPtr;
- pageptr = *(pagetable + page);
-
- if (pageptr == NULL)
- {
- pageptr = (ARMword *) malloc (PAGESIZE);
-
- if (pageptr == NULL)
- {
- perror ("ARMulator can't allocate VM page");
- exit (12);
- }
-
- *(pagetable + page) = pageptr;
- }
-
- return *(pageptr + offset);
-}
-
-/***************************************************************************\
-* Put a Word into Virtual Memory, maybe allocating the page *
-\***************************************************************************/
-
-static void
-PutWord (ARMul_State * state, ARMword address, ARMword data, int check)
-{
- ARMword page;
- ARMword offset;
- ARMword **pagetable;
- ARMword *pageptr;
-
- if (check && state->is_XScale)
- XScale_check_memacc (state, &address, 1);
-
- page = address >> PAGEBITS;
- offset = (address & OFFSETBITS) >> 2;
- pagetable = (ARMword **) state->MemDataPtr;
- pageptr = *(pagetable + page);
-
- if (pageptr == NULL)
- {
- pageptr = (ARMword *) malloc (PAGESIZE);
- if (pageptr == NULL)
- {
- perror ("ARMulator can't allocate VM page");
- exit (13);
- }
-
- *(pagetable + page) = pageptr;
- }
-
- if (address == 0x8)
- SWI_vector_installed = TRUE;
-
- *(pageptr + offset) = data;
-}
-
-/***************************************************************************\
-* Initialise the memory interface *
-\***************************************************************************/
-
-unsigned
-ARMul_MemoryInit (ARMul_State * state, unsigned long initmemsize)
-{
- ARMword **pagetable;
- unsigned page;
-
- if (initmemsize)
- state->MemSize = initmemsize;
-
- pagetable = (ARMword **) malloc (sizeof (ARMword *) * NUMPAGES);
-
- if (pagetable == NULL)
- return FALSE;
-
- for (page = 0; page < NUMPAGES; page++)
- *(pagetable + page) = NULL;
-
- state->MemDataPtr = (unsigned char *) pagetable;
-
- ARMul_ConsolePrint (state, ", 4 Gb memory");
-
- return TRUE;
-}
-
-/***************************************************************************\
-* Remove the memory interface *
-\***************************************************************************/
-
-void
-ARMul_MemoryExit (ARMul_State * state)
-{
- ARMword page;
- ARMword **pagetable;
- ARMword *pageptr;
-
- pagetable = (ARMword **) state->MemDataPtr;
- for (page = 0; page < NUMPAGES; page++)
- {
- pageptr = *(pagetable + page);
- if (pageptr != NULL)
- free ((char *) pageptr);
- }
- free ((char *) pagetable);
- return;
-}
-
-/***************************************************************************\
-* ReLoad Instruction *
-\***************************************************************************/
-
-ARMword
-ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize)
-{
-#ifdef ABORTS
- if (address >= LOWABORT && address < HIGHABORT)
- {
- ARMul_PREFETCHABORT (address);
- return ARMul_ABORTWORD;
- }
- else
- {
- ARMul_CLEARABORT;
- }
-#endif
-
- if ((isize == 2) && (address & 0x2))
- {
- /* We return the next two halfwords: */
- ARMword lo = GetWord (state, address, FALSE);
- ARMword hi = GetWord (state, address + 4, FALSE);
-
- if (state->bigendSig == HIGH)
- return (lo << 16) | (hi >> 16);
- else
- return ((hi & 0xFFFF) << 16) | (lo >> 16);
- }
-
- return GetWord (state, address, TRUE);
-}
-
-/***************************************************************************\
-* Load Instruction, Sequential Cycle *
-\***************************************************************************/
-
-ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize)
-{
- state->NumScycles++;
-
- return ARMul_ReLoadInstr (state, address, isize);
-}
-
-/***************************************************************************\
-* Load Instruction, Non Sequential Cycle *
-\***************************************************************************/
-
-ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize)
-{
- state->NumNcycles++;
-
- return ARMul_ReLoadInstr (state, address, isize);
-}
-
-/***************************************************************************\
-* Read Word (but don't tell anyone!) *
-\***************************************************************************/
-
-ARMword ARMul_ReadWord (ARMul_State * state, ARMword address)
-{
-#ifdef ABORTS
- if (address >= LOWABORT && address < HIGHABORT)
- {
- ARMul_DATAABORT (address);
- return ARMul_ABORTWORD;
- }
- else
- {
- ARMul_CLEARABORT;
- }
-#endif
-
- return GetWord (state, address, TRUE);
-}
-
-/***************************************************************************\
-* Load Word, Sequential Cycle *
-\***************************************************************************/
-
-ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address)
-{
- state->NumScycles++;
-
- return ARMul_ReadWord (state, address);
-}
-
-/***************************************************************************\
-* Load Word, Non Sequential Cycle *
-\***************************************************************************/
-
-ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address)
-{
- state->NumNcycles++;
-
- return ARMul_ReadWord (state, address);
-}
-
-/***************************************************************************\
-* Load Halfword, (Non Sequential Cycle) *
-\***************************************************************************/
-
-ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
-{
- ARMword temp, offset;
-
- state->NumNcycles++;
-
- temp = ARMul_ReadWord (state, address);
- offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
-
- return (temp >> offset) & 0xffff;
-}
-
-/***************************************************************************\
-* Read Byte (but don't tell anyone!) *
-\***************************************************************************/
-
-ARMword ARMul_ReadByte (ARMul_State * state, ARMword address)
-{
- ARMword temp, offset;
-
- temp = ARMul_ReadWord (state, address);
- offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
-
- return (temp >> offset & 0xffL);
-}
-
-/***************************************************************************\
-* Load Byte, (Non Sequential Cycle) *
-\***************************************************************************/
-
-ARMword ARMul_LoadByte (ARMul_State * state, ARMword address)
-{
- state->NumNcycles++;
-
- return ARMul_ReadByte (state, address);
-}
-
-/***************************************************************************\
-* Write Word (but don't tell anyone!) *
-\***************************************************************************/
-
-void
-ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data)
-{
-#ifdef ABORTS
- if (address >= LOWABORT && address < HIGHABORT)
- {
- ARMul_DATAABORT (address);
- return;
- }
- else
- {
- ARMul_CLEARABORT;
- }
-#endif
-
- PutWord (state, address, data, TRUE);
-}
-
-/***************************************************************************\
-* Store Word, Sequential Cycle *
-\***************************************************************************/
-
-void
-ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data)
-{
- state->NumScycles++;
-
- ARMul_WriteWord (state, address, data);
-}
-
-/***************************************************************************\
-* Store Word, Non Sequential Cycle *
-\***************************************************************************/
-
-void
-ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data)
-{
- state->NumNcycles++;
-
- ARMul_WriteWord (state, address, data);
-}
-
-/***************************************************************************\
-* Store HalfWord, (Non Sequential Cycle) *
-\***************************************************************************/
-
-void
-ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data)
-{
- ARMword temp, offset;
-
- state->NumNcycles++;
-
-#ifdef VALIDATE
- if (address == TUBE)
- {
- if (data == 4)
- state->Emulate = FALSE;
- else
- (void) putc ((char) data, stderr); /* Write Char */
- return;
- }
-#endif
-
- temp = ARMul_ReadWord (state, address);
- offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
-
- PutWord (state, address,
- (temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset),
- TRUE);
-}
-
-/***************************************************************************\
-* Write Byte (but don't tell anyone!) *
-\***************************************************************************/
-
-void
-ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data)
-{
- ARMword temp, offset;
-
- temp = ARMul_ReadWord (state, address);
- offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
-
- PutWord (state, address,
- (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset),
- TRUE);
-}
-
-/***************************************************************************\
-* Store Byte, (Non Sequential Cycle) *
-\***************************************************************************/
-
-void
-ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data)
-{
- state->NumNcycles++;
-
-#ifdef VALIDATE
- if (address == TUBE)
- {
- if (data == 4)
- state->Emulate = FALSE;
- else
- (void) putc ((char) data, stderr); /* Write Char */
- return;
- }
-#endif
-
- ARMul_WriteByte (state, address, data);
-}
-
-/***************************************************************************\
-* Swap Word, (Two Non Sequential Cycles) *
-\***************************************************************************/
-
-ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data)
-{
- ARMword temp;
-
- state->NumNcycles++;
-
- temp = ARMul_ReadWord (state, address);
-
- state->NumNcycles++;
-
- PutWord (state, address, data, TRUE);
-
- return temp;
-}
-
-/***************************************************************************\
-* Swap Byte, (Two Non Sequential Cycles) *
-\***************************************************************************/
-
-ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data)
-{
- ARMword temp;
-
- temp = ARMul_LoadByte (state, address);
- ARMul_StoreByte (state, address, data);
-
- return temp;
-}
-
-/***************************************************************************\
-* Count I Cycles *
-\***************************************************************************/
-
-void
-ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
-{
- state->NumIcycles += number;
- ARMul_CLEARABORT;
-}
-
-/***************************************************************************\
-* Count C Cycles *
-\***************************************************************************/
-
-void
-ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
-{
- state->NumCcycles += number;
- ARMul_CLEARABORT;
-}
-
-
-/* Read a byte. Do not check for alignment or access errors. */
-
-ARMword
-ARMul_SafeReadByte (ARMul_State * state, ARMword address)
-{
- ARMword temp, offset;
-
- temp = GetWord (state, address, FALSE);
- offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;
-
- return (temp >> offset & 0xffL);
-}
-
-void
-ARMul_SafeWriteByte (ARMul_State * state, ARMword address, ARMword data)
-{
- ARMword temp, offset;
-
- temp = GetWord (state, address, FALSE);
- offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;
-
- PutWord (state, address,
- (temp & ~(0xffL << offset)) | ((data & 0xffL) << offset),
- FALSE);
-}
+++ /dev/null
-/* dbg_rdi.h -- ARMulator RDI interface: ARM6 Instruction Emulator.
- Copyright (C) 1994 Advanced RISC Machines Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-#ifndef dbg_rdi__h
-#define dbg_rdi__h
-
-/***************************************************************************\
-* Error Codes *
-\***************************************************************************/
-
-#define RDIError_NoError 0
-
-#define RDIError_Reset 1
-#define RDIError_UndefinedInstruction 2
-#define RDIError_SoftwareInterrupt 3
-#define RDIError_PrefetchAbort 4
-#define RDIError_DataAbort 5
-#define RDIError_AddressException 6
-#define RDIError_IRQ 7
-#define RDIError_FIQ 8
-#define RDIError_Error 9
-#define RDIError_BranchThrough0 10
-
-#define RDIError_NotInitialised 128
-#define RDIError_UnableToInitialise 129
-#define RDIError_WrongByteSex 130
-#define RDIError_UnableToTerminate 131
-#define RDIError_BadInstruction 132
-#define RDIError_IllegalInstruction 133
-#define RDIError_BadCPUStateSetting 134
-#define RDIError_UnknownCoPro 135
-#define RDIError_UnknownCoProState 136
-#define RDIError_BadCoProState 137
-#define RDIError_BadPointType 138
-#define RDIError_UnimplementedType 139
-#define RDIError_BadPointSize 140
-#define RDIError_UnimplementedSize 141
-#define RDIError_NoMorePoints 142
-#define RDIError_BreakpointReached 143
-#define RDIError_WatchpointAccessed 144
-#define RDIError_NoSuchPoint 145
-#define RDIError_ProgramFinishedInStep 146
-#define RDIError_UserInterrupt 147
-#define RDIError_CantSetPoint 148
-#define RDIError_IncompatibleRDILevels 149
-
-#define RDIError_CantLoadConfig 150
-#define RDIError_BadConfigData 151
-#define RDIError_NoSuchConfig 152
-#define RDIError_BufferFull 153
-#define RDIError_OutOfStore 154
-#define RDIError_NotInDownload 155
-#define RDIError_PointInUse 156
-#define RDIError_BadImageFormat 157
-#define RDIError_TargetRunning 158
-
-#define RDIError_LittleEndian 240
-#define RDIError_BigEndian 241
-#define RDIError_SoftInitialiseError 242
-
-#define RDIError_InsufficientPrivilege 253
-#define RDIError_UnimplementedMessage 254
-#define RDIError_UndefinedMessage 255
-
-#endif
-
-extern unsigned int swi_mask;
-
-#define SWI_MASK_DEMON (1 << 0)
-#define SWI_MASK_ANGEL (1 << 1)
-#define SWI_MASK_REDBOOT (1 << 2)
+++ /dev/null
-/* iwmmxt.c -- Intel(r) Wireless MMX(tm) technology co-processor interface.
- Copyright (C) 2002-2024 Free Software Foundation, Inc.
- Contributed by matthew green (mrg@redhat.com).
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-/* This must come before any other includes. */
-#include "defs.h"
-
-#include <stdlib.h>
-#include <string.h>
-
-#include "armdefs.h"
-#include "armos.h"
-#include "armemu.h"
-#include "ansidecl.h"
-#include "iwmmxt.h"
-
-/* #define DEBUG 1 */
-
-/* Intel(r) Wireless MMX(tm) technology co-processor.
- It uses co-processor numbers (0 and 1). There are 16 vector registers wRx
- and 16 control registers wCx. Co-processors 0 and 1 are used in MCR/MRC
- to access wRx and wCx respectively. */
-
-static ARMdword wR[16];
-static ARMword wC[16] = { 0x69051010 };
-
-#define SUBSTR(w,t,m,n) ((t)(w << ((sizeof (t) * 8 - 1) - (n))) \
- >> (((sizeof (t) * 8 - 1) - (n)) + (m)))
-#define wCBITS(w,x,y) SUBSTR (wC[w], ARMword, x, y)
-#define wRBITS(w,x,y) SUBSTR (wR[w], ARMdword, x, y)
-#define wCID 0
-#define wCon 1
-#define wCSSF 2
-#define wCASF 3
-#define wCGR0 8
-#define wCGR1 9
-#define wCGR2 10
-#define wCGR3 11
-
-/* Bits in the wCon register. */
-#define WCON_CUP (1 << 0)
-#define WCON_MUP (1 << 1)
-
-/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */
-#define SIMD8_SET(x, v, n, b) (x) |= ((v != 0) << ((((b) + 1) * 4) + (n)))
-#define SIMD16_SET(x, v, n, h) (x) |= ((v != 0) << ((((h) + 1) * 8) + (n)))
-#define SIMD32_SET(x, v, n, w) (x) |= ((v != 0) << ((((w) + 1) * 16) + (n)))
-#define SIMD64_SET(x, v, n) (x) |= ((v != 0) << (32 + (n)))
-
-/* Flags to pass as "n" above. */
-#define SIMD_NBIT -1
-#define SIMD_ZBIT -2
-#define SIMD_CBIT -3
-#define SIMD_VBIT -4
-
-/* Various status bit macros. */
-#define NBIT8(x) ((x) & 0x80)
-#define NBIT16(x) ((x) & 0x8000)
-#define NBIT32(x) ((x) & 0x80000000)
-#define NBIT64(x) ((x) & 0x8000000000000000ULL)
-#define ZBIT8(x) (((x) & 0xff) == 0)
-#define ZBIT16(x) (((x) & 0xffff) == 0)
-#define ZBIT32(x) (((x) & 0xffffffff) == 0)
-#define ZBIT64(x) (x == 0)
-
-/* Access byte/half/word "n" of register "x". */
-#define wRBYTE(x,n) wRBITS ((x), (n) * 8, (n) * 8 + 7)
-#define wRHALF(x,n) wRBITS ((x), (n) * 16, (n) * 16 + 15)
-#define wRWORD(x,n) wRBITS ((x), (n) * 32, (n) * 32 + 31)
-
-/* Macro to handle how the G bit selects wCGR registers. */
-#define DECODE_G_BIT(state, instr, shift) \
-{ \
- unsigned int reg; \
- \
- reg = BITS (0, 3); \
- \
- if (BIT (8)) /* G */ \
- { \
- if (reg < wCGR0 || reg > wCGR3) \
- { \
- ARMul_UndefInstr (state, instr); \
- return ARMul_DONE; \
- } \
- shift = wC [reg]; \
- } \
- else \
- shift = wR [reg]; \
- \
- shift &= 0xff; \
-}
-
-/* Index calculations for the satrv[] array. */
-#define BITIDX8(x) (x)
-#define BITIDX16(x) (((x) + 1) * 2 - 1)
-#define BITIDX32(x) (((x) + 1) * 4 - 1)
-
-/* Sign extension macros. */
-#define EXTEND8(a) ((a) & 0x80 ? ((a) | 0xffffff00) : (a))
-#define EXTEND16(a) ((a) & 0x8000 ? ((a) | 0xffff0000) : (a))
-#define EXTEND32(a) ((a) & 0x80000000ULL ? ((a) | 0xffffffff00000000ULL) : (a))
-
-/* Set the wCSSF from 8 values. */
-#define SET_wCSSF(a,b,c,d,e,f,g,h) \
- wC[wCSSF] = (((h) != 0) << 7) | (((g) != 0) << 6) \
- | (((f) != 0) << 5) | (((e) != 0) << 4) \
- | (((d) != 0) << 3) | (((c) != 0) << 2) \
- | (((b) != 0) << 1) | (((a) != 0) << 0);
-
-/* Set the wCSSR from an array with 8 values. */
-#define SET_wCSSFvec(v) \
- SET_wCSSF((v)[0],(v)[1],(v)[2],(v)[3],(v)[4],(v)[5],(v)[6],(v)[7])
-
-/* Size qualifiers for vector operations. */
-#define Bqual 0
-#define Hqual 1
-#define Wqual 2
-#define Dqual 3
-
-/* Saturation qualifiers for vector operations. */
-#define NoSaturation 0
-#define UnsignedSaturation 1
-#define SignedSaturation 3
-
-\f
-/* Prototypes. */
-static ARMword Add32 (ARMword, ARMword, int *, int *, ARMword);
-static ARMdword AddS32 (ARMdword, ARMdword, int *, int *);
-static ARMdword AddU32 (ARMdword, ARMdword, int *, int *);
-static ARMword AddS16 (ARMword, ARMword, int *, int *);
-static ARMword AddU16 (ARMword, ARMword, int *, int *);
-static ARMword AddS8 (ARMword, ARMword, int *, int *);
-static ARMword AddU8 (ARMword, ARMword, int *, int *);
-static ARMword Sub32 (ARMword, ARMword, int *, int *, ARMword);
-static ARMdword SubS32 (ARMdword, ARMdword, int *, int *);
-static ARMdword SubU32 (ARMdword, ARMdword, int *, int *);
-static ARMword SubS16 (ARMword, ARMword, int *, int *);
-static ARMword SubS8 (ARMword, ARMword, int *, int *);
-static ARMword SubU16 (ARMword, ARMword, int *, int *);
-static ARMword SubU8 (ARMword, ARMword, int *, int *);
-static unsigned char IwmmxtSaturateU8 (signed short, int *);
-static signed char IwmmxtSaturateS8 (signed short, int *);
-static unsigned short IwmmxtSaturateU16 (signed int, int *);
-static signed short IwmmxtSaturateS16 (signed int, int *);
-static unsigned long IwmmxtSaturateU32 (signed long long, int *);
-static signed long IwmmxtSaturateS32 (signed long long, int *);
-static ARMword Compute_Iwmmxt_Address (ARMul_State *, ARMword, int *);
-static ARMdword Iwmmxt_Load_Double_Word (ARMul_State *, ARMword);
-static ARMword Iwmmxt_Load_Word (ARMul_State *, ARMword);
-static ARMword Iwmmxt_Load_Half_Word (ARMul_State *, ARMword);
-static ARMword Iwmmxt_Load_Byte (ARMul_State *, ARMword);
-static void Iwmmxt_Store_Double_Word (ARMul_State *, ARMword, ARMdword);
-static void Iwmmxt_Store_Word (ARMul_State *, ARMword, ARMword);
-static void Iwmmxt_Store_Half_Word (ARMul_State *, ARMword, ARMword);
-static void Iwmmxt_Store_Byte (ARMul_State *, ARMword, ARMword);
-static int Process_Instruction (ARMul_State *, ARMword);
-
-static int TANDC (ARMul_State *, ARMword);
-static int TBCST (ARMul_State *, ARMword);
-static int TEXTRC (ARMul_State *, ARMword);
-static int TEXTRM (ARMul_State *, ARMword);
-static int TINSR (ARMul_State *, ARMword);
-static int TMCR (ARMul_State *, ARMword);
-static int TMCRR (ARMul_State *, ARMword);
-static int TMIA (ARMul_State *, ARMword);
-static int TMIAPH (ARMul_State *, ARMword);
-static int TMIAxy (ARMul_State *, ARMword);
-static int TMOVMSK (ARMul_State *, ARMword);
-static int TMRC (ARMul_State *, ARMword);
-static int TMRRC (ARMul_State *, ARMword);
-static int TORC (ARMul_State *, ARMword);
-static int WACC (ARMul_State *, ARMword);
-static int WADD (ARMul_State *, ARMword);
-static int WALIGNI (ARMword);
-static int WALIGNR (ARMul_State *, ARMword);
-static int WAND (ARMword);
-static int WANDN (ARMword);
-static int WAVG2 (ARMword);
-static int WCMPEQ (ARMul_State *, ARMword);
-static int WCMPGT (ARMul_State *, ARMword);
-static int WLDR (ARMul_State *, ARMword);
-static int WMAC (ARMword);
-static int WMADD (ARMword);
-static int WMAX (ARMul_State *, ARMword);
-static int WMIN (ARMul_State *, ARMword);
-static int WMUL (ARMword);
-static int WOR (ARMword);
-static int WPACK (ARMul_State *, ARMword);
-static int WROR (ARMul_State *, ARMword);
-static int WSAD (ARMword);
-static int WSHUFH (ARMword);
-static int WSLL (ARMul_State *, ARMword);
-static int WSRA (ARMul_State *, ARMword);
-static int WSRL (ARMul_State *, ARMword);
-static int WSTR (ARMul_State *, ARMword);
-static int WSUB (ARMul_State *, ARMword);
-static int WUNPCKEH (ARMul_State *, ARMword);
-static int WUNPCKEL (ARMul_State *, ARMword);
-static int WUNPCKIH (ARMul_State *, ARMword);
-static int WUNPCKIL (ARMul_State *, ARMword);
-static int WXOR (ARMword);
-\f
-/* This function does the work of adding two 32bit values
- together, and calculating if a carry has occurred. */
-
-static ARMword
-Add32 (ARMword a1,
- ARMword a2,
- int * carry_ptr,
- int * overflow_ptr,
- ARMword sign_mask)
-{
- ARMword result = (a1 + a2);
- unsigned int uresult = (unsigned int) result;
- unsigned int ua1 = (unsigned int) a1;
-
- /* If (result == a1) and (a2 == 0),
- or (result > a2) then we have no carry. */
- * carry_ptr = ((uresult == ua1) ? (a2 != 0) : (uresult < ua1));
-
- /* Overflow occurs when both arguments are the
- same sign, but the result is a different sign. */
- * overflow_ptr = ( ( (result & sign_mask) && !(a1 & sign_mask) && !(a2 & sign_mask))
- || (!(result & sign_mask) && (a1 & sign_mask) && (a2 & sign_mask)));
-
- return result;
-}
-
-static ARMdword
-AddS32 (ARMdword a1, ARMdword a2, int * carry_ptr, int * overflow_ptr)
-{
- ARMdword result;
- unsigned int uresult;
- unsigned int ua1;
-
- a1 = EXTEND32 (a1);
- a2 = EXTEND32 (a2);
-
- result = a1 + a2;
- uresult = (unsigned int) result;
- ua1 = (unsigned int) a1;
-
- * carry_ptr = ((uresult == a1) ? (a2 != 0) : (uresult < ua1));
-
- * overflow_ptr = ( ( (result & 0x80000000ULL) && !(a1 & 0x80000000ULL) && !(a2 & 0x80000000ULL))
- || (!(result & 0x80000000ULL) && (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL)));
-
- return result;
-}
-
-static ARMdword
-AddU32 (ARMdword a1, ARMdword a2, int * carry_ptr, int * overflow_ptr)
-{
- ARMdword result;
- unsigned int uresult;
- unsigned int ua1;
-
- a1 &= 0xffffffff;
- a2 &= 0xffffffff;
-
- result = a1 + a2;
- uresult = (unsigned int) result;
- ua1 = (unsigned int) a1;
-
- * carry_ptr = ((uresult == a1) ? (a2 != 0) : (uresult < ua1));
-
- * overflow_ptr = ( ( (result & 0x80000000ULL) && !(a1 & 0x80000000ULL) && !(a2 & 0x80000000ULL))
- || (!(result & 0x80000000ULL) && (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL)));
-
- return result;
-}
-
-static ARMword
-AddS16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
-{
- a1 = EXTEND16 (a1);
- a2 = EXTEND16 (a2);
-
- return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
-}
-
-static ARMword
-AddU16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
-{
- a1 &= 0xffff;
- a2 &= 0xffff;
-
- return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
-}
-
-static ARMword
-AddS8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
-{
- a1 = EXTEND8 (a1);
- a2 = EXTEND8 (a2);
-
- return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
-}
-
-static ARMword
-AddU8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
-{
- a1 &= 0xff;
- a2 &= 0xff;
-
- return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
-}
-
-static ARMword
-Sub32 (ARMword a1,
- ARMword a2,
- int * borrow_ptr,
- int * overflow_ptr,
- ARMword sign_mask)
-{
- ARMword result = (a1 - a2);
- unsigned int ua1 = (unsigned int) a1;
- unsigned int ua2 = (unsigned int) a2;
-
- /* A borrow occurs if a2 is (unsigned) larger than a1.
- However the carry flag is *cleared* if a borrow occurs. */
- * borrow_ptr = ! (ua2 > ua1);
-
- /* Overflow occurs when a negative number is subtracted from a
- positive number and the result is negative or a positive
- number is subtracted from a negative number and the result is
- positive. */
- * overflow_ptr = ( (! (a1 & sign_mask) && (a2 & sign_mask) && (result & sign_mask))
- || ((a1 & sign_mask) && ! (a2 & sign_mask) && ! (result & sign_mask)));
-
- return result;
-}
-
-static ARMdword
-SubS32 (ARMdword a1, ARMdword a2, int * borrow_ptr, int * overflow_ptr)
-{
- ARMdword result;
- unsigned int ua1;
- unsigned int ua2;
-
- a1 = EXTEND32 (a1);
- a2 = EXTEND32 (a2);
-
- result = a1 - a2;
- ua1 = (unsigned int) a1;
- ua2 = (unsigned int) a2;
-
- * borrow_ptr = ! (ua2 > ua1);
-
- * overflow_ptr = ( (! (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL) && (result & 0x80000000ULL))
- || ((a1 & 0x80000000ULL) && ! (a2 & 0x80000000ULL) && ! (result & 0x80000000ULL)));
-
- return result;
-}
-
-static ARMword
-SubS16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
-{
- a1 = EXTEND16 (a1);
- a2 = EXTEND16 (a2);
-
- return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
-}
-
-static ARMword
-SubS8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
-{
- a1 = EXTEND8 (a1);
- a2 = EXTEND8 (a2);
-
- return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
-}
-
-static ARMword
-SubU16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
-{
- a1 &= 0xffff;
- a2 &= 0xffff;
-
- return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
-}
-
-static ARMword
-SubU8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
-{
- a1 &= 0xff;
- a2 &= 0xff;
-
- return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
-}
-
-static ARMdword
-SubU32 (ARMdword a1, ARMdword a2, int * borrow_ptr, int * overflow_ptr)
-{
- ARMdword result;
- unsigned int ua1;
- unsigned int ua2;
-
- a1 &= 0xffffffff;
- a2 &= 0xffffffff;
-
- result = a1 - a2;
- ua1 = (unsigned int) a1;
- ua2 = (unsigned int) a2;
-
- * borrow_ptr = ! (ua2 > ua1);
-
- * overflow_ptr = ( (! (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL) && (result & 0x80000000ULL))
- || ((a1 & 0x80000000ULL) && ! (a2 & 0x80000000ULL) && ! (result & 0x80000000ULL)));
-
- return result;
-}
-
-/* For the saturation. */
-
-static unsigned char
-IwmmxtSaturateU8 (signed short val, int * sat)
-{
- unsigned char rv;
-
- if (val < 0)
- {
- rv = 0;
- *sat = 1;
- }
- else if (val > 0xff)
- {
- rv = 0xff;
- *sat = 1;
- }
- else
- {
- rv = val & 0xff;
- *sat = 0;
- }
- return rv;
-}
-
-static signed char
-IwmmxtSaturateS8 (signed short val, int * sat)
-{
- signed char rv;
-
- if (val < -0x80)
- {
- rv = -0x80;
- *sat = 1;
- }
- else if (val > 0x7f)
- {
- rv = 0x7f;
- *sat = 1;
- }
- else
- {
- rv = val & 0xff;
- *sat = 0;
- }
- return rv;
-}
-
-static unsigned short
-IwmmxtSaturateU16 (signed int val, int * sat)
-{
- unsigned short rv;
-
- if (val < 0)
- {
- rv = 0;
- *sat = 1;
- }
- else if (val > 0xffff)
- {
- rv = 0xffff;
- *sat = 1;
- }
- else
- {
- rv = val & 0xffff;
- *sat = 0;
- }
- return rv;
-}
-
-static signed short
-IwmmxtSaturateS16 (signed int val, int * sat)
-{
- signed short rv;
-
- if (val < -0x8000)
- {
- rv = - 0x8000;
- *sat = 1;
- }
- else if (val > 0x7fff)
- {
- rv = 0x7fff;
- *sat = 1;
- }
- else
- {
- rv = val & 0xffff;
- *sat = 0;
- }
- return rv;
-}
-
-static unsigned long
-IwmmxtSaturateU32 (signed long long val, int * sat)
-{
- unsigned long rv;
-
- if (val < 0)
- {
- rv = 0;
- *sat = 1;
- }
- else if (val > 0xffffffff)
- {
- rv = 0xffffffff;
- *sat = 1;
- }
- else
- {
- rv = val & 0xffffffff;
- *sat = 0;
- }
- return rv;
-}
-
-static signed long
-IwmmxtSaturateS32 (signed long long val, int * sat)
-{
- signed long rv;
-
- if (val < -0x80000000LL)
- {
- rv = -0x80000000;
- *sat = 1;
- }
- else if (val > 0x7fffffff)
- {
- rv = 0x7fffffff;
- *sat = 1;
- }
- else
- {
- rv = val & 0xffffffff;
- *sat = 0;
- }
- return rv;
-}
-
-/* Intel(r) Wireless MMX(tm) technology Acessor functions. */
-
-unsigned
-IwmmxtLDC (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword data)
-{
- return ARMul_CANT;
-}
-
-unsigned
-IwmmxtSTC (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword * data)
-{
- return ARMul_CANT;
-}
-
-unsigned
-IwmmxtMRC (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword * value)
-{
- return ARMul_CANT;
-}
-
-unsigned
-IwmmxtMCR (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword value)
-{
- return ARMul_CANT;
-}
-
-unsigned
-IwmmxtCDP (ARMul_State * state, unsigned type, ARMword instr)
-{
- return ARMul_CANT;
-}
-
-/* Intel(r) Wireless MMX(tm) technology instruction implementations. */
-
-static int
-TANDC (ARMul_State * state, ARMword instr)
-{
- ARMword cpsr;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tandc\n");
-#endif
-
- /* The Rd field must be r15. */
- if (BITS (12, 15) != 15)
- return ARMul_CANT;
-
- /* The CRn field must be r3. */
- if (BITS (16, 19) != 3)
- return ARMul_CANT;
-
- /* The CRm field must be r0. */
- if (BITS (0, 3) != 0)
- return ARMul_CANT;
-
- cpsr = ARMul_GetCPSR (state) & 0x0fffffff;
-
- switch (BITS (22, 23))
- {
- case Bqual:
- cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 24, 27)
- & wCBITS (wCASF, 20, 23) & wCBITS (wCASF, 16, 19)
- & wCBITS (wCASF, 12, 15) & wCBITS (wCASF, 8, 11)
- & wCBITS (wCASF, 4, 7) & wCBITS (wCASF, 0, 3)) << 28);
- break;
-
- case Hqual:
- cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 20, 23)
- & wCBITS (wCASF, 12, 15) & wCBITS (wCASF, 4, 7)) << 28);
- break;
-
- case Wqual:
- cpsr |= ((wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 12, 15)) << 28);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- ARMul_SetCPSR (state, cpsr);
-
- return ARMul_DONE;
-}
-
-static int
-TBCST (ARMul_State * state, ARMword instr)
-{
- ARMdword Rn;
- int wRd;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tbcst\n");
-#endif
-
- Rn = state->Reg [BITS (12, 15)];
- if (BITS (12, 15) == 15)
- Rn &= 0xfffffffc;
-
- wRd = BITS (16, 19);
-
- switch (BITS (6, 7))
- {
- case Bqual:
- Rn &= 0xff;
- wR [wRd] = (Rn << 56) | (Rn << 48) | (Rn << 40) | (Rn << 32)
- | (Rn << 24) | (Rn << 16) | (Rn << 8) | Rn;
- break;
-
- case Hqual:
- Rn &= 0xffff;
- wR [wRd] = (Rn << 48) | (Rn << 32) | (Rn << 16) | Rn;
- break;
-
- case Wqual:
- Rn &= 0xffffffff;
- wR [wRd] = (Rn << 32) | Rn;
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- break;
- }
-
- wC [wCon] |= WCON_MUP;
- return ARMul_DONE;
-}
-
-static int
-TEXTRC (ARMul_State * state, ARMword instr)
-{
- ARMword cpsr;
- ARMword selector;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "textrc\n");
-#endif
-
- /* The Rd field must be r15. */
- if (BITS (12, 15) != 15)
- return ARMul_CANT;
-
- /* The CRn field must be r3. */
- if (BITS (16, 19) != 3)
- return ARMul_CANT;
-
- /* The CRm field must be 0xxx. */
- if (BIT (3) != 0)
- return ARMul_CANT;
-
- selector = BITS (0, 2);
- cpsr = ARMul_GetCPSR (state) & 0x0fffffff;
-
- switch (BITS (22, 23))
- {
- case Bqual: selector *= 4; break;
- case Hqual: selector = ((selector & 3) * 8) + 4; break;
- case Wqual: selector = ((selector & 1) * 16) + 12; break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- cpsr |= wCBITS (wCASF, selector, selector + 3) << 28;
- ARMul_SetCPSR (state, cpsr);
-
- return ARMul_DONE;
-}
-
-static int
-TEXTRM (ARMul_State * state, ARMword instr)
-{
- ARMword Rd;
- int offset;
- int wRn;
- int sign;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "textrm\n");
-#endif
-
- wRn = BITS (16, 19);
- sign = BIT (3);
- offset = BITS (0, 2);
-
- switch (BITS (22, 23))
- {
- case Bqual:
- offset *= 8;
- Rd = wRBITS (wRn, offset, offset + 7);
- if (sign)
- Rd = EXTEND8 (Rd);
- break;
-
- case Hqual:
- offset = (offset & 3) * 16;
- Rd = wRBITS (wRn, offset, offset + 15);
- if (sign)
- Rd = EXTEND16 (Rd);
- break;
-
- case Wqual:
- offset = (offset & 1) * 32;
- Rd = wRBITS (wRn, offset, offset + 31);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- if (BITS (12, 15) == 15)
- ARMul_UndefInstr (state, instr);
- else
- state->Reg [BITS (12, 15)] = Rd;
-
- return ARMul_DONE;
-}
-
-static int
-TINSR (ARMul_State * state, ARMword instr)
-{
- ARMdword data;
- ARMword offset;
- int wRd;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tinsr\n");
-#endif
-
- wRd = BITS (16, 19);
- data = state->Reg [BITS (12, 15)];
- offset = BITS (0, 2);
-
- switch (BITS (6, 7))
- {
- case Bqual:
- data &= 0xff;
- switch (offset)
- {
- case 0: wR [wRd] = data | (wRBITS (wRd, 8, 63) << 8); break;
- case 1: wR [wRd] = wRBITS (wRd, 0, 7) | (data << 8) | (wRBITS (wRd, 16, 63) << 16); break;
- case 2: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 24, 63) << 24); break;
- case 3: wR [wRd] = wRBITS (wRd, 0, 23) | (data << 24) | (wRBITS (wRd, 32, 63) << 32); break;
- case 4: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 40, 63) << 40); break;
- case 5: wR [wRd] = wRBITS (wRd, 0, 39) | (data << 40) | (wRBITS (wRd, 48, 63) << 48); break;
- case 6: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48) | (wRBITS (wRd, 56, 63) << 56); break;
- case 7: wR [wRd] = wRBITS (wRd, 0, 55) | (data << 56); break;
- }
- break;
-
- case Hqual:
- data &= 0xffff;
-
- switch (offset & 3)
- {
- case 0: wR [wRd] = data | (wRBITS (wRd, 16, 63) << 16); break;
- case 1: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 32, 63) << 32); break;
- case 2: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 48, 63) << 48); break;
- case 3: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48); break;
- }
- break;
-
- case Wqual:
- if (offset & 1)
- wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32);
- else
- wR [wRd] = (wRBITS (wRd, 32, 63) << 32) | data;
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- break;
- }
-
- wC [wCon] |= WCON_MUP;
- return ARMul_DONE;
-}
-
-static int
-TMCR (ARMul_State * state, ARMword instr)
-{
- ARMword val;
- int wCreg;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tmcr\n");
-#endif
-
- if (BITS (0, 3) != 0)
- return ARMul_CANT;
-
- val = state->Reg [BITS (12, 15)];
- if (BITS (12, 15) == 15)
- val &= 0xfffffffc;
-
- wCreg = BITS (16, 19);
-
- switch (wCreg)
- {
- case wCID:
- /* The wCID register is read only. */
- break;
-
- case wCon:
- /* Writing to the MUP or CUP bits clears them. */
- wC [wCon] &= ~ (val & 0x3);
- break;
-
- case wCSSF:
- /* Only the bottom 8 bits can be written to.
- The higher bits write as zero. */
- wC [wCSSF] = (val & 0xff);
- wC [wCon] |= WCON_CUP;
- break;
-
- default:
- wC [wCreg] = val;
- wC [wCon] |= WCON_CUP;
- break;
- }
-
- return ARMul_DONE;
-}
-
-static int
-TMCRR (ARMul_State * state, ARMword instr)
-{
- ARMdword RdHi = state->Reg [BITS (16, 19)];
- ARMword RdLo = state->Reg [BITS (12, 15)];
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tmcrr\n");
-#endif
-
- if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15))
- return ARMul_CANT;
-
- wR [BITS (0, 3)] = (RdHi << 32) | RdLo;
-
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-TMIA (ARMul_State * state, ARMword instr)
-{
- signed long long a, b;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tmia\n");
-#endif
-
- if ((BITS (0, 3) == 15) || (BITS (12, 15) == 15))
- {
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- a = state->Reg [BITS (0, 3)];
- b = state->Reg [BITS (12, 15)];
-
- a = EXTEND32 (a);
- b = EXTEND32 (b);
-
- wR [BITS (5, 8)] += a * b;
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-TMIAPH (ARMul_State * state, ARMword instr)
-{
- signed long a, b, result;
- signed long long r;
- ARMword Rm = state->Reg [BITS (0, 3)];
- ARMword Rs = state->Reg [BITS (12, 15)];
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tmiaph\n");
-#endif
-
- if (BITS (0, 3) == 15 || BITS (12, 15) == 15)
- {
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- a = SUBSTR (Rs, ARMword, 16, 31);
- b = SUBSTR (Rm, ARMword, 16, 31);
-
- a = EXTEND16 (a);
- b = EXTEND16 (b);
-
- result = a * b;
-
- r = result;
- r = EXTEND32 (r);
-
- wR [BITS (5, 8)] += r;
-
- a = SUBSTR (Rs, ARMword, 0, 15);
- b = SUBSTR (Rm, ARMword, 0, 15);
-
- a = EXTEND16 (a);
- b = EXTEND16 (b);
-
- result = a * b;
-
- r = result;
- r = EXTEND32 (r);
-
- wR [BITS (5, 8)] += r;
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-TMIAxy (ARMul_State * state, ARMword instr)
-{
- ARMword Rm;
- ARMword Rs;
- long long temp;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tmiaxy\n");
-#endif
-
- if (BITS (0, 3) == 15 || BITS (12, 15) == 15)
- {
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- Rm = state->Reg [BITS (0, 3)];
- if (BIT (17))
- Rm >>= 16;
- else
- Rm &= 0xffff;
-
- Rs = state->Reg [BITS (12, 15)];
- if (BIT (16))
- Rs >>= 16;
- else
- Rs &= 0xffff;
-
- if (Rm & (1 << 15))
- Rm -= 1 << 16;
-
- if (Rs & (1 << 15))
- Rs -= 1 << 16;
-
- Rm *= Rs;
- temp = Rm;
-
- if (temp & (1 << 31))
- temp -= 1ULL << 32;
-
- wR [BITS (5, 8)] += temp;
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-TMOVMSK (ARMul_State * state, ARMword instr)
-{
- ARMdword result;
- int wRn;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tmovmsk\n");
-#endif
-
- /* The CRm field must be r0. */
- if (BITS (0, 3) != 0)
- return ARMul_CANT;
-
- wRn = BITS (16, 19);
-
- switch (BITS (22, 23))
- {
- case Bqual:
- result = ( (wRBITS (wRn, 63, 63) << 7)
- | (wRBITS (wRn, 55, 55) << 6)
- | (wRBITS (wRn, 47, 47) << 5)
- | (wRBITS (wRn, 39, 39) << 4)
- | (wRBITS (wRn, 31, 31) << 3)
- | (wRBITS (wRn, 23, 23) << 2)
- | (wRBITS (wRn, 15, 15) << 1)
- | (wRBITS (wRn, 7, 7) << 0));
- break;
-
- case Hqual:
- result = ( (wRBITS (wRn, 63, 63) << 3)
- | (wRBITS (wRn, 47, 47) << 2)
- | (wRBITS (wRn, 31, 31) << 1)
- | (wRBITS (wRn, 15, 15) << 0));
- break;
-
- case Wqual:
- result = (wRBITS (wRn, 63, 63) << 1) | wRBITS (wRn, 31, 31);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- state->Reg [BITS (12, 15)] = result;
-
- return ARMul_DONE;
-}
-
-static int
-TMRC (ARMul_State * state, ARMword instr)
-{
- int reg = BITS (12, 15);
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tmrc\n");
-#endif
-
- if (BITS (0, 3) != 0)
- return ARMul_CANT;
-
- if (reg == 15)
- ARMul_UndefInstr (state, instr);
- else
- state->Reg [reg] = wC [BITS (16, 19)];
-
- return ARMul_DONE;
-}
-
-static int
-TMRRC (ARMul_State * state, ARMword instr)
-{
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "tmrrc\n");
-#endif
-
- if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15) || (BITS (4, 11) != 0))
- ARMul_UndefInstr (state, instr);
- else
- {
- state->Reg [BITS (16, 19)] = wRBITS (BITS (0, 3), 32, 63);
- state->Reg [BITS (12, 15)] = wRBITS (BITS (0, 3), 0, 31);
- }
-
- return ARMul_DONE;
-}
-
-static int
-TORC (ARMul_State * state, ARMword instr)
-{
- ARMword cpsr = ARMul_GetCPSR (state);
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "torc\n");
-#endif
-
- /* The Rd field must be r15. */
- if (BITS (12, 15) != 15)
- return ARMul_CANT;
-
- /* The CRn field must be r3. */
- if (BITS (16, 19) != 3)
- return ARMul_CANT;
-
- /* The CRm field must be r0. */
- if (BITS (0, 3) != 0)
- return ARMul_CANT;
-
- cpsr &= 0x0fffffff;
-
- switch (BITS (22, 23))
- {
- case Bqual:
- cpsr |= ( (wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 24, 27)
- | wCBITS (wCASF, 20, 23) | wCBITS (wCASF, 16, 19)
- | wCBITS (wCASF, 12, 15) | wCBITS (wCASF, 8, 11)
- | wCBITS (wCASF, 4, 7) | wCBITS (wCASF, 0, 3)) << 28);
- break;
-
- case Hqual:
- cpsr |= ( (wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 20, 23)
- | wCBITS (wCASF, 12, 15) | wCBITS (wCASF, 4, 7)) << 28);
- break;
-
- case Wqual:
- cpsr |= ((wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 12, 15)) << 28);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- ARMul_SetCPSR (state, cpsr);
-
- return ARMul_DONE;
-}
-
-static int
-WACC (ARMul_State * state, ARMword instr)
-{
- int wRn;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wacc\n");
-#endif
-
- wRn = BITS (16, 19);
-
- switch (BITS (22, 23))
- {
- case Bqual:
- wR [BITS (12, 15)] =
- wRBITS (wRn, 56, 63) + wRBITS (wRn, 48, 55)
- + wRBITS (wRn, 40, 47) + wRBITS (wRn, 32, 39)
- + wRBITS (wRn, 24, 31) + wRBITS (wRn, 16, 23)
- + wRBITS (wRn, 8, 15) + wRBITS (wRn, 0, 7);
- break;
-
- case Hqual:
- wR [BITS (12, 15)] =
- wRBITS (wRn, 48, 63) + wRBITS (wRn, 32, 47)
- + wRBITS (wRn, 16, 31) + wRBITS (wRn, 0, 15);
- break;
-
- case Wqual:
- wR [BITS (12, 15)] = wRBITS (wRn, 32, 63) + wRBITS (wRn, 0, 31);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- break;
- }
-
- wC [wCon] |= WCON_MUP;
- return ARMul_DONE;
-}
-
-static int
-WADD (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMdword x;
- ARMdword s;
- ARMword psr = 0;
- int i;
- int carry;
- int overflow;
- int satrv[8];
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wadd\n");
-#endif
-
- /* Add two numbers using the specified function,
- leaving setting the carry bit as required. */
-#define ADDx(x, y, m, f) \
- (*f) (wRBITS (BITS (16, 19), (x), (y)) & (m), \
- wRBITS (BITS ( 0, 3), (x), (y)) & (m), \
- & carry, & overflow)
-
- switch (BITS (22, 23))
- {
- case Bqual:
- for (i = 0; i < 8; i++)
- {
- switch (BITS (20, 21))
- {
- case NoSaturation:
- s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddS8);
- satrv [BITIDX8 (i)] = 0;
- r |= (s & 0xff) << (i * 8);
- SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
- SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
- SIMD8_SET (psr, carry, SIMD_CBIT, i);
- SIMD8_SET (psr, overflow, SIMD_VBIT, i);
- break;
-
- case UnsignedSaturation:
- s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddU8);
- x = IwmmxtSaturateU8 (s, satrv + BITIDX8 (i));
- r |= (x & 0xff) << (i * 8);
- SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
- SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX8 (i)])
- {
- SIMD8_SET (psr, carry, SIMD_CBIT, i);
- SIMD8_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- case SignedSaturation:
- s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddS8);
- x = IwmmxtSaturateS8 (s, satrv + BITIDX8 (i));
- r |= (x & 0xff) << (i * 8);
- SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
- SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX8 (i)])
- {
- SIMD8_SET (psr, carry, SIMD_CBIT, i);
- SIMD8_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
- }
- break;
-
- case Hqual:
- satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0;
-
- for (i = 0; i < 4; i++)
- {
- switch (BITS (20, 21))
- {
- case NoSaturation:
- s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddS16);
- satrv [BITIDX16 (i)] = 0;
- r |= (s & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- SIMD16_SET (psr, carry, SIMD_CBIT, i);
- SIMD16_SET (psr, overflow, SIMD_VBIT, i);
- break;
-
- case UnsignedSaturation:
- s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddU16);
- x = IwmmxtSaturateU16 (s, satrv + BITIDX16 (i));
- r |= (x & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX16 (i)])
- {
- SIMD16_SET (psr, carry, SIMD_CBIT, i);
- SIMD16_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- case SignedSaturation:
- s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddS16);
- x = IwmmxtSaturateS16 (s, satrv + BITIDX16 (i));
- r |= (x & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX16 (i)])
- {
- SIMD16_SET (psr, carry, SIMD_CBIT, i);
- SIMD16_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
- }
- break;
-
- case Wqual:
- satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0;
-
- for (i = 0; i < 2; i++)
- {
- switch (BITS (20, 21))
- {
- case NoSaturation:
- s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddS32);
- satrv [BITIDX32 (i)] = 0;
- r |= (s & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- SIMD32_SET (psr, carry, SIMD_CBIT, i);
- SIMD32_SET (psr, overflow, SIMD_VBIT, i);
- break;
-
- case UnsignedSaturation:
- s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddU32);
- x = IwmmxtSaturateU32 (s, satrv + BITIDX32 (i));
- r |= (x & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX32 (i)])
- {
- SIMD32_SET (psr, carry, SIMD_CBIT, i);
- SIMD32_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- case SignedSaturation:
- s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddS32);
- x = IwmmxtSaturateS32 (s, satrv + BITIDX32 (i));
- r |= (x & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX32 (i)])
- {
- SIMD32_SET (psr, carry, SIMD_CBIT, i);
- SIMD32_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_MUP | WCON_CUP);
-
- SET_wCSSFvec (satrv);
-
-#undef ADDx
-
- return ARMul_DONE;
-}
-
-static int
-WALIGNI (ARMword instr)
-{
- int shift = BITS (20, 22) * 8;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "waligni\n");
-#endif
-
- if (shift)
- wR [BITS (12, 15)] =
- wRBITS (BITS (16, 19), shift, 63)
- | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift)));
- else
- wR [BITS (12, 15)] = wR [BITS (16, 19)];
-
- wC [wCon] |= WCON_MUP;
- return ARMul_DONE;
-}
-
-static int
-WALIGNR (ARMul_State * state, ARMword instr)
-{
- int shift = (wC [BITS (20, 21) + 8] & 0x7) * 8;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "walignr\n");
-#endif
-
- if (shift)
- wR [BITS (12, 15)] =
- wRBITS (BITS (16, 19), shift, 63)
- | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift)));
- else
- wR [BITS (12, 15)] = wR [BITS (16, 19)];
-
- wC [wCon] |= WCON_MUP;
- return ARMul_DONE;
-}
-
-static int
-WAND (ARMword instr)
-{
- ARMdword result;
- ARMword psr = 0;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wand\n");
-#endif
-
- result = wR [BITS (16, 19)] & wR [BITS (0, 3)];
- wR [BITS (12, 15)] = result;
-
- SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
- SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
-
- wC [wCASF] = psr;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WANDN (ARMword instr)
-{
- ARMdword result;
- ARMword psr = 0;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wandn\n");
-#endif
-
- result = wR [BITS (16, 19)] & ~ wR [BITS (0, 3)];
- wR [BITS (12, 15)] = result;
-
- SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
- SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
-
- wC [wCASF] = psr;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WAVG2 (ARMword instr)
-{
- ARMdword r = 0;
- ARMword psr = 0;
- ARMdword s;
- int i;
- int round = BIT (20) ? 1 : 0;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wavg2\n");
-#endif
-
-#define AVG2x(x, y, m) (((wRBITS (BITS (16, 19), (x), (y)) & (m)) \
- + (wRBITS (BITS ( 0, 3), (x), (y)) & (m)) \
- + round) / 2)
-
- if (BIT (22))
- {
- for (i = 0; i < 4; i++)
- {
- s = AVG2x ((i * 16), (i * 16) + 15, 0xffff) & 0xffff;
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- r |= s << (i * 16);
- }
- }
- else
- {
- for (i = 0; i < 8; i++)
- {
- s = AVG2x ((i * 8), (i * 8) + 7, 0xff) & 0xff;
- SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
- r |= s << (i * 8);
- }
- }
-
- wR [BITS (12, 15)] = r;
- wC [wCASF] = psr;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WCMPEQ (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMword psr = 0;
- ARMdword s;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wcmpeq\n");
-#endif
-
- switch (BITS (22, 23))
- {
- case Bqual:
- for (i = 0; i < 8; i++)
- {
- s = wRBYTE (BITS (16, 19), i) == wRBYTE (BITS (0, 3), i) ? 0xff : 0;
- r |= s << (i * 8);
- SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
- SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Hqual:
- for (i = 0; i < 4; i++)
- {
- s = wRHALF (BITS (16, 19), i) == wRHALF (BITS (0, 3), i) ? 0xffff : 0;
- r |= s << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Wqual:
- for (i = 0; i < 2; i++)
- {
- s = wRWORD (BITS (16, 19), i) == wRWORD (BITS (0, 3), i) ? 0xffffffff : 0;
- r |= s << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WCMPGT (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMword psr = 0;
- ARMdword s;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wcmpgt\n");
-#endif
-
- switch (BITS (22, 23))
- {
- case Bqual:
- if (BIT (21))
- {
- /* Use a signed comparison. */
- for (i = 0; i < 8; i++)
- {
- signed char a, b;
-
- a = wRBYTE (BITS (16, 19), i);
- b = wRBYTE (BITS (0, 3), i);
-
- s = (a > b) ? 0xff : 0;
- r |= s << (i * 8);
- SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
- SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
- }
- }
- else
- {
- for (i = 0; i < 8; i++)
- {
- s = (wRBYTE (BITS (16, 19), i) > wRBYTE (BITS (0, 3), i))
- ? 0xff : 0;
- r |= s << (i * 8);
- SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
- SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
- }
- }
- break;
-
- case Hqual:
- if (BIT (21))
- {
- for (i = 0; i < 4; i++)
- {
- signed int a, b;
-
- a = wRHALF (BITS (16, 19), i);
- a = EXTEND16 (a);
-
- b = wRHALF (BITS (0, 3), i);
- b = EXTEND16 (b);
-
- s = (a > b) ? 0xffff : 0;
- r |= s << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
- }
- else
- {
- for (i = 0; i < 4; i++)
- {
- s = (wRHALF (BITS (16, 19), i) > wRHALF (BITS (0, 3), i))
- ? 0xffff : 0;
- r |= s << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
- }
- break;
-
- case Wqual:
- if (BIT (21))
- {
- for (i = 0; i < 2; i++)
- {
- signed long a, b;
-
- a = EXTEND32 (wRWORD (BITS (16, 19), i));
- b = EXTEND32 (wRWORD (BITS (0, 3), i));
-
- s = (a > b) ? 0xffffffff : 0;
- r |= s << (i * 32);
-
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- }
- }
- else
- {
- for (i = 0; i < 2; i++)
- {
- s = (wRWORD (BITS (16, 19), i) > wRWORD (BITS (0, 3), i))
- ? 0xffffffff : 0;
- r |= s << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- }
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static ARMword
-Compute_Iwmmxt_Address (ARMul_State * state, ARMword instr, int * pFailed)
-{
- ARMword Rn;
- ARMword addr;
- ARMword offset;
- ARMword multiplier;
-
- * pFailed = 0;
- Rn = BITS (16, 19);
- addr = state->Reg [Rn];
- offset = BITS (0, 7);
- multiplier = BIT (8) ? 4 : 1;
-
- if (BIT (24)) /* P */
- {
- /* Pre Indexed Addressing. */
- if (BIT (23))
- addr += offset * multiplier;
- else
- addr -= offset * multiplier;
-
- /* Immediate Pre-Indexed. */
- if (BIT (21)) /* W */
- {
- if (Rn == 15)
- {
- /* Writeback into R15 is UNPREDICTABLE. */
-#ifdef DEBUG
- fprintf (stderr, "iWMMXt: writeback into r15\n");
-#endif
- * pFailed = 1;
- }
- else
- state->Reg [Rn] = addr;
- }
- }
- else
- {
- /* Post Indexed Addressing. */
- if (BIT (21)) /* W */
- {
- /* Handle the write back of the final address. */
- if (Rn == 15)
- {
- /* Writeback into R15 is UNPREDICTABLE. */
-#ifdef DEBUG
- fprintf (stderr, "iWMMXt: writeback into r15\n");
-#endif
- * pFailed = 1;
- }
- else
- {
- ARMword increment;
-
- if (BIT (23))
- increment = offset * multiplier;
- else
- increment = - (offset * multiplier);
-
- state->Reg [Rn] = addr + increment;
- }
- }
- else
- {
- /* P == 0, W == 0, U == 0 is UNPREDICTABLE. */
- if (BIT (23) == 0)
- {
-#ifdef DEBUG
- fprintf (stderr, "iWMMXt: undefined addressing mode\n");
-#endif
- * pFailed = 1;
- }
- }
- }
-
- return addr;
-}
-
-static ARMdword
-Iwmmxt_Load_Double_Word (ARMul_State * state, ARMword address)
-{
- ARMdword value;
-
- /* The address must be aligned on a 8 byte boundary. */
- if (address & 0x7)
- {
- fprintf (stderr, "iWMMXt: At addr 0x%x: Unaligned double word load from 0x%x\n",
- (state->Reg[15] - 8) & ~0x3, address);
-#ifdef DEBUG
-#endif
- /* No need to check for alignment traps. An unaligned
- double word load with alignment trapping disabled is
- UNPREDICTABLE. */
- ARMul_Abort (state, ARMul_DataAbortV);
- }
-
- /* Load the words. */
- if (! state->bigendSig)
- {
- value = ARMul_LoadWordN (state, address + 4);
- value <<= 32;
- value |= ARMul_LoadWordN (state, address);
- }
- else
- {
- value = ARMul_LoadWordN (state, address);
- value <<= 32;
- value |= ARMul_LoadWordN (state, address + 4);
- }
-
- /* Check for data aborts. */
- if (state->Aborted)
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- ARMul_Icycles (state, 2, 0L);
-
- return value;
-}
-
-static ARMword
-Iwmmxt_Load_Word (ARMul_State * state, ARMword address)
-{
- ARMword value;
-
- /* Check for a misaligned address. */
- if (address & 3)
- {
- if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- address &= ~ 3;
- }
-
- value = ARMul_LoadWordN (state, address);
-
- if (state->Aborted)
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- ARMul_Icycles (state, 1, 0L);
-
- return value;
-}
-
-static ARMword
-Iwmmxt_Load_Half_Word (ARMul_State * state, ARMword address)
-{
- ARMword value;
-
- /* Check for a misaligned address. */
- if (address & 1)
- {
- if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- address &= ~ 1;
- }
-
- value = ARMul_LoadHalfWord (state, address);
-
- if (state->Aborted)
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- ARMul_Icycles (state, 1, 0L);
-
- return value;
-}
-
-static ARMword
-Iwmmxt_Load_Byte (ARMul_State * state, ARMword address)
-{
- ARMword value;
-
- value = ARMul_LoadByte (state, address);
-
- if (state->Aborted)
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- ARMul_Icycles (state, 1, 0L);
-
- return value;
-}
-
-static void
-Iwmmxt_Store_Double_Word (ARMul_State * state, ARMword address, ARMdword value)
-{
- /* The address must be aligned on a 8 byte boundary. */
- if (address & 0x7)
- {
- fprintf (stderr, "iWMMXt: At addr 0x%x: Unaligned double word store to 0x%x\n",
- (state->Reg[15] - 8) & ~0x3, address);
-#ifdef DEBUG
-#endif
- /* No need to check for alignment traps. An unaligned
- double word store with alignment trapping disabled is
- UNPREDICTABLE. */
- ARMul_Abort (state, ARMul_DataAbortV);
- }
-
- /* Store the words. */
- if (! state->bigendSig)
- {
- ARMul_StoreWordN (state, address, value);
- ARMul_StoreWordN (state, address + 4, value >> 32);
- }
- else
- {
- ARMul_StoreWordN (state, address + 4, value);
- ARMul_StoreWordN (state, address, value >> 32);
- }
-
- /* Check for data aborts. */
- if (state->Aborted)
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- ARMul_Icycles (state, 2, 0L);
-}
-
-static void
-Iwmmxt_Store_Word (ARMul_State * state, ARMword address, ARMword value)
-{
- /* Check for a misaligned address. */
- if (address & 3)
- {
- if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- address &= ~ 3;
- }
-
- ARMul_StoreWordN (state, address, value);
-
- if (state->Aborted)
- ARMul_Abort (state, ARMul_DataAbortV);
-}
-
-static void
-Iwmmxt_Store_Half_Word (ARMul_State * state, ARMword address, ARMword value)
-{
- /* Check for a misaligned address. */
- if (address & 1)
- {
- if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
- ARMul_Abort (state, ARMul_DataAbortV);
- else
- address &= ~ 1;
- }
-
- ARMul_StoreHalfWord (state, address, value);
-
- if (state->Aborted)
- ARMul_Abort (state, ARMul_DataAbortV);
-}
-
-static void
-Iwmmxt_Store_Byte (ARMul_State * state, ARMword address, ARMword value)
-{
- ARMul_StoreByte (state, address, value);
-
- if (state->Aborted)
- ARMul_Abort (state, ARMul_DataAbortV);
-}
-
-static int
-WLDR (ARMul_State * state, ARMword instr)
-{
- ARMword address;
- int failed;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wldr\n");
-#endif
-
- address = Compute_Iwmmxt_Address (state, instr, & failed);
- if (failed)
- return ARMul_CANT;
-
- if (BITS (28, 31) == 0xf)
- {
- /* WLDRW wCx */
- wC [BITS (12, 15)] = Iwmmxt_Load_Word (state, address);
- }
- else if (BIT (8) == 0)
- {
- if (BIT (22) == 0)
- /* WLDRB */
- wR [BITS (12, 15)] = Iwmmxt_Load_Byte (state, address);
- else
- /* WLDRH */
- wR [BITS (12, 15)] = Iwmmxt_Load_Half_Word (state, address);
- }
- else
- {
- if (BIT (22) == 0)
- /* WLDRW wRd */
- wR [BITS (12, 15)] = Iwmmxt_Load_Word (state, address);
- else
- /* WLDRD */
- wR [BITS (12, 15)] = Iwmmxt_Load_Double_Word (state, address);
- }
-
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-WMAC (ARMword instr)
-{
- int i;
- ARMdword t = 0;
- ARMword a, b;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wmac\n");
-#endif
-
- for (i = 0; i < 4; i++)
- {
- if (BIT (21))
- {
- /* Signed. */
- signed long s;
-
- a = wRHALF (BITS (16, 19), i);
- a = EXTEND16 (a);
-
- b = wRHALF (BITS (0, 3), i);
- b = EXTEND16 (b);
-
- s = (signed long) a * (signed long) b;
-
- t = t + (ARMdword) s;
- }
- else
- {
- /* Unsigned. */
- a = wRHALF (BITS (16, 19), i);
- b = wRHALF (BITS ( 0, 3), i);
-
- t += a * b;
- }
- }
-
- if (BIT (21))
- t = EXTEND32 (t);
- else
- t &= 0xffffffff;
-
- if (BIT (20))
- wR [BITS (12, 15)] = t;
- else
- wR[BITS (12, 15)] += t;
-
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-WMADD (ARMword instr)
-{
- ARMdword r = 0;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wmadd\n");
-#endif
-
- for (i = 0; i < 2; i++)
- {
- ARMdword s1, s2;
-
- if (BIT (21)) /* Signed. */
- {
- signed long a, b;
-
- a = wRHALF (BITS (16, 19), i * 2);
- a = EXTEND16 (a);
-
- b = wRHALF (BITS (0, 3), i * 2);
- b = EXTEND16 (b);
-
- s1 = (ARMdword) (a * b);
-
- a = wRHALF (BITS (16, 19), i * 2 + 1);
- a = EXTEND16 (a);
-
- b = wRHALF (BITS (0, 3), i * 2 + 1);
- b = EXTEND16 (b);
-
- s2 = (ARMdword) (a * b);
- }
- else /* Unsigned. */
- {
- unsigned long a, b;
-
- a = wRHALF (BITS (16, 19), i * 2);
- b = wRHALF (BITS ( 0, 3), i * 2);
-
- s1 = (ARMdword) (a * b);
-
- a = wRHALF (BITS (16, 19), i * 2 + 1);
- b = wRHALF (BITS ( 0, 3), i * 2 + 1);
-
- s2 = (ARMdword) a * b;
- }
-
- r |= (ARMdword) ((s1 + s2) & 0xffffffff) << (i ? 32 : 0);
- }
-
- wR [BITS (12, 15)] = r;
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-WMAX (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMdword s;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wmax\n");
-#endif
-
- switch (BITS (22, 23))
- {
- case Bqual:
- for (i = 0; i < 8; i++)
- if (BIT (21)) /* Signed. */
- {
- int a, b;
-
- a = wRBYTE (BITS (16, 19), i);
- a = EXTEND8 (a);
-
- b = wRBYTE (BITS (0, 3), i);
- b = EXTEND8 (b);
-
- if (a > b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xff) << (i * 8);
- }
- else /* Unsigned. */
- {
- unsigned int a, b;
-
- a = wRBYTE (BITS (16, 19), i);
- b = wRBYTE (BITS (0, 3), i);
-
- if (a > b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xff) << (i * 8);
- }
- break;
-
- case Hqual:
- for (i = 0; i < 4; i++)
- if (BIT (21)) /* Signed. */
- {
- int a, b;
-
- a = wRHALF (BITS (16, 19), i);
- a = EXTEND16 (a);
-
- b = wRHALF (BITS (0, 3), i);
- b = EXTEND16 (b);
-
- if (a > b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xffff) << (i * 16);
- }
- else /* Unsigned. */
- {
- unsigned int a, b;
-
- a = wRHALF (BITS (16, 19), i);
- b = wRHALF (BITS (0, 3), i);
-
- if (a > b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xffff) << (i * 16);
- }
- break;
-
- case Wqual:
- for (i = 0; i < 2; i++)
- if (BIT (21)) /* Signed. */
- {
- int a, b;
-
- a = wRWORD (BITS (16, 19), i);
- b = wRWORD (BITS (0, 3), i);
-
- if (a > b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xffffffff) << (i * 32);
- }
- else
- {
- unsigned int a, b;
-
- a = wRWORD (BITS (16, 19), i);
- b = wRWORD (BITS (0, 3), i);
-
- if (a > b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xffffffff) << (i * 32);
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wR [BITS (12, 15)] = r;
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-WMIN (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMdword s;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wmin\n");
-#endif
-
- switch (BITS (22, 23))
- {
- case Bqual:
- for (i = 0; i < 8; i++)
- if (BIT (21)) /* Signed. */
- {
- int a, b;
-
- a = wRBYTE (BITS (16, 19), i);
- a = EXTEND8 (a);
-
- b = wRBYTE (BITS (0, 3), i);
- b = EXTEND8 (b);
-
- if (a < b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xff) << (i * 8);
- }
- else /* Unsigned. */
- {
- unsigned int a, b;
-
- a = wRBYTE (BITS (16, 19), i);
- b = wRBYTE (BITS (0, 3), i);
-
- if (a < b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xff) << (i * 8);
- }
- break;
-
- case Hqual:
- for (i = 0; i < 4; i++)
- if (BIT (21)) /* Signed. */
- {
- int a, b;
-
- a = wRHALF (BITS (16, 19), i);
- a = EXTEND16 (a);
-
- b = wRHALF (BITS (0, 3), i);
- b = EXTEND16 (b);
-
- if (a < b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xffff) << (i * 16);
- }
- else
- {
- /* Unsigned. */
- unsigned int a, b;
-
- a = wRHALF (BITS (16, 19), i);
- b = wRHALF (BITS ( 0, 3), i);
-
- if (a < b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xffff) << (i * 16);
- }
- break;
-
- case Wqual:
- for (i = 0; i < 2; i++)
- if (BIT (21)) /* Signed. */
- {
- int a, b;
-
- a = wRWORD (BITS (16, 19), i);
- b = wRWORD (BITS ( 0, 3), i);
-
- if (a < b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xffffffff) << (i * 32);
- }
- else
- {
- unsigned int a, b;
-
- a = wRWORD (BITS (16, 19), i);
- b = wRWORD (BITS (0, 3), i);
-
- if (a < b)
- s = a;
- else
- s = b;
-
- r |= (s & 0xffffffff) << (i * 32);
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wR [BITS (12, 15)] = r;
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-WMUL (ARMword instr)
-{
- ARMdword r = 0;
- ARMdword s;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wmul\n");
-#endif
-
- for (i = 0; i < 4; i++)
- if (BIT (21)) /* Signed. */
- {
- long a, b;
-
- a = wRHALF (BITS (16, 19), i);
- a = EXTEND16 (a);
-
- b = wRHALF (BITS (0, 3), i);
- b = EXTEND16 (b);
-
- s = a * b;
-
- if (BIT (20))
- r |= ((s >> 16) & 0xffff) << (i * 16);
- else
- r |= (s & 0xffff) << (i * 16);
- }
- else /* Unsigned. */
- {
- unsigned long a, b;
-
- a = wRHALF (BITS (16, 19), i);
- b = wRHALF (BITS (0, 3), i);
-
- s = a * b;
-
- if (BIT (20))
- r |= ((s >> 16) & 0xffff) << (i * 16);
- else
- r |= (s & 0xffff) << (i * 16);
- }
-
- wR [BITS (12, 15)] = r;
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-WOR (ARMword instr)
-{
- ARMword psr = 0;
- ARMdword result;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wor\n");
-#endif
-
- result = wR [BITS (16, 19)] | wR [BITS (0, 3)];
- wR [BITS (12, 15)] = result;
-
- SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
- SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
-
- wC [wCASF] = psr;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WPACK (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMword psr = 0;
- ARMdword x;
- ARMdword s;
- int i;
- int satrv[8];
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wpack\n");
-#endif
-
- switch (BITS (22, 23))
- {
- case Hqual:
- for (i = 0; i < 8; i++)
- {
- x = wRHALF (i < 4 ? BITS (16, 19) : BITS (0, 3), i & 3);
-
- switch (BITS (20, 21))
- {
- case UnsignedSaturation:
- s = IwmmxtSaturateU8 (x, satrv + BITIDX8 (i));
- break;
-
- case SignedSaturation:
- s = IwmmxtSaturateS8 (x, satrv + BITIDX8 (i));
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- r |= (s & 0xff) << (i * 8);
- SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
- SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Wqual:
- satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0;
-
- for (i = 0; i < 4; i++)
- {
- x = wRWORD (i < 2 ? BITS (16, 19) : BITS (0, 3), i & 1);
-
- switch (BITS (20, 21))
- {
- case UnsignedSaturation:
- s = IwmmxtSaturateU16 (x, satrv + BITIDX16 (i));
- break;
-
- case SignedSaturation:
- s = IwmmxtSaturateS16 (x, satrv + BITIDX16 (i));
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- r |= (s & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Dqual:
- satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0;
-
- for (i = 0; i < 2; i++)
- {
- x = wR [i ? BITS (0, 3) : BITS (16, 19)];
-
- switch (BITS (20, 21))
- {
- case UnsignedSaturation:
- s = IwmmxtSaturateU32 (x, satrv + BITIDX32 (i));
- break;
-
- case SignedSaturation:
- s = IwmmxtSaturateS32 (x, satrv + BITIDX32 (i));
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- r |= (s & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- SET_wCSSFvec (satrv);
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WROR (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMdword s;
- ARMword psr = 0;
- int i;
- int shift;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wror\n");
-#endif
-
- DECODE_G_BIT (state, instr, shift);
-
- switch (BITS (22, 23))
- {
- case Hqual:
- shift &= 0xf;
- for (i = 0; i < 4; i++)
- {
- s = ((wRHALF (BITS (16, 19), i) & 0xffff) << (16 - shift))
- | ((wRHALF (BITS (16, 19), i) & 0xffff) >> shift);
- r |= (s & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Wqual:
- shift &= 0x1f;
- for (i = 0; i < 2; i++)
- {
- s = ((wRWORD (BITS (16, 19), i) & 0xffffffff) << (32 - shift))
- | ((wRWORD (BITS (16, 19), i) & 0xffffffff) >> shift);
- r |= (s & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Dqual:
- shift &= 0x3f;
- r = (wR [BITS (16, 19)] >> shift)
- | (wR [BITS (16, 19)] << (64 - shift));
-
- SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
- SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WSAD (ARMword instr)
-{
- ARMdword r;
- int s;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wsad\n");
-#endif
-
- /* Z bit. */
- r = BIT (20) ? 0 : (wR [BITS (12, 15)] & 0xffffffff);
-
- if (BIT (22))
- /* Half. */
- for (i = 0; i < 4; i++)
- {
- s = (wRHALF (BITS (16, 19), i) - wRHALF (BITS (0, 3), i));
- r += abs (s);
- }
- else
- /* Byte. */
- for (i = 0; i < 8; i++)
- {
- s = (wRBYTE (BITS (16, 19), i) - wRBYTE (BITS (0, 3), i));
- r += abs (s);
- }
-
- wR [BITS (12, 15)] = r;
- wC [wCon] |= WCON_MUP;
-
- return ARMul_DONE;
-}
-
-static int
-WSHUFH (ARMword instr)
-{
- ARMdword r = 0;
- ARMword psr = 0;
- ARMdword s;
- int i;
- int imm8;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wshufh\n");
-#endif
-
- imm8 = (BITS (20, 23) << 4) | BITS (0, 3);
-
- for (i = 0; i < 4; i++)
- {
- s = wRHALF (BITS (16, 19), ((imm8 >> (i * 2) & 3)) & 0xff);
- r |= (s & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WSLL (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMdword s;
- ARMword psr = 0;
- int i;
- unsigned shift;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wsll\n");
-#endif
-
- DECODE_G_BIT (state, instr, shift);
-
- switch (BITS (22, 23))
- {
- case Hqual:
- for (i = 0; i < 4; i++)
- {
- if (shift > 15)
- s = 0;
- else
- s = ((wRHALF (BITS (16, 19), i) & 0xffff) << shift);
- r |= (s & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Wqual:
- for (i = 0; i < 2; i++)
- {
- if (shift > 31)
- s = 0;
- else
- s = ((wRWORD (BITS (16, 19), i) & 0xffffffff) << shift);
- r |= (s & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Dqual:
- if (shift > 63)
- r = 0;
- else
- r = ((wR[BITS (16, 19)] & 0xffffffffffffffffULL) << shift);
-
- SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
- SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WSRA (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMdword s;
- ARMword psr = 0;
- int i;
- unsigned shift;
- signed long t;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wsra\n");
-#endif
-
- DECODE_G_BIT (state, instr, shift);
-
- switch (BITS (22, 23))
- {
- case Hqual:
- for (i = 0; i < 4; i++)
- {
- if (shift > 15)
- t = (wRHALF (BITS (16, 19), i) & 0x8000) ? 0xffff : 0;
- else
- {
- t = wRHALF (BITS (16, 19), i);
- t = EXTEND16 (t);
- t >>= shift;
- }
-
- s = t;
- r |= (s & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Wqual:
- for (i = 0; i < 2; i++)
- {
- if (shift > 31)
- t = (wRWORD (BITS (16, 19), i) & 0x80000000) ? 0xffffffff : 0;
- else
- {
- t = EXTEND32 (wRWORD (BITS (16, 19), i));
- t >>= shift;
- }
- s = t;
- r |= (s & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Dqual:
- if (shift > 63)
- r = (wR [BITS (16, 19)] & 0x8000000000000000ULL) ? 0xffffffffffffffffULL : 0;
- else
- r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffffULL) >> shift);
- SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
- SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WSRL (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMdword s;
- ARMword psr = 0;
- int i;
- unsigned int shift;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wsrl\n");
-#endif
-
- DECODE_G_BIT (state, instr, shift);
-
- switch (BITS (22, 23))
- {
- case Hqual:
- for (i = 0; i < 4; i++)
- {
- if (shift > 15)
- s = 0;
- else
- s = ((unsigned) (wRHALF (BITS (16, 19), i) & 0xffff) >> shift);
-
- r |= (s & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Wqual:
- for (i = 0; i < 2; i++)
- {
- if (shift > 31)
- s = 0;
- else
- s = ((unsigned long) (wRWORD (BITS (16, 19), i) & 0xffffffff) >> shift);
-
- r |= (s & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Dqual:
- if (shift > 63)
- r = 0;
- else
- r = (wR [BITS (16, 19)] & 0xffffffffffffffffULL) >> shift;
-
- SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
- SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WSTR (ARMul_State * state, ARMword instr)
-{
- ARMword address;
- int failed;
-
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wstr\n");
-#endif
-
- address = Compute_Iwmmxt_Address (state, instr, & failed);
- if (failed)
- return ARMul_CANT;
-
- if (BITS (28, 31) == 0xf)
- {
- /* WSTRW wCx */
- Iwmmxt_Store_Word (state, address, wC [BITS (12, 15)]);
- }
- else if (BIT (8) == 0)
- {
- if (BIT (22) == 0)
- /* WSTRB */
- Iwmmxt_Store_Byte (state, address, wR [BITS (12, 15)]);
- else
- /* WSTRH */
- Iwmmxt_Store_Half_Word (state, address, wR [BITS (12, 15)]);
- }
- else
- {
- if (BIT (22) == 0)
- /* WSTRW wRd */
- Iwmmxt_Store_Word (state, address, wR [BITS (12, 15)]);
- else
- /* WSTRD */
- Iwmmxt_Store_Double_Word (state, address, wR [BITS (12, 15)]);
- }
-
- return ARMul_DONE;
-}
-
-static int
-WSUB (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMword psr = 0;
- ARMdword x;
- ARMdword s;
- int i;
- int carry;
- int overflow;
- int satrv[8];
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wsub\n");
-#endif
-
-/* Subtract two numbers using the specified function,
- leaving setting the carry bit as required. */
-#define SUBx(x, y, m, f) \
- (*f) (wRBITS (BITS (16, 19), (x), (y)) & (m), \
- wRBITS (BITS ( 0, 3), (x), (y)) & (m), & carry, & overflow)
-
- switch (BITS (22, 23))
- {
- case Bqual:
- for (i = 0; i < 8; i++)
- {
- switch (BITS (20, 21))
- {
- case NoSaturation:
- s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubS8);
- satrv [BITIDX8 (i)] = 0;
- r |= (s & 0xff) << (i * 8);
- SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
- SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
- SIMD8_SET (psr, carry, SIMD_CBIT, i);
- SIMD8_SET (psr, overflow, SIMD_VBIT, i);
- break;
-
- case UnsignedSaturation:
- s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubU8);
- x = IwmmxtSaturateU8 (s, satrv + BITIDX8 (i));
- r |= (x & 0xff) << (i * 8);
- SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
- SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX8 (i)])
- {
- SIMD8_SET (psr, carry, SIMD_CBIT, i);
- SIMD8_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- case SignedSaturation:
- s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubS8);
- x = IwmmxtSaturateS8 (s, satrv + BITIDX8 (i));
- r |= (x & 0xff) << (i * 8);
- SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
- SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX8 (i)])
- {
- SIMD8_SET (psr, carry, SIMD_CBIT, i);
- SIMD8_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
- }
- break;
-
- case Hqual:
- satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0;
-
- for (i = 0; i < 4; i++)
- {
- switch (BITS (20, 21))
- {
- case NoSaturation:
- s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubU16);
- satrv [BITIDX16 (i)] = 0;
- r |= (s & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- SIMD16_SET (psr, carry, SIMD_CBIT, i);
- SIMD16_SET (psr, overflow, SIMD_VBIT, i);
- break;
-
- case UnsignedSaturation:
- s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubU16);
- x = IwmmxtSaturateU16 (s, satrv + BITIDX16 (i));
- r |= (x & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (x & 0xffff), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX16 (i)])
- {
- SIMD16_SET (psr, carry, SIMD_CBIT, i);
- SIMD16_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- case SignedSaturation:
- s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubS16);
- x = IwmmxtSaturateS16 (s, satrv + BITIDX16 (i));
- r |= (x & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX16 (i)])
- {
- SIMD16_SET (psr, carry, SIMD_CBIT, i);
- SIMD16_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
- }
- break;
-
- case Wqual:
- satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0;
-
- for (i = 0; i < 2; i++)
- {
- switch (BITS (20, 21))
- {
- case NoSaturation:
- s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubU32);
- satrv[BITIDX32 (i)] = 0;
- r |= (s & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- SIMD32_SET (psr, carry, SIMD_CBIT, i);
- SIMD32_SET (psr, overflow, SIMD_VBIT, i);
- break;
-
- case UnsignedSaturation:
- s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubU32);
- x = IwmmxtSaturateU32 (s, satrv + BITIDX32 (i));
- r |= (x & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX32 (i)])
- {
- SIMD32_SET (psr, carry, SIMD_CBIT, i);
- SIMD32_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- case SignedSaturation:
- s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubS32);
- x = IwmmxtSaturateS32 (s, satrv + BITIDX32 (i));
- r |= (x & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
- if (! satrv [BITIDX32 (i)])
- {
- SIMD32_SET (psr, carry, SIMD_CBIT, i);
- SIMD32_SET (psr, overflow, SIMD_VBIT, i);
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
- }
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wR [BITS (12, 15)] = r;
- wC [wCASF] = psr;
- SET_wCSSFvec (satrv);
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
-#undef SUBx
-
- return ARMul_DONE;
-}
-
-static int
-WUNPCKEH (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMword psr = 0;
- ARMdword s;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wunpckeh\n");
-#endif
-
- switch (BITS (22, 23))
- {
- case Bqual:
- for (i = 0; i < 4; i++)
- {
- s = wRBYTE (BITS (16, 19), i + 4);
-
- if (BIT (21) && NBIT8 (s))
- s |= 0xff00;
-
- r |= (s & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Hqual:
- for (i = 0; i < 2; i++)
- {
- s = wRHALF (BITS (16, 19), i + 2);
-
- if (BIT (21) && NBIT16 (s))
- s |= 0xffff0000;
-
- r |= (s & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Wqual:
- r = wRWORD (BITS (16, 19), 1);
-
- if (BIT (21) && NBIT32 (r))
- r |= 0xffffffff00000000ULL;
-
- SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
- SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WUNPCKEL (ARMul_State * state, ARMword instr)
-{
- ARMdword r = 0;
- ARMword psr = 0;
- ARMdword s;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wunpckel\n");
-#endif
-
- switch (BITS (22, 23))
- {
- case Bqual:
- for (i = 0; i < 4; i++)
- {
- s = wRBYTE (BITS (16, 19), i);
-
- if (BIT (21) && NBIT8 (s))
- s |= 0xff00;
-
- r |= (s & 0xffff) << (i * 16);
- SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
- SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Hqual:
- for (i = 0; i < 2; i++)
- {
- s = wRHALF (BITS (16, 19), i);
-
- if (BIT (21) && NBIT16 (s))
- s |= 0xffff0000;
-
- r |= (s & 0xffffffff) << (i * 32);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
- }
- break;
-
- case Wqual:
- r = wRWORD (BITS (16, 19), 0);
-
- if (BIT (21) && NBIT32 (r))
- r |= 0xffffffff00000000ULL;
-
- SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
- SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WUNPCKIH (ARMul_State * state, ARMword instr)
-{
- ARMword a, b;
- ARMdword r = 0;
- ARMword psr = 0;
- ARMdword s;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wunpckih\n");
-#endif
-
- switch (BITS (22, 23))
- {
- case Bqual:
- for (i = 0; i < 4; i++)
- {
- a = wRBYTE (BITS (16, 19), i + 4);
- b = wRBYTE (BITS ( 0, 3), i + 4);
- s = a | (b << 8);
- r |= (s & 0xffff) << (i * 16);
- SIMD8_SET (psr, NBIT8 (a), SIMD_NBIT, i * 2);
- SIMD8_SET (psr, ZBIT8 (a), SIMD_ZBIT, i * 2);
- SIMD8_SET (psr, NBIT8 (b), SIMD_NBIT, (i * 2) + 1);
- SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1);
- }
- break;
-
- case Hqual:
- for (i = 0; i < 2; i++)
- {
- a = wRHALF (BITS (16, 19), i + 2);
- b = wRHALF (BITS ( 0, 3), i + 2);
- s = a | (b << 16);
- r |= (s & 0xffffffff) << (i * 32);
- SIMD16_SET (psr, NBIT16 (a), SIMD_NBIT, (i * 2));
- SIMD16_SET (psr, ZBIT16 (a), SIMD_ZBIT, (i * 2));
- SIMD16_SET (psr, NBIT16 (b), SIMD_NBIT, (i * 2) + 1);
- SIMD16_SET (psr, ZBIT16 (b), SIMD_ZBIT, (i * 2) + 1);
- }
- break;
-
- case Wqual:
- a = wRWORD (BITS (16, 19), 1);
- s = wRWORD (BITS ( 0, 3), 1);
- r = a | (s << 32);
-
- SIMD32_SET (psr, NBIT32 (a), SIMD_NBIT, 0);
- SIMD32_SET (psr, ZBIT32 (a), SIMD_ZBIT, 0);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, 1);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, 1);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WUNPCKIL (ARMul_State * state, ARMword instr)
-{
- ARMword a, b;
- ARMdword r = 0;
- ARMword psr = 0;
- ARMdword s;
- int i;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wunpckil\n");
-#endif
-
- switch (BITS (22, 23))
- {
- case Bqual:
- for (i = 0; i < 4; i++)
- {
- a = wRBYTE (BITS (16, 19), i);
- b = wRBYTE (BITS ( 0, 3), i);
- s = a | (b << 8);
- r |= (s & 0xffff) << (i * 16);
- SIMD8_SET (psr, NBIT8 (a), SIMD_NBIT, i * 2);
- SIMD8_SET (psr, ZBIT8 (a), SIMD_ZBIT, i * 2);
- SIMD8_SET (psr, NBIT8 (b), SIMD_NBIT, (i * 2) + 1);
- SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1);
- }
- break;
-
- case Hqual:
- for (i = 0; i < 2; i++)
- {
- a = wRHALF (BITS (16, 19), i);
- b = wRHALF (BITS ( 0, 3), i);
- s = a | (b << 16);
- r |= (s & 0xffffffff) << (i * 32);
- SIMD16_SET (psr, NBIT16 (a), SIMD_NBIT, (i * 2));
- SIMD16_SET (psr, ZBIT16 (a), SIMD_ZBIT, (i * 2));
- SIMD16_SET (psr, NBIT16 (b), SIMD_NBIT, (i * 2) + 1);
- SIMD16_SET (psr, ZBIT16 (b), SIMD_ZBIT, (i * 2) + 1);
- }
- break;
-
- case Wqual:
- a = wRWORD (BITS (16, 19), 0);
- s = wRWORD (BITS ( 0, 3), 0);
- r = a | (s << 32);
-
- SIMD32_SET (psr, NBIT32 (a), SIMD_NBIT, 0);
- SIMD32_SET (psr, ZBIT32 (a), SIMD_ZBIT, 0);
- SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, 1);
- SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, 1);
- break;
-
- default:
- ARMul_UndefInstr (state, instr);
- return ARMul_DONE;
- }
-
- wC [wCASF] = psr;
- wR [BITS (12, 15)] = r;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-static int
-WXOR (ARMword instr)
-{
- ARMword psr = 0;
- ARMdword result;
-
- if ((read_cp15_reg (15, 0, 1) & 3) != 3)
- return ARMul_CANT;
-
-#ifdef DEBUG
- fprintf (stderr, "wxor\n");
-#endif
-
- result = wR [BITS (16, 19)] ^ wR [BITS (0, 3)];
- wR [BITS (12, 15)] = result;
-
- SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
- SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
-
- wC [wCASF] = psr;
- wC [wCon] |= (WCON_CUP | WCON_MUP);
-
- return ARMul_DONE;
-}
-
-/* This switch table is moved to a separate function in order
- to work around a compiler bug in the host compiler... */
-
-static int
-Process_Instruction (ARMul_State * state, ARMword instr)
-{
- int status = ARMul_BUSY;
-
- switch ((BITS (20, 23) << 8) | BITS (4, 11))
- {
- case 0x000: status = WOR (instr); break;
- case 0x011: status = TMCR (state, instr); break;
- case 0x100: status = WXOR (instr); break;
- case 0x111: status = TMRC (state, instr); break;
- case 0x300: status = WANDN (instr); break;
- case 0x200: status = WAND (instr); break;
-
- case 0x810: case 0xa10:
- status = WMADD (instr); break;
-
- case 0x10e: case 0x50e: case 0x90e: case 0xd0e:
- status = WUNPCKIL (state, instr); break;
- case 0x10c: case 0x50c: case 0x90c: case 0xd0c:
- status = WUNPCKIH (state, instr); break;
- case 0x012: case 0x112: case 0x412: case 0x512:
- status = WSAD (instr); break;
- case 0x010: case 0x110: case 0x210: case 0x310:
- status = WMUL (instr); break;
- case 0x410: case 0x510: case 0x610: case 0x710:
- status = WMAC (instr); break;
- case 0x006: case 0x406: case 0x806: case 0xc06:
- status = WCMPEQ (state, instr); break;
- case 0x800: case 0x900: case 0xc00: case 0xd00:
- status = WAVG2 (instr); break;
- case 0x802: case 0x902: case 0xa02: case 0xb02:
- status = WALIGNR (state, instr); break;
- case 0x601: case 0x605: case 0x609: case 0x60d:
- status = TINSR (state, instr); break;
- case 0x107: case 0x507: case 0x907: case 0xd07:
- status = TEXTRM (state, instr); break;
- case 0x117: case 0x517: case 0x917: case 0xd17:
- status = TEXTRC (state, instr); break;
- case 0x401: case 0x405: case 0x409: case 0x40d:
- status = TBCST (state, instr); break;
- case 0x113: case 0x513: case 0x913: case 0xd13:
- status = TANDC (state, instr); break;
- case 0x01c: case 0x41c: case 0x81c: case 0xc1c:
- status = WACC (state, instr); break;
- case 0x115: case 0x515: case 0x915: case 0xd15:
- status = TORC (state, instr); break;
- case 0x103: case 0x503: case 0x903: case 0xd03:
- status = TMOVMSK (state, instr); break;
- case 0x106: case 0x306: case 0x506: case 0x706:
- case 0x906: case 0xb06: case 0xd06: case 0xf06:
- status = WCMPGT (state, instr); break;
- case 0x00e: case 0x20e: case 0x40e: case 0x60e:
- case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
- status = WUNPCKEL (state, instr); break;
- case 0x00c: case 0x20c: case 0x40c: case 0x60c:
- case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
- status = WUNPCKEH (state, instr); break;
- case 0x204: case 0x604: case 0xa04: case 0xe04:
- case 0x214: case 0x614: case 0xa14: case 0xe14:
- status = WSRL (state, instr); break;
- case 0x004: case 0x404: case 0x804: case 0xc04:
- case 0x014: case 0x414: case 0x814: case 0xc14:
- status = WSRA (state, instr); break;
- case 0x104: case 0x504: case 0x904: case 0xd04:
- case 0x114: case 0x514: case 0x914: case 0xd14:
- status = WSLL (state, instr); break;
- case 0x304: case 0x704: case 0xb04: case 0xf04:
- case 0x314: case 0x714: case 0xb14: case 0xf14:
- status = WROR (state, instr); break;
- case 0x116: case 0x316: case 0x516: case 0x716:
- case 0x916: case 0xb16: case 0xd16: case 0xf16:
- status = WMIN (state, instr); break;
- case 0x016: case 0x216: case 0x416: case 0x616:
- case 0x816: case 0xa16: case 0xc16: case 0xe16:
- status = WMAX (state, instr); break;
- case 0x002: case 0x102: case 0x202: case 0x302:
- case 0x402: case 0x502: case 0x602: case 0x702:
- status = WALIGNI (instr); break;
- case 0x01a: case 0x11a: case 0x21a: case 0x31a:
- case 0x41a: case 0x51a: case 0x61a: case 0x71a:
- case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
- case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
- status = WSUB (state, instr); break;
- case 0x01e: case 0x11e: case 0x21e: case 0x31e:
- case 0x41e: case 0x51e: case 0x61e: case 0x71e:
- case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
- case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
- status = WSHUFH (instr); break;
- case 0x018: case 0x118: case 0x218: case 0x318:
- case 0x418: case 0x518: case 0x618: case 0x718:
- case 0x818: case 0x918: case 0xa18: case 0xb18:
- case 0xc18: case 0xd18: case 0xe18: case 0xf18:
- status = WADD (state, instr); break;
- case 0x008: case 0x108: case 0x208: case 0x308:
- case 0x408: case 0x508: case 0x608: case 0x708:
- case 0x808: case 0x908: case 0xa08: case 0xb08:
- case 0xc08: case 0xd08: case 0xe08: case 0xf08:
- status = WPACK (state, instr); break;
- case 0x201: case 0x203: case 0x205: case 0x207:
- case 0x209: case 0x20b: case 0x20d: case 0x20f:
- case 0x211: case 0x213: case 0x215: case 0x217:
- case 0x219: case 0x21b: case 0x21d: case 0x21f:
- switch (BITS (16, 19))
- {
- case 0x0: status = TMIA (state, instr); break;
- case 0x8: status = TMIAPH (state, instr); break;
- case 0xc:
- case 0xd:
- case 0xe:
- case 0xf: status = TMIAxy (state, instr); break;
- default: break;
- }
- break;
- default:
- break;
- }
- return status;
-}
-
-/* Process a possibly Intel(r) Wireless MMX(tm) technology instruction.
- Return true if the instruction was handled. */
-
-int
-ARMul_HandleIwmmxt (ARMul_State * state, ARMword instr)
-{
- int status = ARMul_BUSY;
-
- if (BITS (24, 27) == 0xe)
- {
- status = Process_Instruction (state, instr);
- }
- else if (BITS (25, 27) == 0x6)
- {
- if (BITS (4, 11) == 0x0 && BITS (20, 24) == 0x4)
- status = TMCRR (state, instr);
- else if (BITS (9, 11) == 0x0)
- {
- if (BIT (20) == 0x0)
- status = WSTR (state, instr);
- else if (BITS (20, 24) == 0x5)
- status = TMRRC (state, instr);
- else
- status = WLDR (state, instr);
- }
- }
-
- if (status == ARMul_CANT)
- {
- /* If the instruction was a recognised but illegal,
- perform the abort here rather than returning false.
- If we return false then ARMul_MRC may be called which
- will still abort, but which also perform the register
- transfer... */
- ARMul_Abort (state, ARMul_UndefinedInstrV);
- status = ARMul_DONE;
- }
-
- return status == ARMul_DONE;
-}
-
-int
-Fetch_Iwmmxt_Register (unsigned int regnum, unsigned char * memory)
-{
- if (regnum >= 16)
- {
- memcpy (memory, wC + (regnum - 16), sizeof wC [0]);
- return sizeof wC [0];
- }
- else
- {
- memcpy (memory, wR + regnum, sizeof wR [0]);
- return sizeof wR [0];
- }
-}
-
-int
-Store_Iwmmxt_Register (unsigned int regnum, const unsigned char * memory)
-{
- if (regnum >= 16)
- {
- memcpy (wC + (regnum - 16), memory, sizeof wC [0]);
- return sizeof wC [0];
- }
- else
- {
- memcpy (wR + regnum, memory, sizeof wR [0]);
- return sizeof wR [0];
- }
-}
+++ /dev/null
-/* iwmmxt.h -- Intel(r) Wireless MMX(tm) technology co-processor interface.
- Copyright (C) 2002-2024 Free Software Foundation, Inc.
- Contributed by matthew green (mrg@redhat.com).
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-extern unsigned IwmmxtLDC (ARMul_State *, unsigned, ARMword, ARMword);
-extern unsigned IwmmxtSTC (ARMul_State *, unsigned, ARMword, ARMword *);
-extern unsigned IwmmxtMCR (ARMul_State *, unsigned, ARMword, ARMword);
-extern unsigned IwmmxtMRC (ARMul_State *, unsigned, ARMword, ARMword *);
-extern unsigned IwmmxtCDP (ARMul_State *, unsigned, ARMword);
-
-extern int ARMul_HandleIwmmxt (ARMul_State *, ARMword);
-
-extern int Fetch_Iwmmxt_Register (unsigned int, unsigned char *);
-extern int Store_Iwmmxt_Register (unsigned int, const unsigned char *);
+++ /dev/null
-## See sim/Makefile.am
-##
-## Copyright (C) 1995-2024 Free Software Foundation, Inc.
-## Written by Cygnus Support.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 3 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program. If not, see <http://www.gnu.org/licenses/>.
-
-AM_CPPFLAGS_%C% = -DMODET
-
-nodist_%C%_libsim_a_SOURCES = \
- %D%/modules.c
-%C%_libsim_a_SOURCES = \
- $(common_libcommon_a_SOURCES)
-%C%_libsim_a_LIBADD = \
- %D%/wrapper.o \
- $(patsubst %,%D%/%,$(SIM_NEW_COMMON_OBJS)) \
- $(patsubst %,%D%/dv-%.o,$(SIM_HW_DEVICES)) \
- %D%/armemu.o \
- %D%/armemu32.o %D%/arminit.o %D%/armos.o %D%/armsupp.o \
- %D%/armvirt.o %D%/thumbemu.o \
- %D%/armcopro.o %D%/maverick.o %D%/iwmmxt.o
-$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h
-
-noinst_LIBRARIES += %D%/libsim.a
-
-## Override wildcards that trigger common/modules.c to be (incorrectly) used.
-%D%/modules.o: %D%/modules.c
-
-%D%/%.o: common/%.c ; $(SIM_COMPILE)
--@am__include@ %D%/$(DEPDIR)/*.Po
-
-%C%_run_SOURCES =
-%C%_run_LDADD = \
- %D%/nrun.o \
- %D%/libsim.a \
- $(SIM_COMMON_LIBS)
-
-noinst_PROGRAMS += %D%/run
-
-%C%docdir = $(docdir)/%C%
-%C%doc_DATA = %D%/README
+++ /dev/null
-/* maverick.c -- Cirrus/DSP co-processor interface.
- Copyright (C) 2003-2024 Free Software Foundation, Inc.
- Contributed by Aldy Hernandez (aldyh@redhat.com).
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-/* This must come before any other includes. */
-#include "defs.h"
-
-#include <assert.h>
-#include "armdefs.h"
-#include "ansidecl.h"
-#include "armemu.h"
-#include "maverick.h"
-
-/*#define CIRRUS_DEBUG 1 */
-#if CIRRUS_DEBUG
-# define printfdbg printf
-#else
-# define printfdbg printf_nothing
-#endif
-
-#define POS64(i) ( (~(i)) >> 63 )
-#define NEG64(i) ( (i) >> 63 )
-
-/* These variables are defined here and made extern in maverick.h for use
- in wrapper.c for now.
- Eventually the simulator should be made to handle any coprocessor at run
- time. */
-struct maverick_regs DSPregs[16];
-union maverick_acc_regs DSPacc[4];
-ARMword DSPsc;
-
-#define DEST_REG (BITS (12, 15))
-#define SRC1_REG (BITS (16, 19))
-#define SRC2_REG (BITS (0, 3))
-
-static int lsw_int_index, msw_int_index;
-static int lsw_float_index, msw_float_index;
-
-static double mv_getRegDouble (int);
-static long long mv_getReg64int (int);
-static void mv_setRegDouble (int, double val);
-static void mv_setReg64int (int, long long val);
-
-static union
-{
- double d;
- long long ll;
- int ints[2];
-} reg_conv;
-
-static void
-printf_nothing (void * foo, ...)
-{
-}
-
-static void
-cirrus_not_implemented (char * insn)
-{
- fprintf (stderr, "Cirrus instruction '%s' not implemented.\n", insn);
- fprintf (stderr, "aborting!\n");
-
- exit (1);
-}
-
-unsigned
-DSPMRC4 (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword * value)
-{
- switch (BITS (5, 7))
- {
- case 0: /* cfmvrdl */
- /* Move lower half of a DF stored in a DSP reg into an Arm reg. */
- printfdbg ("cfmvrdl\n");
- printfdbg ("\tlower half=0x%x\n", DSPregs[SRC1_REG].lower.i);
- printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG));
-
- *value = (ARMword) DSPregs[SRC1_REG].lower.i;
- break;
-
- case 1: /* cfmvrdh */
- /* Move upper half of a DF stored in a DSP reg into an Arm reg. */
- printfdbg ("cfmvrdh\n");
- printfdbg ("\tupper half=0x%x\n", DSPregs[SRC1_REG].upper.i);
- printfdbg ("\tentire thing=%g\n", mv_getRegDouble (SRC1_REG));
-
- *value = (ARMword) DSPregs[SRC1_REG].upper.i;
- break;
-
- case 2: /* cfmvrs */
- /* Move SF from upper half of a DSP register to an Arm register. */
- *value = (ARMword) DSPregs[SRC1_REG].upper.i;
- printfdbg ("cfmvrs = mvf%d <-- %f\n",
- SRC1_REG,
- DSPregs[SRC1_REG].upper.f);
- break;
-
-#ifdef doesnt_work
- case 4: /* cfcmps */
- {
- float a, b;
- int n, z, c, v;
-
- a = DSPregs[SRC1_REG].upper.f;
- b = DSPregs[SRC2_REG].upper.f;
-
- printfdbg ("cfcmps\n");
- printfdbg ("\tcomparing %f and %f\n", a, b);
-
- z = a == b; /* zero */
- n = a != b; /* negative */
- v = a > b; /* overflow */
- c = 0; /* carry */
- *value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
- break;
- }
-
- case 5: /* cfcmpd */
- {
- double a, b;
- int n, z, c, v;
-
- a = mv_getRegDouble (SRC1_REG);
- b = mv_getRegDouble (SRC2_REG);
-
- printfdbg ("cfcmpd\n");
- printfdbg ("\tcomparing %g and %g\n", a, b);
-
- z = a == b; /* zero */
- n = a != b; /* negative */
- v = a > b; /* overflow */
- c = 0; /* carry */
- *value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
- break;
- }
-#else
- case 4: /* cfcmps */
- {
- float a, b;
- int n, z, c, v;
-
- a = DSPregs[SRC1_REG].upper.f;
- b = DSPregs[SRC2_REG].upper.f;
-
- printfdbg ("cfcmps\n");
- printfdbg ("\tcomparing %f and %f\n", a, b);
-
- z = a == b; /* zero */
- n = a < b; /* negative */
- c = a > b; /* carry */
- v = 0; /* fixme */
- printfdbg ("\tz = %d, n = %d\n", z, n);
- *value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
- break;
- }
-
- case 5: /* cfcmpd */
- {
- double a, b;
- int n, z, c, v;
-
- a = mv_getRegDouble (SRC1_REG);
- b = mv_getRegDouble (SRC2_REG);
-
- printfdbg ("cfcmpd\n");
- printfdbg ("\tcomparing %g and %g\n", a, b);
-
- z = a == b; /* zero */
- n = a < b; /* negative */
- c = a > b; /* carry */
- v = 0; /* fixme */
- *value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
- break;
- }
-#endif
- default:
- fprintf (stderr, "unknown opcode in DSPMRC4 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPMRC5 (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword * value)
-{
- switch (BITS (5, 7))
- {
- case 0: /* cfmvr64l */
- /* Move lower half of 64bit int from Cirrus to Arm. */
- *value = (ARMword) DSPregs[SRC1_REG].lower.i;
- printfdbg ("cfmvr64l ARM_REG = mvfx%d <-- %d\n",
- DEST_REG,
- (int) *value);
- break;
-
- case 1: /* cfmvr64h */
- /* Move upper half of 64bit int from Cirrus to Arm. */
- *value = (ARMword) DSPregs[SRC1_REG].upper.i;
- printfdbg ("cfmvr64h <-- %d\n", (int) *value);
- break;
-
- case 4: /* cfcmp32 */
- {
- int res;
- int n, z, c, v;
- unsigned int a, b;
-
- printfdbg ("cfcmp32 mvfx%d - mvfx%d\n",
- SRC1_REG,
- SRC2_REG);
-
- /* FIXME: see comment for cfcmps. */
- a = DSPregs[SRC1_REG].lower.i;
- b = DSPregs[SRC2_REG].lower.i;
-
- res = DSPregs[SRC1_REG].lower.i - DSPregs[SRC2_REG].lower.i;
- /* zero */
- z = res == 0;
- /* negative */
- n = res < 0;
- /* overflow */
- v = SubOverflow (DSPregs[SRC1_REG].lower.i, DSPregs[SRC2_REG].lower.i,
- res);
- /* carry */
- c = (NEG (a) && POS (b))
- || (NEG (a) && POS (res))
- || (POS (b) && POS (res));
-
- *value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
- break;
- }
-
- case 5: /* cfcmp64 */
- {
- long long res;
- int n, z, c, v;
- unsigned long long a, b;
-
- printfdbg ("cfcmp64 mvdx%d - mvdx%d\n",
- SRC1_REG,
- SRC2_REG);
-
- /* fixme: see comment for cfcmps. */
-
- a = mv_getReg64int (SRC1_REG);
- b = mv_getReg64int (SRC2_REG);
-
- res = mv_getReg64int (SRC1_REG) - mv_getReg64int (SRC2_REG);
- /* zero */
- z = res == 0;
- /* negative */
- n = res < 0;
- /* overflow */
- v = ((NEG64 (a) && POS64 (b) && POS64 (res))
- || (POS64 (a) && NEG64 (b) && NEG64 (res)));
- /* carry */
- c = (NEG64 (a) && POS64 (b))
- || (NEG64 (a) && POS64 (res))
- || (POS64 (b) && POS64 (res));
-
- *value = (n << 31) | (z << 30) | (c << 29) | (v << 28);
- break;
- }
-
- default:
- fprintf (stderr, "unknown opcode in DSPMRC5 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPMRC6 (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword * value)
-{
- switch (BITS (5, 7))
- {
- case 0: /* cfmval32 */
- cirrus_not_implemented ("cfmval32");
- break;
-
- case 1: /* cfmvam32 */
- cirrus_not_implemented ("cfmvam32");
- break;
-
- case 2: /* cfmvah32 */
- cirrus_not_implemented ("cfmvah32");
- break;
-
- case 3: /* cfmva32 */
- cirrus_not_implemented ("cfmva32");
- break;
-
- case 4: /* cfmva64 */
- cirrus_not_implemented ("cfmva64");
- break;
-
- case 5: /* cfmvsc32 */
- cirrus_not_implemented ("cfmvsc32");
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPMRC6 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPMCR4 (ARMul_State * state,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword value)
-{
- switch (BITS (5, 7))
- {
- case 0: /* cfmvdlr */
- /* Move the lower half of a DF value from an Arm register into
- the lower half of a Cirrus register. */
- printfdbg ("cfmvdlr <-- 0x%x\n", (int) value);
- DSPregs[SRC1_REG].lower.i = (int) value;
- break;
-
- case 1: /* cfmvdhr */
- /* Move the upper half of a DF value from an Arm register into
- the upper half of a Cirrus register. */
- printfdbg ("cfmvdhr <-- 0x%x\n", (int) value);
- DSPregs[SRC1_REG].upper.i = (int) value;
- break;
-
- case 2: /* cfmvsr */
- /* Move SF from Arm register into upper half of Cirrus register. */
- printfdbg ("cfmvsr <-- 0x%x\n", (int) value);
- DSPregs[SRC1_REG].upper.i = (int) value;
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPMCR4 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPMCR5 (ARMul_State * state,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword value)
-{
- union
- {
- int s;
- unsigned int us;
- } val;
-
- switch (BITS (5, 7))
- {
- case 0: /* cfmv64lr */
- /* Move lower half of a 64bit int from an ARM register into the
- lower half of a DSP register and sign extend it. */
- printfdbg ("cfmv64lr mvdx%d <-- 0x%x\n", SRC1_REG, (int) value);
- DSPregs[SRC1_REG].lower.i = (int) value;
- break;
-
- case 1: /* cfmv64hr */
- /* Move upper half of a 64bit int from an ARM register into the
- upper half of a DSP register. */
- printfdbg ("cfmv64hr ARM_REG = mvfx%d <-- 0x%x\n",
- SRC1_REG,
- (int) value);
- DSPregs[SRC1_REG].upper.i = (int) value;
- break;
-
- case 2: /* cfrshl32 */
- printfdbg ("cfrshl32\n");
- val.us = value;
- if (val.s > 0)
- DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i << value;
- else
- DSPregs[SRC2_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -value;
- break;
-
- case 3: /* cfrshl64 */
- printfdbg ("cfrshl64\n");
- val.us = value;
- if (val.s > 0)
- mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) << value);
- else
- mv_setReg64int (SRC2_REG, mv_getReg64int (SRC1_REG) >> -value);
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPMCR5 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPMCR6 (ARMul_State * state,
- unsigned type ATTRIBUTE_UNUSED,
- ARMword instr,
- ARMword value)
-{
- switch (BITS (5, 7))
- {
- case 0: /* cfmv32al */
- cirrus_not_implemented ("cfmv32al");
- break;
-
- case 1: /* cfmv32am */
- cirrus_not_implemented ("cfmv32am");
- break;
-
- case 2: /* cfmv32ah */
- cirrus_not_implemented ("cfmv32ah");
- break;
-
- case 3: /* cfmv32a */
- cirrus_not_implemented ("cfmv32a");
- break;
-
- case 4: /* cfmv64a */
- cirrus_not_implemented ("cfmv64a");
- break;
-
- case 5: /* cfmv32sc */
- cirrus_not_implemented ("cfmv32sc");
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPMCR6 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPLDC4 (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type,
- ARMword instr,
- ARMword data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA)
- {
- words = 0;
- return ARMul_DONE;
- }
-
- if (BIT (22))
- { /* it's a long access, get two words */
- /* cfldrd */
-
- printfdbg ("cfldrd: %x (words = %d) (bigend = %d) DESTREG = %d\n",
- data, words, state->bigendSig, DEST_REG);
-
- if (words == 0)
- {
- if (state->bigendSig)
- DSPregs[DEST_REG].upper.i = (int) data;
- else
- DSPregs[DEST_REG].lower.i = (int) data;
- }
- else
- {
- if (state->bigendSig)
- DSPregs[DEST_REG].lower.i = (int) data;
- else
- DSPregs[DEST_REG].upper.i = (int) data;
- }
-
- ++ words;
-
- if (words == 2)
- {
- printfdbg ("\tmvd%d <-- mem = %g\n", DEST_REG,
- mv_getRegDouble (DEST_REG));
-
- return ARMul_DONE;
- }
- else
- return ARMul_INC;
- }
- else
- {
- /* Get just one word. */
-
- /* cfldrs */
- printfdbg ("cfldrs\n");
-
- DSPregs[DEST_REG].upper.i = (int) data;
-
- printfdbg ("\tmvf%d <-- mem = %f\n", DEST_REG,
- DSPregs[DEST_REG].upper.f);
-
- return ARMul_DONE;
- }
-}
-
-unsigned
-DSPLDC5 (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type,
- ARMword instr,
- ARMword data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA)
- {
- words = 0;
- return ARMul_DONE;
- }
-
- if (BIT (22))
- {
- /* It's a long access, get two words. */
-
- /* cfldr64 */
- printfdbg ("cfldr64: %d\n", data);
-
- if (words == 0)
- {
- if (state->bigendSig)
- DSPregs[DEST_REG].upper.i = (int) data;
- else
- DSPregs[DEST_REG].lower.i = (int) data;
- }
- else
- {
- if (state->bigendSig)
- DSPregs[DEST_REG].lower.i = (int) data;
- else
- DSPregs[DEST_REG].upper.i = (int) data;
- }
-
- ++ words;
-
- if (words == 2)
- {
- printfdbg ("\tmvdx%d <-- mem = %lld\n", DEST_REG,
- mv_getReg64int (DEST_REG));
-
- return ARMul_DONE;
- }
- else
- return ARMul_INC;
- }
- else
- {
- /* Get just one word. */
-
- /* cfldr32 */
- printfdbg ("cfldr32 mvfx%d <-- %d\n", DEST_REG, (int) data);
-
- /* 32bit ints should be sign extended to 64bits when loaded. */
- mv_setReg64int (DEST_REG, (long long) data);
-
- return ARMul_DONE;
- }
-}
-
-unsigned
-DSPSTC4 (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type,
- ARMword instr,
- ARMword * data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA)
- {
- words = 0;
- return ARMul_DONE;
- }
-
- if (BIT (22))
- {
- /* It's a long access, get two words. */
- /* cfstrd */
- printfdbg ("cfstrd\n");
-
- if (words == 0)
- {
- if (state->bigendSig)
- *data = (ARMword) DSPregs[DEST_REG].upper.i;
- else
- *data = (ARMword) DSPregs[DEST_REG].lower.i;
- }
- else
- {
- if (state->bigendSig)
- *data = (ARMword) DSPregs[DEST_REG].lower.i;
- else
- *data = (ARMword) DSPregs[DEST_REG].upper.i;
- }
-
- ++ words;
-
- if (words == 2)
- {
- printfdbg ("\tmem = mvd%d = %g\n", DEST_REG,
- mv_getRegDouble (DEST_REG));
-
- return ARMul_DONE;
- }
- else
- return ARMul_INC;
- }
- else
- {
- /* Get just one word. */
- /* cfstrs */
- printfdbg ("cfstrs mvf%d <-- %f\n", DEST_REG,
- DSPregs[DEST_REG].upper.f);
-
- *data = (ARMword) DSPregs[DEST_REG].upper.i;
-
- return ARMul_DONE;
- }
-}
-
-unsigned
-DSPSTC5 (ARMul_State * state ATTRIBUTE_UNUSED,
- unsigned type,
- ARMword instr,
- ARMword * data)
-{
- static unsigned words;
-
- if (type != ARMul_DATA)
- {
- words = 0;
- return ARMul_DONE;
- }
-
- if (BIT (22))
- {
- /* It's a long access, store two words. */
- /* cfstr64 */
- printfdbg ("cfstr64\n");
-
- if (words == 0)
- {
- if (state->bigendSig)
- *data = (ARMword) DSPregs[DEST_REG].upper.i;
- else
- *data = (ARMword) DSPregs[DEST_REG].lower.i;
- }
- else
- {
- if (state->bigendSig)
- *data = (ARMword) DSPregs[DEST_REG].lower.i;
- else
- *data = (ARMword) DSPregs[DEST_REG].upper.i;
- }
-
- ++ words;
-
- if (words == 2)
- {
- printfdbg ("\tmem = mvd%d = %lld\n", DEST_REG,
- mv_getReg64int (DEST_REG));
-
- return ARMul_DONE;
- }
- else
- return ARMul_INC;
- }
- else
- {
- /* Store just one word. */
- /* cfstr32 */
- *data = (ARMword) DSPregs[DEST_REG].lower.i;
-
- printfdbg ("cfstr32 MEM = %d\n", (int) *data);
-
- return ARMul_DONE;
- }
-}
-
-unsigned
-DSPCDP4 (ARMul_State * state,
- unsigned type,
- ARMword instr)
-{
- int opcode2;
-
- opcode2 = BITS (5,7);
-
- switch (BITS (20,21))
- {
- case 0:
- switch (opcode2)
- {
- case 0: /* cfcpys */
- printfdbg ("cfcpys mvf%d = mvf%d = %f\n",
- DEST_REG,
- SRC1_REG,
- DSPregs[SRC1_REG].upper.f);
- DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f;
- break;
-
- case 1: /* cfcpyd */
- printfdbg ("cfcpyd mvd%d = mvd%d = %g\n",
- DEST_REG,
- SRC1_REG,
- mv_getRegDouble (SRC1_REG));
- mv_setRegDouble (DEST_REG, mv_getRegDouble (SRC1_REG));
- break;
-
- case 2: /* cfcvtds */
- printfdbg ("cfcvtds mvf%d = (float) mvd%d = %f\n",
- DEST_REG,
- SRC1_REG,
- (float) mv_getRegDouble (SRC1_REG));
- DSPregs[DEST_REG].upper.f = (float) mv_getRegDouble (SRC1_REG);
- break;
-
- case 3: /* cfcvtsd */
- printfdbg ("cfcvtsd mvd%d = mvf%d = %g\n",
- DEST_REG,
- SRC1_REG,
- (double) DSPregs[SRC1_REG].upper.f);
- mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].upper.f);
- break;
-
- case 4: /* cfcvt32s */
- printfdbg ("cfcvt32s mvf%d = mvfx%d = %f\n",
- DEST_REG,
- SRC1_REG,
- (float) DSPregs[SRC1_REG].lower.i);
- DSPregs[DEST_REG].upper.f = (float) DSPregs[SRC1_REG].lower.i;
- break;
-
- case 5: /* cfcvt32d */
- printfdbg ("cfcvt32d mvd%d = mvfx%d = %g\n",
- DEST_REG,
- SRC1_REG,
- (double) DSPregs[SRC1_REG].lower.i);
- mv_setRegDouble (DEST_REG, (double) DSPregs[SRC1_REG].lower.i);
- break;
-
- case 6: /* cfcvt64s */
- printfdbg ("cfcvt64s mvf%d = mvdx%d = %f\n",
- DEST_REG,
- SRC1_REG,
- (float) mv_getReg64int (SRC1_REG));
- DSPregs[DEST_REG].upper.f = (float) mv_getReg64int (SRC1_REG);
- break;
-
- case 7: /* cfcvt64d */
- printfdbg ("cfcvt64d mvd%d = mvdx%d = %g\n",
- DEST_REG,
- SRC1_REG,
- (double) mv_getReg64int (SRC1_REG));
- mv_setRegDouble (DEST_REG, (double) mv_getReg64int (SRC1_REG));
- break;
- }
- break;
-
- case 1:
- switch (opcode2)
- {
- case 0: /* cfmuls */
- printfdbg ("cfmuls mvf%d = mvf%d = %f\n",
- DEST_REG,
- SRC1_REG,
- DSPregs[SRC1_REG].upper.f * DSPregs[SRC2_REG].upper.f);
-
- DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f
- * DSPregs[SRC2_REG].upper.f;
- break;
-
- case 1: /* cfmuld */
- printfdbg ("cfmuld mvd%d = mvd%d = %g\n",
- DEST_REG,
- SRC1_REG,
- mv_getRegDouble (SRC1_REG) * mv_getRegDouble (SRC2_REG));
-
- mv_setRegDouble (DEST_REG,
- mv_getRegDouble (SRC1_REG)
- * mv_getRegDouble (SRC2_REG));
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
- break;
-
- case 3:
- switch (opcode2)
- {
- case 0: /* cfabss */
- DSPregs[DEST_REG].upper.f = (DSPregs[SRC1_REG].upper.f < 0.0F ?
- -DSPregs[SRC1_REG].upper.f
- : DSPregs[SRC1_REG].upper.f);
- printfdbg ("cfabss mvf%d = |mvf%d| = %f\n",
- DEST_REG,
- SRC1_REG,
- DSPregs[DEST_REG].upper.f);
- break;
-
- case 1: /* cfabsd */
- mv_setRegDouble (DEST_REG,
- (mv_getRegDouble (SRC1_REG) < 0.0 ?
- -mv_getRegDouble (SRC1_REG)
- : mv_getRegDouble (SRC1_REG)));
- printfdbg ("cfabsd mvd%d = |mvd%d| = %g\n",
- DEST_REG,
- SRC1_REG,
- mv_getRegDouble (DEST_REG));
- break;
-
- case 2: /* cfnegs */
- DSPregs[DEST_REG].upper.f = -DSPregs[SRC1_REG].upper.f;
- printfdbg ("cfnegs mvf%d = -mvf%d = %f\n",
- DEST_REG,
- SRC1_REG,
- DSPregs[DEST_REG].upper.f);
- break;
-
- case 3: /* cfnegd */
- mv_setRegDouble (DEST_REG,
- -mv_getRegDouble (SRC1_REG));
- printfdbg ("cfnegd mvd%d = -mvd%d = %g\n",
- DEST_REG, DEST_REG,
- mv_getRegDouble (DEST_REG));
- break;
-
- case 4: /* cfadds */
- DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f
- + DSPregs[SRC2_REG].upper.f;
- printfdbg ("cfadds mvf%d = mvf%d + mvf%d = %f\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- DSPregs[DEST_REG].upper.f);
- break;
-
- case 5: /* cfaddd */
- mv_setRegDouble (DEST_REG,
- mv_getRegDouble (SRC1_REG)
- + mv_getRegDouble (SRC2_REG));
- printfdbg ("cfaddd: mvd%d = mvd%d + mvd%d = %g\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- mv_getRegDouble (DEST_REG));
- break;
-
- case 6: /* cfsubs */
- DSPregs[DEST_REG].upper.f = DSPregs[SRC1_REG].upper.f
- - DSPregs[SRC2_REG].upper.f;
- printfdbg ("cfsubs: mvf%d = mvf%d - mvf%d = %f\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- DSPregs[DEST_REG].upper.f);
- break;
-
- case 7: /* cfsubd */
- mv_setRegDouble (DEST_REG,
- mv_getRegDouble (SRC1_REG)
- - mv_getRegDouble (SRC2_REG));
- printfdbg ("cfsubd: mvd%d = mvd%d - mvd%d = %g\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- mv_getRegDouble (DEST_REG));
- break;
- }
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPCDP4 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPCDP5 (ARMul_State * state,
- unsigned type,
- ARMword instr)
-{
- int opcode2;
- char shift;
-
- opcode2 = BITS (5,7);
-
- /* Shift constants are 7bit signed numbers in bits 0..3|5..7. */
- shift = BITS (0, 3) | (BITS (5, 7)) << 4;
- if (shift & 0x40)
- shift |= 0xc0;
-
- switch (BITS (20,21))
- {
- case 0:
- /* cfsh32 */
- printfdbg ("cfsh32 %s amount=%d\n", shift < 0 ? "right" : "left",
- shift);
- if (shift < 0)
- /* Negative shift is a right shift. */
- DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i >> -shift;
- else
- /* Positive shift is a left shift. */
- DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i << shift;
- break;
-
- case 1:
- switch (opcode2)
- {
- case 0: /* cfmul32 */
- DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
- * DSPregs[SRC2_REG].lower.i;
- printfdbg ("cfmul32 mvfx%d = mvfx%d * mvfx%d = %d\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 1: /* cfmul64 */
- mv_setReg64int (DEST_REG,
- mv_getReg64int (SRC1_REG)
- * mv_getReg64int (SRC2_REG));
- printfdbg ("cfmul64 mvdx%d = mvdx%d * mvdx%d = %lld\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- mv_getReg64int (DEST_REG));
- break;
-
- case 2: /* cfmac32 */
- DSPregs[DEST_REG].lower.i
- += DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i;
- printfdbg ("cfmac32 mvfx%d += mvfx%d * mvfx%d = %d\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 3: /* cfmsc32 */
- DSPregs[DEST_REG].lower.i
- -= DSPregs[SRC1_REG].lower.i * DSPregs[SRC2_REG].lower.i;
- printfdbg ("cfmsc32 mvfx%d -= mvfx%d * mvfx%d = %d\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 4: /* cfcvts32 */
- /* fixme: this should round */
- DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f;
- printfdbg ("cfcvts32 mvfx%d = mvf%d = %d\n",
- DEST_REG,
- SRC1_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 5: /* cfcvtd32 */
- /* fixme: this should round */
- DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG);
- printfdbg ("cfcvtd32 mvdx%d = mvd%d = %d\n",
- DEST_REG,
- SRC1_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 6: /* cftruncs32 */
- DSPregs[DEST_REG].lower.i = (int) DSPregs[SRC1_REG].upper.f;
- printfdbg ("cftruncs32 mvfx%d = mvf%d = %d\n",
- DEST_REG,
- SRC1_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 7: /* cftruncd32 */
- DSPregs[DEST_REG].lower.i = (int) mv_getRegDouble (SRC1_REG);
- printfdbg ("cftruncd32 mvfx%d = mvd%d = %d\n",
- DEST_REG,
- SRC1_REG,
- DSPregs[DEST_REG].lower.i);
- break;
- }
- break;
-
- case 2:
- /* cfsh64 */
- printfdbg ("cfsh64\n");
-
- if (shift < 0)
- /* Negative shift is a right shift. */
- mv_setReg64int (DEST_REG,
- mv_getReg64int (SRC1_REG) >> -shift);
- else
- /* Positive shift is a left shift. */
- mv_setReg64int (DEST_REG,
- mv_getReg64int (SRC1_REG) << shift);
- printfdbg ("\t%llx\n", mv_getReg64int(DEST_REG));
- break;
-
- case 3:
- switch (opcode2)
- {
- case 0: /* cfabs32 */
- DSPregs[DEST_REG].lower.i = (DSPregs[SRC1_REG].lower.i < 0
- ? -DSPregs[SRC1_REG].lower.i : DSPregs[SRC1_REG].lower.i);
- printfdbg ("cfabs32 mvfx%d = |mvfx%d| = %d\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 1: /* cfabs64 */
- mv_setReg64int (DEST_REG,
- (mv_getReg64int (SRC1_REG) < 0
- ? -mv_getReg64int (SRC1_REG)
- : mv_getReg64int (SRC1_REG)));
- printfdbg ("cfabs64 mvdx%d = |mvdx%d| = %lld\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- mv_getReg64int (DEST_REG));
- break;
-
- case 2: /* cfneg32 */
- DSPregs[DEST_REG].lower.i = -DSPregs[SRC1_REG].lower.i;
- printfdbg ("cfneg32 mvfx%d = -mvfx%d = %d\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 3: /* cfneg64 */
- mv_setReg64int (DEST_REG, -mv_getReg64int (SRC1_REG));
- printfdbg ("cfneg64 mvdx%d = -mvdx%d = %lld\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- mv_getReg64int (DEST_REG));
- break;
-
- case 4: /* cfadd32 */
- DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
- + DSPregs[SRC2_REG].lower.i;
- printfdbg ("cfadd32 mvfx%d = mvfx%d + mvfx%d = %d\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 5: /* cfadd64 */
- mv_setReg64int (DEST_REG,
- mv_getReg64int (SRC1_REG)
- + mv_getReg64int (SRC2_REG));
- printfdbg ("cfadd64 mvdx%d = mvdx%d + mvdx%d = %lld\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- mv_getReg64int (DEST_REG));
- break;
-
- case 6: /* cfsub32 */
- DSPregs[DEST_REG].lower.i = DSPregs[SRC1_REG].lower.i
- - DSPregs[SRC2_REG].lower.i;
- printfdbg ("cfsub32 mvfx%d = mvfx%d - mvfx%d = %d\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- DSPregs[DEST_REG].lower.i);
- break;
-
- case 7: /* cfsub64 */
- mv_setReg64int (DEST_REG,
- mv_getReg64int (SRC1_REG)
- - mv_getReg64int (SRC2_REG));
- printfdbg ("cfsub64 mvdx%d = mvdx%d - mvdx%d = %d\n",
- DEST_REG,
- SRC1_REG,
- SRC2_REG,
- mv_getReg64int (DEST_REG));
- break;
- }
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPCDP5 0x%x\n", instr);
- cirrus_not_implemented ("unknown");
- break;
- }
-
- return ARMul_DONE;
-}
-
-unsigned
-DSPCDP6 (ARMul_State * state,
- unsigned type,
- ARMword instr)
-{
- switch (BITS (20,21))
- {
- case 0:
- /* cfmadd32 */
- cirrus_not_implemented ("cfmadd32");
- break;
-
- case 1:
- /* cfmsub32 */
- cirrus_not_implemented ("cfmsub32");
- break;
-
- case 2:
- /* cfmadda32 */
- cirrus_not_implemented ("cfmadda32");
- break;
-
- case 3:
- /* cfmsuba32 */
- cirrus_not_implemented ("cfmsuba32");
- break;
-
- default:
- fprintf (stderr, "unknown opcode in DSPCDP6 0x%x\n", instr);
- }
-
- return ARMul_DONE;
-}
-
-/* Conversion functions.
-
- 32-bit integers are stored in the LOWER half of a 64-bit physical
- register.
-
- Single precision floats are stored in the UPPER half of a 64-bit
- physical register. */
-
-static double
-mv_getRegDouble (int regnum)
-{
- reg_conv.ints[lsw_float_index] = DSPregs[regnum].upper.i;
- reg_conv.ints[msw_float_index] = DSPregs[regnum].lower.i;
- return reg_conv.d;
-}
-
-static void
-mv_setRegDouble (int regnum, double val)
-{
- reg_conv.d = val;
- DSPregs[regnum].upper.i = reg_conv.ints[lsw_float_index];
- DSPregs[regnum].lower.i = reg_conv.ints[msw_float_index];
-}
-
-static long long
-mv_getReg64int (int regnum)
-{
- reg_conv.ints[lsw_int_index] = DSPregs[regnum].lower.i;
- reg_conv.ints[msw_int_index] = DSPregs[regnum].upper.i;
- return reg_conv.ll;
-}
-
-static void
-mv_setReg64int (int regnum, long long val)
-{
- reg_conv.ll = val;
- DSPregs[regnum].lower.i = reg_conv.ints[lsw_int_index];
- DSPregs[regnum].upper.i = reg_conv.ints[msw_int_index];
-}
+++ /dev/null
-/* maverick.h -- Cirrus/DSP co-processor interface header
- Copyright (C) 2003-2024 Free Software Foundation, Inc.
- Contributed by Aldy Hernandez (aldyh@redhat.com).
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-/* Define Co-Processor instruction handlers here. */
-
-/* Here's ARMulator's DSP definition. A few things to note:
- 1) it has 16 64-bit registers and 4 72-bit accumulators
- 2) you can only access its registers with MCR and MRC. */
-
-struct maverick_regs
-{
- union
- {
- int i;
- float f;
- } upper;
-
- union
- {
- int i;
- float f;
- } lower;
-};
-
-union maverick_acc_regs
-{
- long double ld; /* Acc registers are 72-bits. */
-};
-
-extern struct maverick_regs DSPregs[16];
-extern union maverick_acc_regs DSPacc[4];
-extern ARMword DSPsc;
+++ /dev/null
-/* Simulation code for the ARM processor.
- Copyright (C) 2009-2024 Free Software Foundation, Inc.
-
- This file is part of simulators.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-#ifndef SIM_MAIN_H
-#define SIM_MAIN_H
-
-#include "sim-basics.h"
-#include "sim-base.h"
-
-#endif
+++ /dev/null
-/* thumbemu.c -- Thumb instruction emulation.
- Copyright (C) 1996, Cygnus Software Technologies Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* We can provide simple Thumb simulation by decoding the Thumb
-instruction into its corresponding ARM instruction, and using the
-existing ARM simulator. */
-
-/* This must come before any other includes. */
-#include "defs.h"
-
-#ifndef MODET /* required for the Thumb instruction support */
-#if 1
-#error "MODET needs to be defined for the Thumb world to work"
-#else
-#define MODET (1)
-#endif
-#endif
-
-#include "armdefs.h"
-#include "armemu.h"
-#include "armos.h"
-
-#define tBIT(n) ( (ARMword)(tinstr >> (n)) & 1)
-#define tBITS(m,n) ( (ARMword)(tinstr << (31 - (n))) >> ((31 - (n)) + (m)) )
-
-#define ntBIT(n) ( (ARMword)(next_instr >> (n)) & 1)
-#define ntBITS(m,n) ( (ARMword)(next_instr << (31 - (n))) >> ((31 - (n)) + (m)) )
-
-static int
-test_cond (int cond, ARMul_State * state)
-{
- switch (cond)
- {
- case EQ: return ZFLAG;
- case NE: return !ZFLAG;
- case VS: return VFLAG;
- case VC: return !VFLAG;
- case MI: return NFLAG;
- case PL: return !NFLAG;
- case CS: return CFLAG;
- case CC: return !CFLAG;
- case HI: return (CFLAG && !ZFLAG);
- case LS: return (!CFLAG || ZFLAG);
- case GE: return ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
- case LT: return ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
- case GT: return ((!NFLAG && !VFLAG && !ZFLAG)
- || (NFLAG && VFLAG && !ZFLAG));
- case LE: return ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
- case AL: return TRUE;
- case NV:
- default: return FALSE;
- }
-}
-
-static ARMword skipping_32bit_thumb = 0;
-
-static int IT_block_cond = AL;
-static ARMword IT_block_mask = 0;
-static int IT_block_first = FALSE;
-
-static void
-handle_IT_block (ARMul_State * state,
- ARMword tinstr,
- tdstate * pvalid)
-{
- * pvalid = t_branch;
- IT_block_mask = tBITS (0, 3);
-
- if (IT_block_mask == 0)
- // NOP or a HINT.
- return;
-
- IT_block_cond = tBITS (4, 7);
- IT_block_first = TRUE;
-}
-
-static int
-in_IT_block (void)
-{
- return IT_block_mask != 0;
-}
-
-static int
-IT_block_allow (ARMul_State * state)
-{
- int cond;
-
- if (IT_block_mask == 0)
- return TRUE;
-
- cond = IT_block_cond;
-
- if (IT_block_first)
- IT_block_first = FALSE;
- else
- {
- if ((IT_block_mask & 8) == 0)
- cond &= 0xe;
- else
- cond |= 1;
- IT_block_mask <<= 1;
- IT_block_mask &= 0xF;
- }
-
- if (IT_block_mask == 0x8)
- IT_block_mask = 0;
-
- return test_cond (cond, state);
-}
-
-static ARMword
-ThumbExpandImm (ARMword tinstr)
-{
- ARMword val;
-
- if (tBITS (10, 11) == 0)
- {
- switch (tBITS (8, 9))
- {
- case 0: val = tBITS (0, 7); break;
- case 1: val = tBITS (0, 7) << 8; break;
- case 2: val = (tBITS (0, 7) << 8) | (tBITS (0, 7) << 24); break;
- case 3: val = tBITS (0, 7) * 0x01010101; break;
- default: val = 0;
- }
- }
- else
- {
- int ror = tBITS (7, 11);
-
- val = (1 << 7) | tBITS (0, 6);
- val = (val >> ror) | (val << (32 - ror));
- }
-
- return val;
-}
-
-#define tASSERT(truth) \
- do \
- { \
- if (! (truth)) \
- { \
- fprintf (stderr, "unhandled T2 insn %04x|%04x detected at thumbemu.c:%d\n", \
- tinstr, next_instr, __LINE__); \
- return ; \
- } \
- } \
- while (0)
-
-
-/* Attempt to emulate a 32-bit ARMv7 Thumb instruction.
- Stores t_branch into PVALUE upon success or t_undefined otherwise. */
-
-static void
-handle_T2_insn (ARMul_State * state,
- ARMword tinstr,
- ARMword next_instr,
- ARMword pc,
- ARMword * ainstr,
- tdstate * pvalid)
-{
- * pvalid = t_undefined;
-
- if (! state->is_v6)
- return;
-
- if (trace)
- fprintf (stderr, "|%04x ", next_instr);
-
- if (tBITS (11, 15) == 0x1E && ntBIT (15) == 1)
- {
- ARMsword simm32 = 0;
- int S = tBIT (10);
-
- * pvalid = t_branch;
- switch ((ntBIT (14) << 1) | ntBIT (12))
- {
- case 0: /* B<c>.W */
- {
- ARMword cond = tBITS (6, 9);
- ARMword imm6;
- ARMword imm11;
- ARMword J1;
- ARMword J2;
-
- tASSERT (cond != AL && cond != NV);
- if (! test_cond (cond, state))
- return;
-
- imm6 = tBITS (0, 5);
- imm11 = ntBITS (0, 10);
- J1 = ntBIT (13);
- J2 = ntBIT (11);
-
- simm32 = (J1 << 19) | (J2 << 18) | (imm6 << 12) | (imm11 << 1);
- if (S)
- simm32 |= -(1 << 20);
- break;
- }
-
- case 1: /* B.W */
- {
- ARMword imm10 = tBITS (0, 9);
- ARMword imm11 = ntBITS (0, 10);
- ARMword I1 = (ntBIT (13) ^ S) ? 0 : 1;
- ARMword I2 = (ntBIT (11) ^ S) ? 0 : 1;
-
- simm32 = (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
- if (S)
- simm32 |= -(1 << 24);
- break;
- }
-
- case 2: /* BLX <label> */
- {
- ARMword imm10h = tBITS (0, 9);
- ARMword imm10l = ntBITS (1, 10);
- ARMword I1 = (ntBIT (13) ^ S) ? 0 : 1;
- ARMword I2 = (ntBIT (11) ^ S) ? 0 : 1;
-
- simm32 = (I1 << 23) | (I2 << 22) | (imm10h << 12) | (imm10l << 2);
- if (S)
- simm32 |= -(1 << 24);
-
- CLEART;
- state->Reg[14] = (pc + 4) | 1;
- break;
- }
-
- case 3: /* BL <label> */
- {
- ARMword imm10 = tBITS (0, 9);
- ARMword imm11 = ntBITS (0, 10);
- ARMword I1 = (ntBIT (13) ^ S) ? 0 : 1;
- ARMword I2 = (ntBIT (11) ^ S) ? 0 : 1;
-
- simm32 = (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
- if (S)
- simm32 |= -(1 << 24);
- state->Reg[14] = (pc + 4) | 1;
- break;
- }
- }
-
- state->Reg[15] = (pc + 4 + simm32);
- FLUSHPIPE;
- if (trace_funcs)
- fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
- return;
- }
-
- switch (tBITS (5,12))
- {
- case 0x29: // TST<c>.W <Rn>,<Rm>{,<shift>}
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rm = ntBITS (0, 3);
- ARMword type = ntBITS (4, 5);
- ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
-
- tASSERT (ntBITS (8, 11) == 0xF);
-
- * ainstr = 0xE1100000;
- * ainstr |= (Rn << 16);
- * ainstr |= (Rm);
- * ainstr |= (type << 5);
- * ainstr |= (imm5 << 7);
- * pvalid = t_decoded;
- break;
- }
-
- case 0x46:
- if (tBIT (4) && ntBITS (5, 15) == 0x780)
- {
- // Table Branch
- ARMword Rn = tBITS (0, 3);
- ARMword Rm = ntBITS (0, 3);
- ARMword address, dest;
-
- if (ntBIT (4))
- {
- // TBH
- address = state->Reg[Rn] + state->Reg[Rm] * 2;
- dest = ARMul_LoadHalfWord (state, address);
- }
- else
- {
- // TBB
- address = state->Reg[Rn] + state->Reg[Rm];
- dest = ARMul_LoadByte (state, address);
- }
-
- state->Reg[15] = (pc + 4 + dest * 2);
- FLUSHPIPE;
- * pvalid = t_branch;
- break;
- }
- ATTRIBUTE_FALLTHROUGH;
- case 0x42:
- case 0x43:
- case 0x47:
- case 0x4A:
- case 0x4B:
- case 0x4E: // STRD
- case 0x4F: // LDRD
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rt = ntBITS (12, 15);
- ARMword Rt2 = ntBITS (8, 11);
- ARMword imm8 = ntBITS (0, 7);
- ARMword P = tBIT (8);
- ARMword U = tBIT (7);
- ARMword W = tBIT (5);
-
- tASSERT (Rt2 == Rt + 1);
- imm8 <<= 2;
- tASSERT (imm8 <= 255);
- tASSERT (P != 0 || W != 0);
-
- // Convert into an ARM A1 encoding.
- if (Rn == 15)
- {
- tASSERT (tBIT (4) == 1);
- // LDRD (literal)
- // Ignore W even if 1.
- * ainstr = 0xE14F00D0;
- }
- else
- {
- if (tBIT (4) == 1)
- // LDRD (immediate)
- * ainstr = 0xE04000D0;
- else
- {
- // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
- // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8>
- // STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
- * ainstr = 0xE04000F0;
- }
- * ainstr |= (Rn << 16);
- * ainstr |= (P << 24);
- * ainstr |= (W << 21);
- }
-
- * ainstr |= (U << 23);
- * ainstr |= (Rt << 12);
- * ainstr |= ((imm8 << 4) & 0xF00);
- * ainstr |= (imm8 & 0xF);
- * pvalid = t_decoded;
- break;
- }
-
- case 0x44:
- case 0x45: // LDMIA
- {
- ARMword Rn = tBITS (0, 3);
- int W = tBIT (5);
- ARMword list = (ntBIT (15) << 15) | (ntBIT (14) << 14) | ntBITS (0, 12);
-
- if (Rn == 13)
- * ainstr = 0xE8BD0000;
- else
- {
- * ainstr = 0xE8900000;
- * ainstr |= (W << 21);
- * ainstr |= (Rn << 16);
- }
- * ainstr |= list;
- * pvalid = t_decoded;
- break;
- }
-
- case 0x48:
- case 0x49: // STMDB
- {
- ARMword Rn = tBITS (0, 3);
- int W = tBIT (5);
- ARMword list = (ntBIT (14) << 14) | ntBITS (0, 12);
-
- if (Rn == 13 && W)
- * ainstr = 0xE92D0000;
- else
- {
- * ainstr = 0xE9000000;
- * ainstr |= (W << 21);
- * ainstr |= (Rn << 16);
- }
- * ainstr |= list;
- * pvalid = t_decoded;
- break;
- }
-
- case 0x50:
- {
- ARMword Rd = ntBITS (8, 11);
- ARMword Rn = tBITS (0, 3);
- ARMword Rm = ntBITS (0, 3);
- ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
- ARMword type = ntBITS (4, 5);
-
- tASSERT (ntBIT (15) == 0);
-
- if (Rd == 15)
- {
- tASSERT (tBIT (4) == 1);
-
- // TST<c>.W <Rn>,<Rm>{,<shift>}
- * ainstr = 0xE1100000;
- }
- else
- {
- // AND{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
- int S = tBIT (4);
-
- * ainstr = 0xE0000000;
-
- if (in_IT_block ())
- S = 0;
- * ainstr |= (S << 20);
- }
-
- * ainstr |= (Rn << 16);
- * ainstr |= (imm5 << 7);
- * ainstr |= (type << 5);
- * ainstr |= (Rm << 0);
- * pvalid = t_decoded;
- break;
- }
-
- case 0x51: // BIC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
- {
- ARMword Rn = tBITS (0, 3);
- ARMword S = tBIT(4);
- ARMword Rm = ntBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
- ARMword type = ntBITS (4, 5);
-
- tASSERT (ntBIT (15) == 0);
-
- * ainstr = 0xE1C00000;
- * ainstr |= (S << 20);
- * ainstr |= (Rn << 16);
- * ainstr |= (Rd << 12);
- * ainstr |= (imm5 << 7);
- * ainstr |= (type << 5);
- * ainstr |= (Rm << 0);
- * pvalid = t_decoded;
- break;
- }
-
- case 0x52:
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword Rm = ntBITS (0, 3);
- int S = tBIT (4);
- ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
- ARMword type = ntBITS (4, 5);
-
- tASSERT (Rd != 15);
-
- if (in_IT_block ())
- S = 0;
-
- if (Rn == 15)
- {
- tASSERT (ntBIT (15) == 0);
-
- switch (ntBITS (4, 5))
- {
- case 0:
- // LSL{S}<c>.W <Rd>,<Rm>,#<imm5>
- * ainstr = 0xE1A00000;
- break;
- case 1:
- // LSR{S}<c>.W <Rd>,<Rm>,#<imm>
- * ainstr = 0xE1A00020;
- break;
- case 2:
- // ASR{S}<c>.W <Rd>,<Rm>,#<imm>
- * ainstr = 0xE1A00040;
- break;
- case 3:
- // ROR{S}<c> <Rd>,<Rm>,#<imm>
- * ainstr = 0xE1A00060;
- break;
- default:
- tASSERT (0);
- * ainstr = 0;
- }
- }
- else
- {
- // ORR{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
- * ainstr = 0xE1800000;
- * ainstr |= (Rn << 16);
- * ainstr |= (type << 5);
- }
-
- * ainstr |= (Rd << 12);
- * ainstr |= (S << 20);
- * ainstr |= (imm5 << 7);
- * ainstr |= (Rm << 0);
- * pvalid = t_decoded;
- break;
- }
-
- case 0x53: // MVN{S}<c>.W <Rd>,<Rm>{,<shift>}
- {
- ARMword Rd = ntBITS (8, 11);
- ARMword Rm = ntBITS (0, 3);
- int S = tBIT (4);
- ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
- ARMword type = ntBITS (4, 5);
-
- tASSERT (ntBIT (15) == 0);
-
- if (in_IT_block ())
- S = 0;
-
- * ainstr = 0xE1E00000;
- * ainstr |= (S << 20);
- * ainstr |= (Rd << 12);
- * ainstr |= (imm5 << 7);
- * ainstr |= (type << 5);
- * ainstr |= (Rm << 0);
- * pvalid = t_decoded;
- break;
- }
-
- case 0x54:
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword Rm = ntBITS (0, 3);
- int S = tBIT (4);
- ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
- ARMword type = ntBITS (4, 5);
-
- if (Rd == 15 && S)
- {
- // TEQ<c> <Rn>,<Rm>{,<shift>}
- tASSERT (ntBIT (15) == 0);
-
- * ainstr = 0xE1300000;
- }
- else
- {
- // EOR{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
- if (in_IT_block ())
- S = 0;
-
- * ainstr = 0xE0200000;
- * ainstr |= (S << 20);
- * ainstr |= (Rd << 8);
- }
-
- * ainstr |= (Rn << 16);
- * ainstr |= (imm5 << 7);
- * ainstr |= (type << 5);
- * ainstr |= (Rm << 0);
- * pvalid = t_decoded;
- break;
- }
-
- case 0x58: // ADD{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword Rm = ntBITS (0, 3);
- int S = tBIT (4);
- ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
- ARMword type = ntBITS (4, 5);
-
- tASSERT (! (Rd == 15 && S));
-
- if (in_IT_block ())
- S = 0;
-
- * ainstr = 0xE0800000;
- * ainstr |= (S << 20);
- * ainstr |= (Rn << 16);
- * ainstr |= (Rd << 12);
- * ainstr |= (imm5 << 7);
- * ainstr |= (type << 5);
- * ainstr |= Rm;
- * pvalid = t_decoded;
- break;
- }
-
- case 0x5A: // ADC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
- tASSERT (ntBIT (15) == 0);
- * ainstr = 0xE0A00000;
- if (! in_IT_block ())
- * ainstr |= (tBIT (4) << 20); // S
- * ainstr |= (tBITS (0, 3) << 16); // Rn
- * ainstr |= (ntBITS (8, 11) << 12); // Rd
- * ainstr |= ((ntBITS (12, 14) << 2) | ntBITS (6, 7)) << 7; // imm5
- * ainstr |= (ntBITS (4, 5) << 5); // type
- * ainstr |= ntBITS (0, 3); // Rm
- * pvalid = t_decoded;
- break;
-
- case 0x5B: // SBC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword Rm = ntBITS (0, 3);
- int S = tBIT (4);
- ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
- ARMword type = ntBITS (4, 5);
-
- tASSERT (ntBIT (15) == 0);
-
- if (in_IT_block ())
- S = 0;
-
- * ainstr = 0xE0C00000;
- * ainstr |= (S << 20);
- * ainstr |= (Rn << 16);
- * ainstr |= (Rd << 12);
- * ainstr |= (imm5 << 7);
- * ainstr |= (type << 5);
- * ainstr |= Rm;
- * pvalid = t_decoded;
- break;
- }
-
- case 0x5E: // RSB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}
- case 0x5D: // SUB{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword Rm = ntBITS (0, 3);
- ARMword S = tBIT (4);
- ARMword type = ntBITS (4, 5);
- ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
-
- tASSERT (ntBIT(15) == 0);
-
- if (Rd == 15)
- {
- // CMP<c>.W <Rn>, <Rm> {,<shift>}
- * ainstr = 0xE1500000;
- Rd = 0;
- }
- else if (tBIT (5))
- * ainstr = 0xE0400000;
- else
- * ainstr = 0xE0600000;
-
- * ainstr |= (S << 20);
- * ainstr |= (Rn << 16);
- * ainstr |= (Rd << 12);
- * ainstr |= (imm5 << 7);
- * ainstr |= (type << 5);
- * ainstr |= (Rm << 0);
- * pvalid = t_decoded;
- break;
- }
-
- case 0x9D: // NOP.W
- tASSERT (tBITS (0, 15) == 0xF3AF);
- tASSERT (ntBITS (0, 15) == 0x8000);
- * pvalid = t_branch;
- break;
-
- case 0x80: // AND
- case 0xA0: // TST
- {
- ARMword Rn = tBITS (0, 3);
- ARMword imm12 = (tBIT(10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
- ARMword Rd = ntBITS (8, 11);
- ARMword val;
- int S = tBIT (4);
-
- imm12 = ThumbExpandImm (imm12);
- val = state->Reg[Rn] & imm12;
-
- if (Rd == 15)
- {
- // TST<c> <Rn>,#<const>
- tASSERT (S == 1);
- }
- else
- {
- // AND{S}<c> <Rd>,<Rn>,#<const>
- if (in_IT_block ())
- S = 0;
-
- state->Reg[Rd] = val;
- }
-
- if (S)
- ARMul_NegZero (state, val);
- * pvalid = t_branch;
- break;
- }
-
- case 0xA1:
- case 0x81: // BIC.W
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword S = tBIT (4);
- ARMword imm8 = (ntBITS (12, 14) << 8) | ntBITS (0, 7);
-
- tASSERT (ntBIT (15) == 0);
-
- imm8 = ThumbExpandImm (imm8);
- state->Reg[Rd] = state->Reg[Rn] & ~ imm8;
-
- if (S && ! in_IT_block ())
- ARMul_NegZero (state, state->Reg[Rd]);
- * pvalid = t_resolved;
- break;
- }
-
- case 0xA2:
- case 0x82: // MOV{S}<c>.W <Rd>,#<const>
- {
- ARMword val = (tBIT(10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
- ARMword Rd = ntBITS (8, 11);
-
- val = ThumbExpandImm (val);
- state->Reg[Rd] = val;
-
- if (tBIT (4) && ! in_IT_block ())
- ARMul_NegZero (state, val);
- /* Indicate that the instruction has been processed. */
- * pvalid = t_branch;
- break;
- }
-
- case 0xA3:
- case 0x83: // MVN{S}<c> <Rd>,#<const>
- {
- ARMword val = (tBIT(10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
- ARMword Rd = ntBITS (8, 11);
-
- val = ThumbExpandImm (val);
- val = ~ val;
- state->Reg[Rd] = val;
-
- if (tBIT (4) && ! in_IT_block ())
- ARMul_NegZero (state, val);
- * pvalid = t_resolved;
- break;
- }
-
- case 0xA4: // EOR
- case 0x84: // TEQ
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword S = tBIT (4);
- ARMword imm12 = ((tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7));
- ARMword result;
-
- imm12 = ThumbExpandImm (imm12);
-
- result = state->Reg[Rn] ^ imm12;
-
- if (Rd == 15 && S)
- // TEQ<c> <Rn>,#<const>
- ;
- else
- {
- // EOR{S}<c> <Rd>,<Rn>,#<const>
- state->Reg[Rd] = result;
-
- if (in_IT_block ())
- S = 0;
- }
-
- if (S)
- ARMul_NegZero (state, result);
- * pvalid = t_resolved;
- break;
- }
-
- case 0xA8: // CMN
- case 0x88: // ADD
- {
- ARMword Rd = ntBITS (8, 11);
- int S = tBIT (4);
- ARMword Rn = tBITS (0, 3);
- ARMword lhs = state->Reg[Rn];
- ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
- ARMword rhs = ThumbExpandImm (imm12);
- ARMword res = lhs + rhs;
-
- if (Rd == 15 && S)
- {
- // CMN<c> <Rn>,#<const>
- res = lhs - rhs;
- }
- else
- {
- // ADD{S}<c>.W <Rd>,<Rn>,#<const>
- res = lhs + rhs;
-
- if (in_IT_block ())
- S = 0;
-
- state->Reg[Rd] = res;
- }
-
- if (S)
- {
- ARMul_NegZero (state, res);
-
- if ((lhs | rhs) >> 30)
- {
- /* Possible C,V,N to set. */
- ARMul_AddCarry (state, lhs, rhs, res);
- ARMul_AddOverflow (state, lhs, rhs, res);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- }
-
- * pvalid = t_branch;
- break;
- }
-
- case 0xAA:
- case 0x8A: // ADC{S}<c> <Rd>,<Rn>,#<const>
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- int S = tBIT (4);
- ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
- ARMword lhs = state->Reg[Rn];
- ARMword rhs = ThumbExpandImm (imm12);
- ARMword res;
-
- tASSERT (ntBIT (15) == 0);
-
- if (CFLAG)
- rhs += 1;
-
- res = lhs + rhs;
- state->Reg[Rd] = res;
-
- if (in_IT_block ())
- S = 0;
-
- if (S)
- {
- ARMul_NegZero (state, res);
-
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_AddCarry (state, lhs, rhs, res);
- ARMul_AddOverflow (state, lhs, rhs, res);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- }
-
- * pvalid = t_branch;
- break;
- }
-
- case 0xAB:
- case 0x8B: // SBC{S}<c> <Rd>,<Rn>,#<const>
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- int S = tBIT (4);
- ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
- ARMword lhs = state->Reg[Rn];
- ARMword rhs = ThumbExpandImm (imm12);
- ARMword res;
-
- tASSERT (ntBIT (15) == 0);
-
- if (! CFLAG)
- rhs += 1;
-
- res = lhs - rhs;
- state->Reg[Rd] = res;
-
- if (in_IT_block ())
- S = 0;
-
- if (S)
- {
- ARMul_NegZero (state, res);
-
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, res);
- ARMul_SubOverflow (state, lhs, rhs, res);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- }
-
- * pvalid = t_branch;
- break;
- }
-
- case 0xAD:
- case 0x8D: // SUB
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- int S = tBIT (4);
- ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
- ARMword lhs = state->Reg[Rn];
- ARMword rhs = ThumbExpandImm (imm12);
- ARMword res = lhs - rhs;
-
- if (Rd == 15 && S)
- {
- // CMP<c>.W <Rn>,#<const>
- tASSERT (S);
- }
- else
- {
- // SUB{S}<c>.W <Rd>,<Rn>,#<const>
- if (in_IT_block ())
- S = 0;
-
- state->Reg[Rd] = res;
- }
-
- if (S)
- {
- ARMul_NegZero (state, res);
-
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, res);
- ARMul_SubOverflow (state, lhs, rhs, res);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- }
-
- * pvalid = t_branch;
- break;
- }
-
- case 0xAE:
- case 0x8E: // RSB{S}<c>.W <Rd>,<Rn>,#<const>
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
- int S = tBIT (4);
- ARMword lhs = imm12;
- ARMword rhs = state->Reg[Rn];
- ARMword res = lhs - rhs;
-
- tASSERT (ntBIT (15) == 0);
-
- state->Reg[Rd] = res;
-
- if (S)
- {
- ARMul_NegZero (state, res);
-
- if ((lhs >= rhs) || ((rhs | lhs) >> 31))
- {
- ARMul_SubCarry (state, lhs, rhs, res);
- ARMul_SubOverflow (state, lhs, rhs, res);
- }
- else
- {
- CLEARC;
- CLEARV;
- }
- }
-
- * pvalid = t_branch;
- break;
- }
-
- case 0xB0:
- case 0x90: // ADDW<c> <Rd>,<Rn>,#<imm12>
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
-
- tASSERT (tBIT (4) == 0);
- tASSERT (ntBIT (15) == 0);
-
- state->Reg[Rd] = state->Reg[Rn] + imm12;
- * pvalid = t_branch;
- break;
- }
-
- case 0xB2:
- case 0x92: // MOVW<c> <Rd>,#<imm16>
- {
- ARMword Rd = ntBITS (8, 11);
- ARMword imm = (tBITS (0, 3) << 12) | (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
-
- state->Reg[Rd] = imm;
- /* Indicate that the instruction has been processed. */
- * pvalid = t_branch;
- break;
- }
-
- case 0xb5:
- case 0x95:// SUBW<c> <Rd>,<Rn>,#<imm12>
- {
- ARMword Rd = ntBITS (8, 11);
- ARMword Rn = tBITS (0, 3);
- ARMword imm12 = (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
-
- tASSERT (tBIT (4) == 0);
- tASSERT (ntBIT (15) == 0);
-
- /* Note the ARM ARM indicates special cases for Rn == 15 (ADR)
- and Rn == 13 (SUB SP minus immediate), but these are implemented
- in exactly the same way as the normal SUBW insn. */
- state->Reg[Rd] = state->Reg[Rn] - imm12;
-
- * pvalid = t_resolved;
- break;
- }
-
- case 0xB6:
- case 0x96: // MOVT<c> <Rd>,#<imm16>
- {
- ARMword Rd = ntBITS (8, 11);
- ARMword imm = (tBITS (0, 3) << 12) | (tBIT (10) << 11) | (ntBITS (12, 14) << 8) | ntBITS (0, 7);
-
- state->Reg[Rd] &= 0xFFFF;
- state->Reg[Rd] |= (imm << 16);
- * pvalid = t_resolved;
- break;
- }
-
- case 0x9A: // SBFXc> <Rd>,<Rn>,#<lsb>,#<width>
- tASSERT (tBIT (4) == 0);
- tASSERT (ntBIT (15) == 0);
- tASSERT (ntBIT (5) == 0);
- * ainstr = 0xE7A00050;
- * ainstr |= (ntBITS (0, 4) << 16); // widthm1
- * ainstr |= (ntBITS (8, 11) << 12); // Rd
- * ainstr |= (((ntBITS (12, 14) << 2) | ntBITS (6, 7)) << 7); // lsb
- * ainstr |= tBITS (0, 3); // Rn
- * pvalid = t_decoded;
- break;
-
- case 0x9B:
- {
- ARMword Rd = ntBITS (8, 11);
- ARMword Rn = tBITS (0, 3);
- ARMword msbit = ntBITS (0, 5);
- ARMword lsbit = (ntBITS (12, 14) << 2) | ntBITS (6, 7);
- ARMword mask = -(1 << lsbit);
-
- tASSERT (tBIT (4) == 0);
- tASSERT (ntBIT (15) == 0);
- tASSERT (ntBIT (5) == 0);
-
- mask &= ((1 << (msbit + 1)) - 1);
-
- if (lsbit > msbit)
- ; // UNPREDICTABLE
- else if (Rn == 15)
- {
- // BFC<c> <Rd>,#<lsb>,#<width>
- state->Reg[Rd] &= ~ mask;
- }
- else
- {
- // BFI<c> <Rd>,<Rn>,#<lsb>,#<width>
- ARMword val = state->Reg[Rn] & (mask >> lsbit);
-
- val <<= lsbit;
- state->Reg[Rd] &= ~ mask;
- state->Reg[Rd] |= val;
- }
-
- * pvalid = t_resolved;
- break;
- }
-
- case 0x9E: // UBFXc> <Rd>,<Rn>,#<lsb>,#<width>
- tASSERT (tBIT (4) == 0);
- tASSERT (ntBIT (15) == 0);
- tASSERT (ntBIT (5) == 0);
- * ainstr = 0xE7E00050;
- * ainstr |= (ntBITS (0, 4) << 16); // widthm1
- * ainstr |= (ntBITS (8, 11) << 12); // Rd
- * ainstr |= (((ntBITS (12, 14) << 2) | ntBITS (6, 7)) << 7); // lsb
- * ainstr |= tBITS (0, 3); // Rn
- * pvalid = t_decoded;
- break;
-
- case 0xC0: // STRB
- case 0xC4: // LDRB
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rt = ntBITS (12, 15);
-
- if (tBIT (4))
- {
- if (Rn == 15)
- {
- tASSERT (Rt != 15);
-
- /* LDRB<c> <Rt>,<label> => 1111 1000 U001 1111 */
- * ainstr = 0xE55F0000;
- * ainstr |= (tBIT (7) << 23);
- * ainstr |= ntBITS (0, 11);
- }
- else if (tBIT (7))
- {
- /* LDRB<c>.W <Rt>,[<Rn>{,#<imm12>}] => 1111 1000 1001 rrrr */
- * ainstr = 0xE5D00000;
- * ainstr |= ntBITS (0, 11);
- }
- else if (ntBIT (11) == 0)
- {
- /* LDRB<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}] => 1111 1000 0001 rrrr */
- * ainstr = 0xE7D00000;
- * ainstr |= (ntBITS (4, 5) << 7);
- * ainstr |= ntBITS (0, 3);
- }
- else
- {
- int P = ntBIT (10);
- int U = ntBIT (9);
- int W = ntBIT (8);
-
- tASSERT (! (Rt == 15 && P && !U && !W));
- tASSERT (! (P && U && !W));
-
- /* LDRB<c> <Rt>,[<Rn>,#-<imm8>] => 1111 1000 0001 rrrr
- LDRB<c> <Rt>,[<Rn>],#+/-<imm8> => 1111 1000 0001 rrrr
- LDRB<c> <Rt>,[<Rn>,#+/-<imm8>]! => 1111 1000 0001 rrrr */
- * ainstr = 0xE4500000;
- * ainstr |= (P << 24);
- * ainstr |= (U << 23);
- * ainstr |= (W << 21);
- * ainstr |= ntBITS (0, 7);
- }
- }
- else
- {
- if (tBIT (7) == 1)
- {
- // STRB<c>.W <Rt>,[<Rn>,#<imm12>]
- ARMword imm12 = ntBITS (0, 11);
-
- ARMul_StoreByte (state, state->Reg[Rn] + imm12, state->Reg [Rt]);
- * pvalid = t_branch;
- break;
- }
- else if (ntBIT (11))
- {
- // STRB<c> <Rt>,[<Rn>,#-<imm8>]
- // STRB<c> <Rt>,[<Rn>],#+/-<imm8>
- // STRB<c> <Rt>,[<Rn>,#+/-<imm8>]!
- int P = ntBIT (10);
- int U = ntBIT (9);
- int W = ntBIT (8);
- ARMword imm8 = ntBITS (0, 7);
-
- tASSERT (! (P && U && !W));
- tASSERT (! (Rn == 13 && P && !U && W && imm8 == 4));
-
- * ainstr = 0xE4000000;
- * ainstr |= (P << 24);
- * ainstr |= (U << 23);
- * ainstr |= (W << 21);
- * ainstr |= imm8;
- }
- else
- {
- // STRB<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
- tASSERT (ntBITS (6, 11) == 0);
-
- * ainstr = 0xE7C00000;
- * ainstr |= (ntBITS (4, 5) << 7);
- * ainstr |= ntBITS (0, 3);
- }
- }
-
- * ainstr |= (Rn << 16);
- * ainstr |= (Rt << 12);
- * pvalid = t_decoded;
- break;
- }
-
- case 0xC2: // LDR, STR
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rt = ntBITS (12, 15);
- ARMword imm8 = ntBITS (0, 7);
- ARMword P = ntBIT (10);
- ARMword U = ntBIT (9);
- ARMword W = ntBIT (8);
-
- tASSERT (Rn != 15);
-
- if (tBIT (4))
- {
- if (Rn == 15)
- {
- // LDR<c>.W <Rt>,<label>
- * ainstr = 0xE51F0000;
- * ainstr |= ntBITS (0, 11);
- }
- else if (ntBIT (11))
- {
- tASSERT (! (P && U && ! W));
- tASSERT (! (!P && U && W && Rn == 13 && imm8 == 4 && ntBIT (11) == 0));
- tASSERT (! (P && !U && W && Rn == 13 && imm8 == 4 && ntBIT (11)));
-
- // LDR<c> <Rt>,[<Rn>,#-<imm8>]
- // LDR<c> <Rt>,[<Rn>],#+/-<imm8>
- // LDR<c> <Rt>,[<Rn>,#+/-<imm8>]!
- if (!P && W)
- W = 0;
- * ainstr = 0xE4100000;
- * ainstr |= (P << 24);
- * ainstr |= (U << 23);
- * ainstr |= (W << 21);
- * ainstr |= imm8;
- }
- else
- {
- // LDR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
-
- tASSERT (ntBITS (6, 11) == 0);
-
- * ainstr = 0xE7900000;
- * ainstr |= ntBITS (4, 5) << 7;
- * ainstr |= ntBITS (0, 3);
- }
- }
- else
- {
- if (ntBIT (11))
- {
- tASSERT (! (P && U && ! W));
- if (Rn == 13 && P && !U && W && imm8 == 4)
- {
- // PUSH<c>.W <register>
- tASSERT (ntBITS (0, 11) == 0xD04);
- tASSERT (tBITS (0, 4) == 0x0D);
-
- * ainstr = 0xE92D0000;
- * ainstr |= (1 << Rt);
-
- Rt = Rn = 0;
- }
- else
- {
- tASSERT (! (P && U && !W));
- if (!P && W)
- W = 0;
- // STR<c> <Rt>,[<Rn>,#-<imm8>]
- // STR<c> <Rt>,[<Rn>],#+/-<imm8>
- // STR<c> <Rt>,[<Rn>,#+/-<imm8>]!
- * ainstr = 0xE4000000;
- * ainstr |= (P << 24);
- * ainstr |= (U << 23);
- * ainstr |= (W << 21);
- * ainstr |= imm8;
- }
- }
- else
- {
- // STR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
- tASSERT (ntBITS (6, 11) == 0);
-
- * ainstr = 0xE7800000;
- * ainstr |= ntBITS (4, 5) << 7;
- * ainstr |= ntBITS (0, 3);
- }
- }
-
- * ainstr |= (Rn << 16);
- * ainstr |= (Rt << 12);
- * pvalid = t_decoded;
- break;
- }
-
- case 0xC1: // STRH
- case 0xC5: // LDRH
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rt = ntBITS (12, 15);
- ARMword address;
-
- tASSERT (Rn != 15);
-
- if (tBIT (4) == 1)
- {
- if (tBIT (7))
- {
- // LDRH<c>.W <Rt>,[<Rn>{,#<imm12>}]
- ARMword imm12 = ntBITS (0, 11);
- address = state->Reg[Rn] + imm12;
- }
- else if (ntBIT (11))
- {
- // LDRH<c> <Rt>,[<Rn>,#-<imm8>]
- // LDRH<c> <Rt>,[<Rn>],#+/-<imm8>
- // LDRH<c> <Rt>,[<Rn>,#+/-<imm8>]!
- ARMword P = ntBIT (10);
- ARMword U = ntBIT (9);
- ARMword W = ntBIT (8);
- ARMword imm8 = ntBITS (0, 7);
-
- tASSERT (Rn != 15);
- tASSERT (! (P && U && !W));
-
- * ainstr = 0xE05000B0;
- * ainstr |= (P << 24);
- * ainstr |= (U << 23);
- * ainstr |= (W << 21);
- * ainstr |= (Rn << 16);
- * ainstr |= (Rt << 12);
- * ainstr |= ((imm8 & 0xF0) << 4);
- * ainstr |= (imm8 & 0xF);
- * pvalid = t_decoded;
- break;
- }
- else
- {
- // LDRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
- ARMword Rm = ntBITS (0, 3);
- ARMword imm2 = ntBITS (4, 5);
-
- tASSERT (ntBITS (6, 10) == 0);
-
- address = state->Reg[Rn] + (state->Reg[Rm] << imm2);
- }
-
- state->Reg[Rt] = ARMul_LoadHalfWord (state, address);
- }
- else
- {
- if (tBIT (7))
- {
- // STRH<c>.W <Rt>,[<Rn>{,#<imm12>}]
- ARMword imm12 = ntBITS (0, 11);
-
- address = state->Reg[Rn] + imm12;
- }
- else if (ntBIT (11))
- {
- // STRH<c> <Rt>,[<Rn>,#-<imm8>]
- // STRH<c> <Rt>,[<Rn>],#+/-<imm8>
- // STRH<c> <Rt>,[<Rn>,#+/-<imm8>]!
- ARMword P = ntBIT (10);
- ARMword U = ntBIT (9);
- ARMword W = ntBIT (8);
- ARMword imm8 = ntBITS (0, 7);
-
- tASSERT (! (P && U && !W));
-
- * ainstr = 0xE04000B0;
- * ainstr |= (P << 24);
- * ainstr |= (U << 23);
- * ainstr |= (W << 21);
- * ainstr |= (Rn << 16);
- * ainstr |= (Rt << 12);
- * ainstr |= ((imm8 & 0xF0) << 4);
- * ainstr |= (imm8 & 0xF);
- * pvalid = t_decoded;
- break;
- }
- else
- {
- // STRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
- ARMword Rm = ntBITS (0, 3);
- ARMword imm2 = ntBITS (4, 5);
-
- tASSERT (ntBITS (6, 10) == 0);
-
- address = state->Reg[Rn] + (state->Reg[Rm] << imm2);
- }
-
- ARMul_StoreHalfWord (state, address, state->Reg [Rt]);
- }
- * pvalid = t_branch;
- break;
- }
-
- case 0xC6: // LDR.W/STR.W
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rt = ntBITS (12, 15);
- ARMword imm12 = ntBITS (0, 11);
- ARMword address = state->Reg[Rn];
-
- if (Rn == 15)
- {
- // LDR<c>.W <Rt>,<label>
- tASSERT (tBIT (4) == 1);
- // tASSERT (tBIT (7) == 1)
- }
-
- address += imm12;
- if (tBIT (4) == 1)
- state->Reg[Rt] = ARMul_LoadWordN (state, address);
- else
- ARMul_StoreWordN (state, address, state->Reg [Rt]);
-
- * pvalid = t_resolved;
- break;
- }
-
- case 0xC8:
- case 0xCC: // LDRSB
- {
- ARMword Rt = ntBITS (12, 15);
- ARMword Rn = tBITS (0, 3);
- ARMword U = tBIT (7);
- ARMword address = state->Reg[Rn];
-
- tASSERT (tBIT (4) == 1);
- tASSERT (Rt != 15); // PLI
-
- if (Rn == 15)
- {
- // LDRSB<c> <Rt>,<label>
- ARMword imm12 = ntBITS (0, 11);
- address += (U ? imm12 : - imm12);
- }
- else if (U)
- {
- // LDRSB<c> <Rt>,[<Rn>,#<imm12>]
- ARMword imm12 = ntBITS (0, 11);
- address += imm12;
- }
- else if (ntBIT (11))
- {
- // LDRSB<c> <Rt>,[<Rn>,#-<imm8>]
- // LDRSB<c> <Rt>,[<Rn>],#+/-<imm8>
- // LDRSB<c> <Rt>,[<Rn>,#+/-<imm8>]!
- * ainstr = 0xE05000D0;
- * ainstr |= ntBIT (10) << 24; // P
- * ainstr |= ntBIT (9) << 23; // U
- * ainstr |= ntBIT (8) << 21; // W
- * ainstr |= Rn << 16;
- * ainstr |= Rt << 12;
- * ainstr |= ntBITS (4, 7) << 8;
- * ainstr |= ntBITS (0, 3);
- * pvalid = t_decoded;
- break;
- }
- else
- {
- // LDRSB<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
- ARMword Rm = ntBITS (0, 3);
- ARMword imm2 = ntBITS (4,5);
-
- tASSERT (ntBITS (6, 11) == 0);
-
- address += (state->Reg[Rm] << imm2);
- }
-
- state->Reg[Rt] = ARMul_LoadByte (state, address);
- if (state->Reg[Rt] & 0x80)
- state->Reg[Rt] |= -(1 << 8);
-
- * pvalid = t_resolved;
- break;
- }
-
- case 0xC9:
- case 0xCD:// LDRSH
- {
- ARMword Rt = ntBITS (12, 15);
- ARMword Rn = tBITS (0, 3);
- ARMword U = tBIT (7);
- ARMword address = state->Reg[Rn];
-
- tASSERT (tBIT (4) == 1);
-
- if (Rn == 15 || U == 1)
- {
- // Rn==15 => LDRSH<c> <Rt>,<label>
- // Rn!=15 => LDRSH<c> <Rt>,[<Rn>,#<imm12>]
- ARMword imm12 = ntBITS (0, 11);
-
- address += (U ? imm12 : - imm12);
- }
- else if (ntBIT (11))
- {
- // LDRSH<c> <Rt>,[<Rn>,#-<imm8>]
- // LDRSH<c> <Rt>,[<Rn>],#+/-<imm8>
- // LDRSH<c> <Rt>,[<Rn>,#+/-<imm8>]!
- * ainstr = 0xE05000F0;
- * ainstr |= ntBIT (10) << 24; // P
- * ainstr |= ntBIT (9) << 23; // U
- * ainstr |= ntBIT (8) << 21; // W
- * ainstr |= Rn << 16;
- * ainstr |= Rt << 12;
- * ainstr |= ntBITS (4, 7) << 8;
- * ainstr |= ntBITS (0, 3);
- * pvalid = t_decoded;
- break;
- }
- else /* U == 0 */
- {
- // LDRSH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
- ARMword Rm = ntBITS (0, 3);
- ARMword imm2 = ntBITS (4,5);
-
- tASSERT (ntBITS (6, 11) == 0);
-
- address += (state->Reg[Rm] << imm2);
- }
-
- state->Reg[Rt] = ARMul_LoadHalfWord (state, address);
- if (state->Reg[Rt] & 0x8000)
- state->Reg[Rt] |= -(1 << 16);
-
- * pvalid = t_branch;
- break;
- }
-
- case 0x0D0:
- {
- ARMword Rm = ntBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
-
- tASSERT (ntBITS (12, 15) == 15);
-
- if (ntBIT (7) == 1)
- {
- // SXTH<c>.W <Rd>,<Rm>{,<rotation>}
- ARMword ror = ntBITS (4, 5) << 3;
- ARMword val;
-
- val = state->Reg[Rm];
- val = (val >> ror) | (val << (32 - ror));
- if (val & 0x8000)
- val |= -(1 << 16);
- state->Reg[Rd] = val;
- }
- else
- {
- // LSL{S}<c>.W <Rd>,<Rn>,<Rm>
- ARMword Rn = tBITS (0, 3);
-
- tASSERT (ntBITS (4, 6) == 0);
-
- state->Reg[Rd] = state->Reg[Rn] << (state->Reg[Rm] & 0xFF);
- if (tBIT (4))
- ARMul_NegZero (state, state->Reg[Rd]);
- }
- * pvalid = t_branch;
- break;
- }
-
- case 0x0D1: // LSR{S}<c>.W <Rd>,<Rn>,<Rm>
- {
- ARMword Rd = ntBITS (8, 11);
- ARMword Rn = tBITS (0, 3);
- ARMword Rm = ntBITS (0, 3);
-
- tASSERT (ntBITS (12, 15) == 15);
- tASSERT (ntBITS (4, 7) == 0);
-
- state->Reg[Rd] = state->Reg[Rn] >> (state->Reg[Rm] & 0xFF);
- if (tBIT (4))
- ARMul_NegZero (state, state->Reg[Rd]);
- * pvalid = t_resolved;
- break;
- }
-
- case 0xD2:
- tASSERT (ntBITS (12, 15) == 15);
- if (ntBIT (7))
- {
- tASSERT (ntBIT (6) == 0);
- // UXTB<c>.W <Rd>,<Rm>{,<rotation>}
- * ainstr = 0xE6EF0070;
- * ainstr |= (ntBITS (4, 5) << 10); // rotate
- * ainstr |= ntBITS (0, 3); // Rm
- }
- else
- {
- // ASR{S}<c>.W <Rd>,<Rn>,<Rm>
- tASSERT (ntBITS (4, 7) == 0);
- * ainstr = 0xE1A00050;
- if (! in_IT_block ())
- * ainstr |= (tBIT (4) << 20);
- * ainstr |= (ntBITS (0, 3) << 8); // Rm
- * ainstr |= tBITS (0, 3); // Rn
- }
-
- * ainstr |= (ntBITS (8, 11) << 12); // Rd
- * pvalid = t_decoded;
- break;
-
- case 0xD3: // ROR{S}<c>.W <Rd>,<Rn>,<Rm>
- tASSERT (ntBITS (12, 15) == 15);
- tASSERT (ntBITS (4, 7) == 0);
- * ainstr = 0xE1A00070;
- if (! in_IT_block ())
- * ainstr |= (tBIT (4) << 20);
- * ainstr |= (ntBITS (8, 11) << 12); // Rd
- * ainstr |= (ntBITS (0, 3) << 8); // Rm
- * ainstr |= (tBITS (0, 3) << 0); // Rn
- * pvalid = t_decoded;
- break;
-
- case 0xD4:
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword Rm = ntBITS (0, 3);
-
- tASSERT (ntBITS (12, 15) == 15);
-
- if (ntBITS (4, 7) == 8)
- {
- // REV<c>.W <Rd>,<Rm>
- ARMword val = state->Reg[Rm];
-
- tASSERT (Rm == Rn);
-
- state->Reg [Rd] =
- (val >> 24)
- | ((val >> 8) & 0xFF00)
- | ((val << 8) & 0xFF0000)
- | (val << 24);
- * pvalid = t_resolved;
- }
- else
- {
- tASSERT (ntBITS (4, 7) == 4);
-
- if (tBIT (4) == 1)
- // UADD8<c> <Rd>,<Rn>,<Rm>
- * ainstr = 0xE6500F10;
- else
- // UADD16<c> <Rd>,<Rn>,<Rm>
- * ainstr = 0xE6500F90;
-
- * ainstr |= (Rn << 16);
- * ainstr |= (Rd << 12);
- * ainstr |= (Rm << 0);
- * pvalid = t_decoded;
- }
- break;
- }
-
- case 0xD5:
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword Rm = ntBITS (0, 3);
-
- tASSERT (ntBITS (12, 15) == 15);
- tASSERT (ntBITS (4, 7) == 8);
-
- if (tBIT (4))
- {
- // CLZ<c> <Rd>,<Rm>
- tASSERT (Rm == Rn);
- * ainstr = 0xE16F0F10;
- }
- else
- {
- // SEL<c> <Rd>,<Rn>,<Rm>
- * ainstr = 0xE6800FB0;
- * ainstr |= (Rn << 16);
- }
-
- * ainstr |= (Rd << 12);
- * ainstr |= (Rm << 0);
- * pvalid = t_decoded;
- break;
- }
-
- case 0xD8: // MUL
- {
- ARMword Rn = tBITS (0, 3);
- ARMword Rm = ntBITS (0, 3);
- ARMword Rd = ntBITS (8, 11);
- ARMword Ra = ntBITS (12, 15);
-
- if (tBIT (4))
- {
- // SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
- ARMword nval = state->Reg[Rn];
- ARMword mval = state->Reg[Rm];
- ARMword res;
-
- tASSERT (ntBITS (6, 7) == 0);
- tASSERT (Ra != 15);
-
- if (ntBIT (5))
- nval >>= 16;
- else
- nval &= 0xFFFF;
-
- if (ntBIT (4))
- mval >>= 16;
- else
- mval &= 0xFFFF;
-
- res = nval * mval;
- res += state->Reg[Ra];
- // FIXME: Test and clear/set the Q bit.
- state->Reg[Rd] = res;
- }
- else
- {
- if (ntBITS (4, 7) == 1)
- {
- // MLS<c> <Rd>,<Rn>,<Rm>,<Ra>
- state->Reg[Rd] = state->Reg[Ra] - (state->Reg[Rn] * state->Reg[Rm]);
- }
- else
- {
- tASSERT (ntBITS (4, 7) == 0);
-
- if (Ra == 15)
- // MUL<c> <Rd>,<Rn>,<Rm>
- state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm];
- else
- // MLA<c> <Rd>,<Rn>,<Rm>,<Ra>
- state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm] + state->Reg[Ra];
- }
- }
- * pvalid = t_resolved;
- break;
- }
-
- case 0xDC:
- if (tBIT (4) == 0 && ntBITS (4, 7) == 0)
- {
- // SMULL
- * ainstr = 0xE0C00090;
- * ainstr |= (ntBITS (8, 11) << 16); // RdHi
- * ainstr |= (ntBITS (12, 15) << 12); // RdLo
- * ainstr |= (ntBITS (0, 3) << 8); // Rm
- * ainstr |= tBITS (0, 3); // Rn
- * pvalid = t_decoded;
- }
- else if (tBIT (4) == 1 && ntBITS (4, 7) == 0xF)
- {
- // SDIV
- * ainstr = 0xE710F010;
- * ainstr |= (ntBITS (8, 11) << 16); // Rd
- * ainstr |= (ntBITS (0, 3) << 8); // Rm
- * ainstr |= tBITS (0, 3); // Rn
- * pvalid = t_decoded;
- }
- else
- {
- fprintf (stderr, "(op = %x) ", tBITS (5,12));
- tASSERT (0);
- return;
- }
- break;
-
- case 0xDD:
- if (tBIT (4) == 0 && ntBITS (4, 7) == 0)
- {
- // UMULL
- * ainstr = 0xE0800090;
- * ainstr |= (ntBITS (8, 11) << 16); // RdHi
- * ainstr |= (ntBITS (12, 15) << 12); // RdLo
- * ainstr |= (ntBITS (0, 3) << 8); // Rm
- * ainstr |= tBITS (0, 3); // Rn
- * pvalid = t_decoded;
- }
- else if (tBIT (4) == 1 && ntBITS (4, 7) == 0xF)
- {
- // UDIV
- * ainstr = 0xE730F010;
- * ainstr |= (ntBITS (8, 11) << 16); // Rd
- * ainstr |= (ntBITS (0, 3) << 8); // Rm
- * ainstr |= tBITS (0, 3); // Rn
- * pvalid = t_decoded;
- }
- else
- {
- fprintf (stderr, "(op = %x) ", tBITS (5,12));
- tASSERT (0);
- return;
- }
- break;
-
- case 0xDF: // UMLAL
- tASSERT (tBIT (4) == 0);
- tASSERT (ntBITS (4, 7) == 0);
- * ainstr = 0xE0A00090;
- * ainstr |= (ntBITS (8, 11) << 16); // RdHi
- * ainstr |= (ntBITS (12, 15) << 12); // RdLo
- * ainstr |= (ntBITS (0, 3) << 8); // Rm
- * ainstr |= tBITS (0, 3); // Rn
- * pvalid = t_decoded;
- break;
-
- default:
- fprintf (stderr, "(op = %x) ", tBITS (5,12));
- tASSERT (0);
- return;
- }
-
- /* Tell the Thumb decoder to skip the next 16-bit insn - it was
- part of this insn - unless this insn has changed the PC. */
- skipping_32bit_thumb = pc + 2;
-}
-
-/* Attempt to emulate an ARMv6 instruction.
- Stores t_branch into PVALUE upon success or t_undefined otherwise. */
-
-static void
-handle_v6_thumb_insn (ARMul_State * state,
- ARMword tinstr,
- ARMword next_instr,
- ARMword pc,
- ARMword * ainstr,
- tdstate * pvalid)
-{
- if (! state->is_v6)
- {
- * pvalid = t_undefined;
- return;
- }
-
- if (tBITS (12, 15) == 0xB
- && tBIT (10) == 0
- && tBIT (8) == 1)
- {
- // Conditional branch forwards.
- ARMword Rn = tBITS (0, 2);
- ARMword imm5 = tBIT (9) << 5 | tBITS (3, 7);
-
- if (tBIT (11))
- {
- if (state->Reg[Rn] != 0)
- {
- state->Reg[15] = (pc + 4 + imm5 * 2);
- FLUSHPIPE;
- }
- }
- else
- {
- if (state->Reg[Rn] == 0)
- {
- state->Reg[15] = (pc + 4 + imm5 * 2);
- FLUSHPIPE;
- }
- }
- * pvalid = t_branch;
- return;
- }
-
- switch (tinstr & 0xFFC0)
- {
- case 0x4400:
- case 0x4480:
- case 0x4440:
- case 0x44C0: // ADD
- {
- ARMword Rd = (tBIT (7) << 3) | tBITS (0, 2);
- ARMword Rm = tBITS (3, 6);
- state->Reg[Rd] += state->Reg[Rm];
- break;
- }
-
- case 0x4600: // MOV<c> <Rd>,<Rm>
- {
- // instr [15, 8] = 0100 0110
- // instr [7] = Rd<high>
- // instr [6,3] = Rm
- // instr [2,0] = Rd<low>
- ARMword Rd = (tBIT(7) << 3) | tBITS (0, 2);
- // FIXME: Check for Rd == 15 and ITblock.
- state->Reg[Rd] = state->Reg[tBITS (3, 6)];
- break;
- }
-
- case 0xBF00:
- case 0xBF40:
- case 0xBF80:
- case 0xBFC0:
- handle_IT_block (state, tinstr, pvalid);
- return;
-
- case 0xE840:
- case 0xE880: // LDMIA
- case 0xE8C0:
- case 0xE900: // STM
- case 0xE940:
- case 0xE980:
- case 0xE9C0: // LDRD
- case 0xEA00: // BIC
- case 0xEA40: // ORR
- case 0xEA80: // EOR
- case 0xEAC0:
- case 0xEB00: // ADD
- case 0xEB40: // SBC
- case 0xEB80: // SUB
- case 0xEBC0: // RSB
- case 0xFA80: // UADD, SEL
- case 0xFBC0: // UMULL, SMULL, SDIV, UDIV
- handle_T2_insn (state, tinstr, next_instr, pc, ainstr, pvalid);
- return;
-
- case 0xba00: /* rev */
- {
- ARMword val = state->Reg[tBITS (3, 5)];
- state->Reg [tBITS (0, 2)] =
- (val >> 24)
- | ((val >> 8) & 0xFF00)
- | ((val << 8) & 0xFF0000)
- | (val << 24);
- break;
- }
-
- case 0xba40: /* rev16 */
- {
- ARMword val = state->Reg[tBITS (3, 5)];
- state->Reg [tBITS (0, 2)] = (val >> 16) | (val << 16);
- break;
- }
-
- case 0xb660: /* cpsie */
- case 0xb670: /* cpsid */
- case 0xbac0: /* revsh */
- case 0xb650: /* setend */
- default:
- printf ("Unhandled v6 thumb insn: %04x\n", tinstr);
- * pvalid = t_undefined;
- return;
-
- case 0xb200: /* sxth */
- {
- ARMword Rm = state->Reg [(tinstr & 0x38) >> 3];
-
- if (Rm & 0x8000)
- state->Reg [(tinstr & 0x7)] = (Rm & 0xffff) | 0xffff0000;
- else
- state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
- break;
- }
-
- case 0xb240: /* sxtb */
- {
- ARMword Rm = state->Reg [(tinstr & 0x38) >> 3];
-
- if (Rm & 0x80)
- state->Reg [(tinstr & 0x7)] = (Rm & 0xff) | 0xffffff00;
- else
- state->Reg [(tinstr & 0x7)] = Rm & 0xff;
- break;
- }
-
- case 0xb280: /* uxth */
- {
- ARMword Rm = state->Reg [(tinstr & 0x38) >> 3];
-
- state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
- break;
- }
-
- case 0xb2c0: /* uxtb */
- {
- ARMword Rm = state->Reg [(tinstr & 0x38) >> 3];
-
- state->Reg [(tinstr & 0x7)] = Rm & 0xff;
- break;
- }
- }
- /* Indicate that the instruction has been processed. */
- * pvalid = t_branch;
-}
-
-/* Decode a 16bit Thumb instruction. The instruction is in the low
- 16-bits of the tinstr field, with the following Thumb instruction
- held in the high 16-bits. Passing in two Thumb instructions allows
- easier simulation of the special dual BL instruction. */
-
-tdstate
-ARMul_ThumbDecode (ARMul_State * state,
- ARMword pc,
- ARMword tinstr,
- ARMword * ainstr)
-{
- tdstate valid = t_decoded; /* default assumes a valid instruction */
- ARMword next_instr;
- ARMword old_tinstr = tinstr;
-
- if (skipping_32bit_thumb == pc)
- {
- skipping_32bit_thumb = 0;
- return t_branch;
- }
- skipping_32bit_thumb = 0;
-
- if (state->bigendSig)
- {
- next_instr = tinstr & 0xFFFF;
- tinstr >>= 16;
- }
- else
- {
- next_instr = tinstr >> 16;
- tinstr &= 0xFFFF;
- }
-
- if (! IT_block_allow (state))
- {
- if ( tBITS (11, 15) == 0x1F
- || tBITS (11, 15) == 0x1E
- || tBITS (11, 15) == 0x1D)
- {
- if (trace)
- fprintf (stderr, "pc: %x, SKIP instr: %04x|%04x\n",
- pc & ~1, tinstr, next_instr);
- skipping_32bit_thumb = pc + 2;
- }
- else if (trace)
- fprintf (stderr, "pc: %x, SKIP instr: %04x\n", pc & ~1, tinstr);
-
- return t_branch;
- }
-
- old_tinstr = tinstr;
- if (trace)
- fprintf (stderr, "pc: %x, Thumb instr: %x", pc & ~1, tinstr);
-
-#if 1 /* debugging to catch non updates */
- *ainstr = 0xDEADC0DE;
-#endif
-
- switch ((tinstr & 0xF800) >> 11)
- {
- case 0: /* LSL */
- case 1: /* LSR */
- case 2: /* ASR */
- /* Format 1 */
- *ainstr = 0xE1B00000 /* base opcode */
- | ((tinstr & 0x1800) >> (11 - 5)) /* shift type */
- | ((tinstr & 0x07C0) << (7 - 6)) /* imm5 */
- | ((tinstr & 0x0038) >> 3) /* Rs */
- | ((tinstr & 0x0007) << 12); /* Rd */
- break;
- case 3: /* ADD/SUB */
- /* Format 2 */
- {
- ARMword subset[4] =
- {
- 0xE0900000, /* ADDS Rd,Rs,Rn */
- 0xE0500000, /* SUBS Rd,Rs,Rn */
- 0xE2900000, /* ADDS Rd,Rs,#imm3 */
- 0xE2500000 /* SUBS Rd,Rs,#imm3 */
- };
- /* It is quicker indexing into a table, than performing switch
- or conditionals: */
- *ainstr = subset[(tinstr & 0x0600) >> 9] /* base opcode */
- | ((tinstr & 0x01C0) >> 6) /* Rn or imm3 */
- | ((tinstr & 0x0038) << (16 - 3)) /* Rs */
- | ((tinstr & 0x0007) << (12 - 0)); /* Rd */
-
- if (in_IT_block ())
- *ainstr &= ~ (1 << 20);
- }
- break;
- case 4:
- * ainstr = 0xE3A00000; /* MOV Rd,#imm8 */
- if (! in_IT_block ())
- * ainstr |= (1 << 20);
- * ainstr |= tBITS (8, 10) << 12;
- * ainstr |= tBITS (0, 7);
- break;
-
- case 5:
- * ainstr = 0xE3500000; /* CMP Rd,#imm8 */
- * ainstr |= tBITS (8, 10) << 16;
- * ainstr |= tBITS (0, 7);
- break;
-
- case 6:
- case 7:
- * ainstr = tBIT (11)
- ? 0xE2400000 /* SUB Rd,Rd,#imm8 */
- : 0xE2800000; /* ADD Rd,Rd,#imm8 */
- if (! in_IT_block ())
- * ainstr |= (1 << 20);
- * ainstr |= tBITS (8, 10) << 12;
- * ainstr |= tBITS (8, 10) << 16;
- * ainstr |= tBITS (0, 7);
- break;
-
- case 8: /* Arithmetic and high register transfers */
- /* TODO: Since the subsets for both Format 4 and Format 5
- instructions are made up of different ARM encodings, we could
- save the following conditional, and just have one large
- subset. */
- if ((tinstr & (1 << 10)) == 0)
- {
- /* Format 4 */
- struct insn_format {
- ARMword opcode;
- enum { t_norm, t_shift, t_neg, t_mul } otype;
- };
- static const struct insn_format subset[16] =
- {
- { 0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */
- { 0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */
- { 0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */
- { 0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */
- { 0xE1B00050, t_shift}, /* MOVS Rd,Rd,ASR Rs */
- { 0xE0B00000, t_norm}, /* ADCS Rd,Rd,Rs */
- { 0xE0D00000, t_norm}, /* SBCS Rd,Rd,Rs */
- { 0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */
- { 0xE1100000, t_norm}, /* TST Rd,Rs */
- { 0xE2700000, t_neg}, /* RSBS Rd,Rs,#0 */
- { 0xE1500000, t_norm}, /* CMP Rd,Rs */
- { 0xE1700000, t_norm}, /* CMN Rd,Rs */
- { 0xE1900000, t_norm}, /* ORRS Rd,Rd,Rs */
- { 0xE0100090, t_mul} , /* MULS Rd,Rd,Rs */
- { 0xE1D00000, t_norm}, /* BICS Rd,Rd,Rs */
- { 0xE1F00000, t_norm} /* MVNS Rd,Rs */
- };
- *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */
-
- if (in_IT_block ())
- {
- static const struct insn_format it_subset[16] =
- {
- { 0xE0000000, t_norm}, /* AND Rd,Rd,Rs */
- { 0xE0200000, t_norm}, /* EOR Rd,Rd,Rs */
- { 0xE1A00010, t_shift}, /* MOV Rd,Rd,LSL Rs */
- { 0xE1A00030, t_shift}, /* MOV Rd,Rd,LSR Rs */
- { 0xE1A00050, t_shift}, /* MOV Rd,Rd,ASR Rs */
- { 0xE0A00000, t_norm}, /* ADC Rd,Rd,Rs */
- { 0xE0C00000, t_norm}, /* SBC Rd,Rd,Rs */
- { 0xE1A00070, t_shift}, /* MOV Rd,Rd,ROR Rs */
- { 0xE1100000, t_norm}, /* TST Rd,Rs */
- { 0xE2600000, t_neg}, /* RSB Rd,Rs,#0 */
- { 0xE1500000, t_norm}, /* CMP Rd,Rs */
- { 0xE1700000, t_norm}, /* CMN Rd,Rs */
- { 0xE1800000, t_norm}, /* ORR Rd,Rd,Rs */
- { 0xE0000090, t_mul} , /* MUL Rd,Rd,Rs */
- { 0xE1C00000, t_norm}, /* BIC Rd,Rd,Rs */
- { 0xE1E00000, t_norm} /* MVN Rd,Rs */
- };
- *ainstr = it_subset[(tinstr & 0x03C0) >> 6].opcode; /* base */
- }
-
- switch (subset[(tinstr & 0x03C0) >> 6].otype)
- {
- case t_norm:
- *ainstr |= ((tinstr & 0x0007) << 16) /* Rn */
- | ((tinstr & 0x0007) << 12) /* Rd */
- | ((tinstr & 0x0038) >> 3); /* Rs */
- break;
- case t_shift:
- *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
- | ((tinstr & 0x0007) >> 0) /* Rm */
- | ((tinstr & 0x0038) << (8 - 3)); /* Rs */
- break;
- case t_neg:
- *ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
- | ((tinstr & 0x0038) << (16 - 3)); /* Rn */
- break;
- case t_mul:
- *ainstr |= ((tinstr & 0x0007) << 16) /* Rd */
- | ((tinstr & 0x0007) << 8) /* Rs */
- | ((tinstr & 0x0038) >> 3); /* Rm */
- break;
- }
- }
- else
- {
- /* Format 5 */
- ARMword Rd = ((tinstr & 0x0007) >> 0);
- ARMword Rs = ((tinstr & 0x0038) >> 3);
- if (tinstr & (1 << 7))
- Rd += 8;
- if (tinstr & (1 << 6))
- Rs += 8;
- switch ((tinstr & 0x03C0) >> 6)
- {
- case 0x1: /* ADD Rd,Rd,Hs */
- case 0x2: /* ADD Hd,Hd,Rs */
- case 0x3: /* ADD Hd,Hd,Hs */
- *ainstr = 0xE0800000 /* base */
- | (Rd << 16) /* Rn */
- | (Rd << 12) /* Rd */
- | (Rs << 0); /* Rm */
- break;
- case 0x5: /* CMP Rd,Hs */
- case 0x6: /* CMP Hd,Rs */
- case 0x7: /* CMP Hd,Hs */
- *ainstr = 0xE1500000 /* base */
- | (Rd << 16) /* Rn */
- | (Rd << 12) /* Rd */
- | (Rs << 0); /* Rm */
- break;
- case 0x9: /* MOV Rd,Hs */
- case 0xA: /* MOV Hd,Rs */
- case 0xB: /* MOV Hd,Hs */
- *ainstr = 0xE1A00000 /* base */
- | (Rd << 12) /* Rd */
- | (Rs << 0); /* Rm */
- break;
- case 0xC: /* BX Rs */
- case 0xD: /* BX Hs */
- *ainstr = 0xE12FFF10 /* base */
- | ((tinstr & 0x0078) >> 3); /* Rd */
- break;
- case 0xE: /* UNDEFINED */
- case 0xF: /* UNDEFINED */
- if (state->is_v5)
- {
- /* BLX Rs; BLX Hs */
- *ainstr = 0xE12FFF30 /* base */
- | ((tinstr & 0x0078) >> 3); /* Rd */
- break;
- }
- ATTRIBUTE_FALLTHROUGH;
- default:
- case 0x0: /* UNDEFINED */
- case 0x4: /* UNDEFINED */
- case 0x8: /* UNDEFINED */
- handle_v6_thumb_insn (state, tinstr, next_instr, pc, ainstr, & valid);
- break;
- }
- }
- break;
- case 9: /* LDR Rd,[PC,#imm8] */
- /* Format 6 */
- *ainstr = 0xE59F0000 /* base */
- | ((tinstr & 0x0700) << (12 - 8)) /* Rd */
- | ((tinstr & 0x00FF) << (2 - 0)); /* off8 */
- break;
- case 10:
- case 11:
- /* TODO: Format 7 and Format 8 perform the same ARM encoding, so
- the following could be merged into a single subset, saving on
- the following boolean: */
- if ((tinstr & (1 << 9)) == 0)
- {
- /* Format 7 */
- ARMword subset[4] = {
- 0xE7800000, /* STR Rd,[Rb,Ro] */
- 0xE7C00000, /* STRB Rd,[Rb,Ro] */
- 0xE7900000, /* LDR Rd,[Rb,Ro] */
- 0xE7D00000 /* LDRB Rd,[Rb,Ro] */
- };
- *ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
- | ((tinstr & 0x0007) << (12 - 0)) /* Rd */
- | ((tinstr & 0x0038) << (16 - 3)) /* Rb */
- | ((tinstr & 0x01C0) >> 6); /* Ro */
- }
- else
- {
- /* Format 8 */
- ARMword subset[4] = {
- 0xE18000B0, /* STRH Rd,[Rb,Ro] */
- 0xE19000D0, /* LDRSB Rd,[Rb,Ro] */
- 0xE19000B0, /* LDRH Rd,[Rb,Ro] */
- 0xE19000F0 /* LDRSH Rd,[Rb,Ro] */
- };
- *ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
- | ((tinstr & 0x0007) << (12 - 0)) /* Rd */
- | ((tinstr & 0x0038) << (16 - 3)) /* Rb */
- | ((tinstr & 0x01C0) >> 6); /* Ro */
- }
- break;
- case 12: /* STR Rd,[Rb,#imm5] */
- case 13: /* LDR Rd,[Rb,#imm5] */
- case 14: /* STRB Rd,[Rb,#imm5] */
- case 15: /* LDRB Rd,[Rb,#imm5] */
- /* Format 9 */
- {
- ARMword subset[4] = {
- 0xE5800000, /* STR Rd,[Rb,#imm5] */
- 0xE5900000, /* LDR Rd,[Rb,#imm5] */
- 0xE5C00000, /* STRB Rd,[Rb,#imm5] */
- 0xE5D00000 /* LDRB Rd,[Rb,#imm5] */
- };
- /* The offset range defends on whether we are transferring a
- byte or word value: */
- *ainstr = subset[(tinstr & 0x1800) >> 11] /* base */
- | ((tinstr & 0x0007) << (12 - 0)) /* Rd */
- | ((tinstr & 0x0038) << (16 - 3)) /* Rb */
- | ((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); /* off5 */
- }
- break;
- case 16: /* STRH Rd,[Rb,#imm5] */
- case 17: /* LDRH Rd,[Rb,#imm5] */
- /* Format 10 */
- *ainstr = ((tinstr & (1 << 11)) /* base */
- ? 0xE1D000B0 /* LDRH */
- : 0xE1C000B0) /* STRH */
- | ((tinstr & 0x0007) << (12 - 0)) /* Rd */
- | ((tinstr & 0x0038) << (16 - 3)) /* Rb */
- | ((tinstr & 0x01C0) >> (6 - 1)) /* off5, low nibble */
- | ((tinstr & 0x0600) >> (9 - 8)); /* off5, high nibble */
- break;
- case 18: /* STR Rd,[SP,#imm8] */
- case 19: /* LDR Rd,[SP,#imm8] */
- /* Format 11 */
- *ainstr = ((tinstr & (1 << 11)) /* base */
- ? 0xE59D0000 /* LDR */
- : 0xE58D0000) /* STR */
- | ((tinstr & 0x0700) << (12 - 8)) /* Rd */
- | ((tinstr & 0x00FF) << 2); /* off8 */
- break;
- case 20: /* ADD Rd,PC,#imm8 */
- case 21: /* ADD Rd,SP,#imm8 */
- /* Format 12 */
- if ((tinstr & (1 << 11)) == 0)
- {
- /* NOTE: The PC value used here should by word aligned */
- /* We encode shift-left-by-2 in the rotate immediate field,
- so no shift of off8 is needed. */
- *ainstr = 0xE28F0F00 /* base */
- | ((tinstr & 0x0700) << (12 - 8)) /* Rd */
- | (tinstr & 0x00FF); /* off8 */
- }
- else
- {
- /* We encode shift-left-by-2 in the rotate immediate field,
- so no shift of off8 is needed. */
- *ainstr = 0xE28D0F00 /* base */
- | ((tinstr & 0x0700) << (12 - 8)) /* Rd */
- | (tinstr & 0x00FF); /* off8 */
- }
- break;
- case 22:
- case 23:
- switch (tinstr & 0x0F00)
- {
- case 0x0000:
- /* Format 13 */
- /* NOTE: The instruction contains a shift left of 2
- equivalent (implemented as ROR #30): */
- *ainstr = ((tinstr & (1 << 7)) /* base */
- ? 0xE24DDF00 /* SUB */
- : 0xE28DDF00) /* ADD */
- | (tinstr & 0x007F); /* off7 */
- break;
- case 0x0400:
- /* Format 14 - Push */
- * ainstr = 0xE92D0000 | (tinstr & 0x00FF);
- break;
- case 0x0500:
- /* Format 14 - Push + LR */
- * ainstr = 0xE92D4000 | (tinstr & 0x00FF);
- break;
- case 0x0c00:
- /* Format 14 - Pop */
- * ainstr = 0xE8BD0000 | (tinstr & 0x00FF);
- break;
- case 0x0d00:
- /* Format 14 - Pop + PC */
- * ainstr = 0xE8BD8000 | (tinstr & 0x00FF);
- break;
- case 0x0e00:
- if (state->is_v5)
- {
- /* This is normally an undefined instruction. The v5t architecture
- defines this particular pattern as a BKPT instruction, for
- hardware assisted debugging. We map onto the arm BKPT
- instruction. */
- if (state->is_v6)
- // Map to the SVC instruction instead of the BKPT instruction.
- * ainstr = 0xEF000000 | tBITS (0, 7);
- else
- * ainstr = 0xE1200070 | ((tinstr & 0xf0) << 4) | (tinstr & 0xf);
- break;
- }
- ATTRIBUTE_FALLTHROUGH;
- default:
- /* Everything else is an undefined instruction. */
- handle_v6_thumb_insn (state, tinstr, next_instr, pc, ainstr, & valid);
- break;
- }
- break;
- case 24: /* STMIA */
- case 25: /* LDMIA */
- /* Format 15 */
- *ainstr = ((tinstr & (1 << 11)) /* base */
- ? 0xE8B00000 /* LDMIA */
- : 0xE8A00000) /* STMIA */
- | ((tinstr & 0x0700) << (16 - 8)) /* Rb */
- | (tinstr & 0x00FF); /* mask8 */
- break;
- case 26: /* Bcc */
- case 27: /* Bcc/SWI */
- if ((tinstr & 0x0F00) == 0x0F00)
- {
- /* Format 17 : SWI */
- *ainstr = 0xEF000000;
- /* Breakpoint must be handled specially. */
- if ((tinstr & 0x00FF) == 0x18)
- *ainstr |= ((tinstr & 0x00FF) << 16);
- /* New breakpoint value. See gdb/arm-tdep.c */
- else if ((tinstr & 0x00FF) == 0xFE)
- *ainstr |= SWI_Breakpoint;
- else
- *ainstr |= (tinstr & 0x00FF);
- }
- else if ((tinstr & 0x0F00) != 0x0E00)
- {
- /* Format 16 */
- int doit = FALSE;
- /* TODO: Since we are doing a switch here, we could just add
- the SWI and undefined instruction checks into this
- switch to same on a couple of conditionals: */
- switch ((tinstr & 0x0F00) >> 8)
- {
- case EQ:
- doit = ZFLAG;
- break;
- case NE:
- doit = !ZFLAG;
- break;
- case VS:
- doit = VFLAG;
- break;
- case VC:
- doit = !VFLAG;
- break;
- case MI:
- doit = NFLAG;
- break;
- case PL:
- doit = !NFLAG;
- break;
- case CS:
- doit = CFLAG;
- break;
- case CC:
- doit = !CFLAG;
- break;
- case HI:
- doit = (CFLAG && !ZFLAG);
- break;
- case LS:
- doit = (!CFLAG || ZFLAG);
- break;
- case GE:
- doit = ((!NFLAG && !VFLAG) || (NFLAG && VFLAG));
- break;
- case LT:
- doit = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG));
- break;
- case GT:
- doit = ((!NFLAG && !VFLAG && !ZFLAG)
- || (NFLAG && VFLAG && !ZFLAG));
- break;
- case LE:
- doit = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) || ZFLAG;
- break;
- }
- if (doit)
- {
- state->Reg[15] = (pc + 4
- + (((tinstr & 0x7F) << 1)
- | ((tinstr & (1 << 7)) ? 0xFFFFFF00 : 0)));
- FLUSHPIPE;
- }
- valid = t_branch;
- }
- else
- /* UNDEFINED : cc=1110(AL) uses different format. */
- handle_v6_thumb_insn (state, tinstr, next_instr, pc, ainstr, & valid);
- break;
- case 28: /* B */
- /* Format 18 */
- state->Reg[15] = (pc + 4
- + (((tinstr & 0x3FF) << 1)
- | ((tinstr & (1 << 10)) ? 0xFFFFF800 : 0)));
- FLUSHPIPE;
- valid = t_branch;
- break;
- case 29: /* UNDEFINED */
- if (state->is_v6)
- {
- handle_v6_thumb_insn (state, tinstr, next_instr, pc, ainstr, & valid);
- break;
- }
-
- if (state->is_v5)
- {
- if (tinstr & 1)
- {
- handle_v6_thumb_insn (state, tinstr, next_instr, pc, ainstr, & valid);
- break;
- }
- /* Drop through. */
-
- /* Format 19 */
- /* There is no single ARM instruction equivalent for this
- instruction. Also, it should only ever be matched with the
- fmt19 "BL/BLX instruction 1" instruction. However, we do
- allow the simulation of it on its own, with undefined results
- if r14 is not suitably initialised. */
- {
- ARMword tmp = (pc + 2);
-
- state->Reg[15] = ((state->Reg[14] + ((tinstr & 0x07FF) << 1))
- & 0xFFFFFFFC);
- CLEART;
- state->Reg[14] = (tmp | 1);
- valid = t_branch;
- FLUSHPIPE;
- if (trace_funcs)
- fprintf (stderr, " pc changed to %x\n", state->Reg[15]);
- break;
- }
- }
-
- handle_v6_thumb_insn (state, tinstr, next_instr, pc, ainstr, & valid);
- break;
-
- case 30: /* BL instruction 1 */
- if (state->is_v6)
- {
- handle_T2_insn (state, tinstr, next_instr, pc, ainstr, & valid);
- break;
- }
-
- /* Format 19 */
- /* There is no single ARM instruction equivalent for this Thumb
- instruction. To keep the simulation simple (from the user
- perspective) we check if the following instruction is the
- second half of this BL, and if it is we simulate it
- immediately. */
- state->Reg[14] = state->Reg[15] \
- + (((tinstr & 0x07FF) << 12) \
- | ((tinstr & (1 << 10)) ? 0xFF800000 : 0));
-
- valid = t_branch; /* in-case we don't have the 2nd half */
- tinstr = next_instr; /* move the instruction down */
- pc += 2; /* point the pc at the 2nd half */
- if (((tinstr & 0xF800) >> 11) != 31)
- {
- if (((tinstr & 0xF800) >> 11) == 29)
- {
- ARMword tmp = (pc + 2);
-
- state->Reg[15] = ((state->Reg[14]
- + ((tinstr & 0x07FE) << 1))
- & 0xFFFFFFFC);
- CLEART;
- state->Reg[14] = (tmp | 1);
- valid = t_branch;
- FLUSHPIPE;
- }
- else
- /* Exit, since not correct instruction. */
- pc -= 2;
- break;
- }
- /* else we fall through to process the second half of the BL */
- pc += 2; /* point the pc at the 2nd half */
- ATTRIBUTE_FALLTHROUGH;
- case 31: /* BL instruction 2 */
- if (state->is_v6)
- {
- handle_T2_insn (state, old_tinstr, next_instr, pc, ainstr, & valid);
- break;
- }
-
- /* Format 19 */
- /* There is no single ARM instruction equivalent for this
- instruction. Also, it should only ever be matched with the
- fmt19 "BL instruction 1" instruction. However, we do allow
- the simulation of it on its own, with undefined results if
- r14 is not suitably initialised. */
- {
- ARMword tmp = pc;
-
- state->Reg[15] = (state->Reg[14] + ((tinstr & 0x07FF) << 1));
- state->Reg[14] = (tmp | 1);
- valid = t_branch;
- FLUSHPIPE;
- }
- break;
- }
-
- if (trace && valid != t_decoded)
- fprintf (stderr, "\n");
-
- return valid;
-}
+++ /dev/null
-/* run front end support for arm
- Copyright (C) 1995-2024 Free Software Foundation, Inc.
-
- This file is part of ARM SIM.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>. */
-
-/* This file provides the interface between the simulator and
- run.c and gdb (when the simulator is linked with gdb).
- All simulator interaction should go through this file. */
-
-/* This must come before any other includes. */
-#include "defs.h"
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <string.h>
-#include <bfd.h>
-#include <signal.h>
-#include "sim/callback.h"
-#include "sim/sim.h"
-#include "sim-main.h"
-#include "sim-options.h"
-#include "armemu.h"
-#include "dbg_rdi.h"
-#include "ansidecl.h"
-#include "sim/sim-arm.h"
-#include "gdb/signals.h"
-#include "libiberty.h"
-#include "iwmmxt.h"
-#include "maverick.h"
-#include "arm-sim.h"
-
-/* TODO: This should get pulled from the SIM_DESC. */
-host_callback *sim_callback;
-
-/* TODO: This should get merged into sim_cpu. */
-struct ARMul_State *state;
-
-/* Memory size in bytes. */
-/* TODO: Memory should be converted to the common memory module. */
-static int mem_size = (1 << 21);
-
-int stop_simulator;
-
-#include "dis-asm.h"
-
-/* TODO: Tracing should be converted to common tracing module. */
-int trace = 0;
-int disas = 0;
-int trace_funcs = 0;
-
-static struct disassemble_info info;
-static char opbuf[1000];
-
-static int ATTRIBUTE_PRINTF (2, 3)
-op_printf (char *buf, const char *fmt, ...)
-{
- int ret;
- va_list ap;
-
- va_start (ap, fmt);
- ret = vsprintf (opbuf + strlen (opbuf), fmt, ap);
- va_end (ap);
- return ret;
-}
-
-static int ATTRIBUTE_PRINTF (3, 4)
-op_styled_printf (char *buf, enum disassembler_style style,
- const char *fmt, ...)
-{
- int ret;
- va_list ap;
-
- va_start (ap, fmt);
- ret = vsprintf (opbuf + strlen (opbuf), fmt, ap);
- va_end (ap);
- return ret;
-}
-
-static int
-sim_dis_read (bfd_vma memaddr ATTRIBUTE_UNUSED,
- bfd_byte * ptr,
- unsigned int length,
- struct disassemble_info * info)
-{
- ARMword val = (ARMword) *((ARMword *) info->application_data);
-
- while (length--)
- {
- * ptr ++ = val & 0xFF;
- val >>= 8;
- }
- return 0;
-}
-
-void
-print_insn (ARMword instr)
-{
- int size;
- disassembler_ftype disassemble_fn;
-
- opbuf[0] = 0;
- info.application_data = & instr;
- disassemble_fn = disassembler (bfd_arch_arm, 0, 0, NULL);
- size = disassemble_fn (0, & info);
- fprintf (stderr, " %*s\n", size, opbuf);
-}
-
-static void
-init (void)
-{
- static int done;
-
- if (!done)
- {
- ARMul_EmulateInit ();
- state = ARMul_NewState ();
- state->bigendSig = (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? HIGH : LOW);
- ARMul_MemoryInit (state, mem_size);
- ARMul_OSInit (state);
- state->verbose = 0;
- done = 1;
- }
-}
-
-void
-ARMul_ConsolePrint (ARMul_State * state,
- const char * format,
- ...)
-{
- va_list ap;
-
- if (state->verbose)
- {
- va_start (ap, format);
- vprintf (format, ap);
- va_end (ap);
- }
-}
-
-uint64_t
-sim_write (SIM_DESC sd ATTRIBUTE_UNUSED,
- uint64_t addr,
- const void * buffer,
- uint64_t size)
-{
- uint64_t i;
- const unsigned char * data = buffer;
-
- init ();
-
- for (i = 0; i < size; i++)
- ARMul_SafeWriteByte (state, addr + i, data[i]);
-
- return size;
-}
-
-uint64_t
-sim_read (SIM_DESC sd ATTRIBUTE_UNUSED,
- uint64_t addr,
- void * buffer,
- uint64_t size)
-{
- uint64_t i;
- unsigned char * data = buffer;
-
- init ();
-
- for (i = 0; i < size; i++)
- data[i] = ARMul_SafeReadByte (state, addr + i);
-
- return size;
-}
-
-int
-sim_stop (SIM_DESC sd ATTRIBUTE_UNUSED)
-{
- state->Emulate = STOP;
- stop_simulator = 1;
- return 1;
-}
-
-void
-sim_resume (SIM_DESC sd ATTRIBUTE_UNUSED,
- int step,
- int siggnal ATTRIBUTE_UNUSED)
-{
- state->EndCondition = 0;
- stop_simulator = 0;
-
- if (step)
- {
- state->Reg[15] = ARMul_DoInstr (state);
- if (state->EndCondition == 0)
- state->EndCondition = RDIError_BreakpointReached;
- }
- else
- {
- state->NextInstr = RESUME; /* treat as PC change */
- state->Reg[15] = ARMul_DoProg (state);
- }
-
- FLUSHPIPE;
-}
-
-SIM_RC
-sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED,
- struct bfd * abfd,
- char * const *argv,
- char * const *env)
-{
- int argvlen = 0;
- int mach;
- char * const *arg;
-
- init ();
-
- if (abfd != NULL)
- {
- ARMul_SetPC (state, bfd_get_start_address (abfd));
- mach = bfd_get_mach (abfd);
- }
- else
- {
- ARMul_SetPC (state, 0); /* ??? */
- mach = 0;
- }
-
-#ifdef MODET
- if (abfd != NULL && (bfd_get_start_address (abfd) & 1))
- SETT;
-#endif
-
- switch (mach)
- {
- default:
- (*sim_callback->printf_filtered)
- (sim_callback,
- "Unknown machine type '%d'; please update sim_create_inferior.\n",
- mach);
- ATTRIBUTE_FALLTHROUGH;
-
- case 0:
- /* We wouldn't set the machine type with earlier toolchains, so we
- explicitly select a processor capable of supporting all ARMs in
- 32bit mode. */
- ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
- break;
-
-#if 1
- case bfd_mach_arm_6T2:
- case bfd_mach_arm_7:
- case bfd_mach_arm_7EM:
- ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
- break;
-#endif
-
- case bfd_mach_arm_XScale:
- ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
- break;
-
- case bfd_mach_arm_iWMMXt2:
- case bfd_mach_arm_iWMMXt:
- {
- extern int SWI_vector_installed;
- ARMword i;
-
- if (! SWI_vector_installed)
- {
- /* Intialise the hardware vectors to zero. */
- if (! SWI_vector_installed)
- for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
- ARMul_WriteWord (state, i, 0);
-
- /* ARM_WriteWord will have detected the write to the SWI vector,
- but we want SWI_vector_installed to remain at 0 so that thumb
- mode breakpoints will work. */
- SWI_vector_installed = 0;
- }
- }
- ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
- break;
-
- case bfd_mach_arm_ep9312:
- ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
- break;
-
- case bfd_mach_arm_5:
- if (bfd_family_coff (abfd))
- {
- /* This is a special case in order to support COFF based ARM toolchains.
- The COFF header does not have enough room to store all the different
- kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
- to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
- machine type here, we assume it could be any of the above architectures
- and so select the most feature-full. */
- ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
- break;
- }
- ATTRIBUTE_FALLTHROUGH;
-
- case bfd_mach_arm_5T:
- ARMul_SelectProcessor (state, ARM_v5_Prop);
- break;
-
- case bfd_mach_arm_5TE:
- ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
- break;
-
- case bfd_mach_arm_4:
- case bfd_mach_arm_4T:
- ARMul_SelectProcessor (state, ARM_v4_Prop);
- break;
-
- case bfd_mach_arm_3:
- case bfd_mach_arm_3M:
- ARMul_SelectProcessor (state, ARM_Lock_Prop);
- break;
-
- case bfd_mach_arm_2:
- case bfd_mach_arm_2a:
- ARMul_SelectProcessor (state, ARM_Fix26_Prop);
- break;
- }
-
- memset (& info, 0, sizeof (info));
- INIT_DISASSEMBLE_INFO (info, stdout, op_printf, op_styled_printf);
- info.read_memory_func = sim_dis_read;
- info.arch = bfd_get_arch (abfd);
- info.mach = bfd_get_mach (abfd);
- info.endian_code = BFD_ENDIAN_LITTLE;
- if (info.mach == 0)
- info.arch = bfd_arch_arm;
- disassemble_init_for_target (& info);
-
- if (argv != NULL)
- {
- /* Set up the command line by laboriously stringing together
- the environment carefully picked apart by our caller. */
-
- /* Free any old stuff. */
- if (state->CommandLine != NULL)
- {
- free (state->CommandLine);
- state->CommandLine = NULL;
- }
-
- /* See how much we need. */
- for (arg = argv; *arg != NULL; arg++)
- argvlen += strlen (*arg) + 1;
-
- /* Allocate it. */
- state->CommandLine = malloc (argvlen + 1);
- if (state->CommandLine != NULL)
- {
- arg = argv;
- state->CommandLine[0] = '\0';
-
- for (arg = argv; *arg != NULL; arg++)
- {
- strcat (state->CommandLine, *arg);
- strcat (state->CommandLine, " ");
- }
- }
- }
-
- if (env != NULL)
- {
- /* Now see if there's a MEMSIZE spec in the environment. */
- while (*env)
- {
- if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
- {
- char *end_of_num;
-
- /* Set up memory limit. */
- state->MemSize =
- strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
- }
- env++;
- }
- }
-
- return SIM_RC_OK;
-}
-
-static int
-frommem (struct ARMul_State *state, const unsigned char *memory)
-{
- if (state->bigendSig == HIGH)
- return (memory[0] << 24) | (memory[1] << 16)
- | (memory[2] << 8) | (memory[3] << 0);
- else
- return (memory[3] << 24) | (memory[2] << 16)
- | (memory[1] << 8) | (memory[0] << 0);
-}
-
-static void
-tomem (struct ARMul_State *state,
- unsigned char *memory,
- int val)
-{
- if (state->bigendSig == HIGH)
- {
- memory[0] = val >> 24;
- memory[1] = val >> 16;
- memory[2] = val >> 8;
- memory[3] = val >> 0;
- }
- else
- {
- memory[3] = val >> 24;
- memory[2] = val >> 16;
- memory[1] = val >> 8;
- memory[0] = val >> 0;
- }
-}
-
-static int
-arm_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length)
-{
- init ();
-
- switch ((enum sim_arm_regs) rn)
- {
- case SIM_ARM_R0_REGNUM:
- case SIM_ARM_R1_REGNUM:
- case SIM_ARM_R2_REGNUM:
- case SIM_ARM_R3_REGNUM:
- case SIM_ARM_R4_REGNUM:
- case SIM_ARM_R5_REGNUM:
- case SIM_ARM_R6_REGNUM:
- case SIM_ARM_R7_REGNUM:
- case SIM_ARM_R8_REGNUM:
- case SIM_ARM_R9_REGNUM:
- case SIM_ARM_R10_REGNUM:
- case SIM_ARM_R11_REGNUM:
- case SIM_ARM_R12_REGNUM:
- case SIM_ARM_R13_REGNUM:
- case SIM_ARM_R14_REGNUM:
- case SIM_ARM_R15_REGNUM: /* PC */
- case SIM_ARM_FP0_REGNUM:
- case SIM_ARM_FP1_REGNUM:
- case SIM_ARM_FP2_REGNUM:
- case SIM_ARM_FP3_REGNUM:
- case SIM_ARM_FP4_REGNUM:
- case SIM_ARM_FP5_REGNUM:
- case SIM_ARM_FP6_REGNUM:
- case SIM_ARM_FP7_REGNUM:
- case SIM_ARM_FPS_REGNUM:
- ARMul_SetReg (state, state->Mode, rn, frommem (state, buf));
- break;
-
- case SIM_ARM_PS_REGNUM:
- state->Cpsr = frommem (state, buf);
- ARMul_CPSRAltered (state);
- break;
-
- case SIM_ARM_MAVERIC_COP0R0_REGNUM:
- case SIM_ARM_MAVERIC_COP0R1_REGNUM:
- case SIM_ARM_MAVERIC_COP0R2_REGNUM:
- case SIM_ARM_MAVERIC_COP0R3_REGNUM:
- case SIM_ARM_MAVERIC_COP0R4_REGNUM:
- case SIM_ARM_MAVERIC_COP0R5_REGNUM:
- case SIM_ARM_MAVERIC_COP0R6_REGNUM:
- case SIM_ARM_MAVERIC_COP0R7_REGNUM:
- case SIM_ARM_MAVERIC_COP0R8_REGNUM:
- case SIM_ARM_MAVERIC_COP0R9_REGNUM:
- case SIM_ARM_MAVERIC_COP0R10_REGNUM:
- case SIM_ARM_MAVERIC_COP0R11_REGNUM:
- case SIM_ARM_MAVERIC_COP0R12_REGNUM:
- case SIM_ARM_MAVERIC_COP0R13_REGNUM:
- case SIM_ARM_MAVERIC_COP0R14_REGNUM:
- case SIM_ARM_MAVERIC_COP0R15_REGNUM:
- memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
- buf, sizeof (struct maverick_regs));
- return sizeof (struct maverick_regs);
-
- case SIM_ARM_MAVERIC_DSPSC_REGNUM:
- memcpy (&DSPsc, buf, sizeof DSPsc);
- return sizeof DSPsc;
-
- case SIM_ARM_IWMMXT_COP0R0_REGNUM:
- case SIM_ARM_IWMMXT_COP0R1_REGNUM:
- case SIM_ARM_IWMMXT_COP0R2_REGNUM:
- case SIM_ARM_IWMMXT_COP0R3_REGNUM:
- case SIM_ARM_IWMMXT_COP0R4_REGNUM:
- case SIM_ARM_IWMMXT_COP0R5_REGNUM:
- case SIM_ARM_IWMMXT_COP0R6_REGNUM:
- case SIM_ARM_IWMMXT_COP0R7_REGNUM:
- case SIM_ARM_IWMMXT_COP0R8_REGNUM:
- case SIM_ARM_IWMMXT_COP0R9_REGNUM:
- case SIM_ARM_IWMMXT_COP0R10_REGNUM:
- case SIM_ARM_IWMMXT_COP0R11_REGNUM:
- case SIM_ARM_IWMMXT_COP0R12_REGNUM:
- case SIM_ARM_IWMMXT_COP0R13_REGNUM:
- case SIM_ARM_IWMMXT_COP0R14_REGNUM:
- case SIM_ARM_IWMMXT_COP0R15_REGNUM:
- case SIM_ARM_IWMMXT_COP1R0_REGNUM:
- case SIM_ARM_IWMMXT_COP1R1_REGNUM:
- case SIM_ARM_IWMMXT_COP1R2_REGNUM:
- case SIM_ARM_IWMMXT_COP1R3_REGNUM:
- case SIM_ARM_IWMMXT_COP1R4_REGNUM:
- case SIM_ARM_IWMMXT_COP1R5_REGNUM:
- case SIM_ARM_IWMMXT_COP1R6_REGNUM:
- case SIM_ARM_IWMMXT_COP1R7_REGNUM:
- case SIM_ARM_IWMMXT_COP1R8_REGNUM:
- case SIM_ARM_IWMMXT_COP1R9_REGNUM:
- case SIM_ARM_IWMMXT_COP1R10_REGNUM:
- case SIM_ARM_IWMMXT_COP1R11_REGNUM:
- case SIM_ARM_IWMMXT_COP1R12_REGNUM:
- case SIM_ARM_IWMMXT_COP1R13_REGNUM:
- case SIM_ARM_IWMMXT_COP1R14_REGNUM:
- case SIM_ARM_IWMMXT_COP1R15_REGNUM:
- return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, buf);
-
- default:
- return 0;
- }
-
- return length;
-}
-
-static int
-arm_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length)
-{
- unsigned char *memory = buf;
- ARMword regval;
- int len = length;
-
- init ();
-
- switch ((enum sim_arm_regs) rn)
- {
- case SIM_ARM_R0_REGNUM:
- case SIM_ARM_R1_REGNUM:
- case SIM_ARM_R2_REGNUM:
- case SIM_ARM_R3_REGNUM:
- case SIM_ARM_R4_REGNUM:
- case SIM_ARM_R5_REGNUM:
- case SIM_ARM_R6_REGNUM:
- case SIM_ARM_R7_REGNUM:
- case SIM_ARM_R8_REGNUM:
- case SIM_ARM_R9_REGNUM:
- case SIM_ARM_R10_REGNUM:
- case SIM_ARM_R11_REGNUM:
- case SIM_ARM_R12_REGNUM:
- case SIM_ARM_R13_REGNUM:
- case SIM_ARM_R14_REGNUM:
- case SIM_ARM_R15_REGNUM: /* PC */
- regval = ARMul_GetReg (state, state->Mode, rn);
- break;
-
- case SIM_ARM_FP0_REGNUM:
- case SIM_ARM_FP1_REGNUM:
- case SIM_ARM_FP2_REGNUM:
- case SIM_ARM_FP3_REGNUM:
- case SIM_ARM_FP4_REGNUM:
- case SIM_ARM_FP5_REGNUM:
- case SIM_ARM_FP6_REGNUM:
- case SIM_ARM_FP7_REGNUM:
- case SIM_ARM_FPS_REGNUM:
- memset (memory, 0, length);
- return 0;
-
- case SIM_ARM_PS_REGNUM:
- regval = ARMul_GetCPSR (state);
- break;
-
- case SIM_ARM_MAVERIC_COP0R0_REGNUM:
- case SIM_ARM_MAVERIC_COP0R1_REGNUM:
- case SIM_ARM_MAVERIC_COP0R2_REGNUM:
- case SIM_ARM_MAVERIC_COP0R3_REGNUM:
- case SIM_ARM_MAVERIC_COP0R4_REGNUM:
- case SIM_ARM_MAVERIC_COP0R5_REGNUM:
- case SIM_ARM_MAVERIC_COP0R6_REGNUM:
- case SIM_ARM_MAVERIC_COP0R7_REGNUM:
- case SIM_ARM_MAVERIC_COP0R8_REGNUM:
- case SIM_ARM_MAVERIC_COP0R9_REGNUM:
- case SIM_ARM_MAVERIC_COP0R10_REGNUM:
- case SIM_ARM_MAVERIC_COP0R11_REGNUM:
- case SIM_ARM_MAVERIC_COP0R12_REGNUM:
- case SIM_ARM_MAVERIC_COP0R13_REGNUM:
- case SIM_ARM_MAVERIC_COP0R14_REGNUM:
- case SIM_ARM_MAVERIC_COP0R15_REGNUM:
- memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
- sizeof (struct maverick_regs));
- return sizeof (struct maverick_regs);
-
- case SIM_ARM_MAVERIC_DSPSC_REGNUM:
- memcpy (memory, & DSPsc, sizeof DSPsc);
- return sizeof DSPsc;
-
- case SIM_ARM_IWMMXT_COP0R0_REGNUM:
- case SIM_ARM_IWMMXT_COP0R1_REGNUM:
- case SIM_ARM_IWMMXT_COP0R2_REGNUM:
- case SIM_ARM_IWMMXT_COP0R3_REGNUM:
- case SIM_ARM_IWMMXT_COP0R4_REGNUM:
- case SIM_ARM_IWMMXT_COP0R5_REGNUM:
- case SIM_ARM_IWMMXT_COP0R6_REGNUM:
- case SIM_ARM_IWMMXT_COP0R7_REGNUM:
- case SIM_ARM_IWMMXT_COP0R8_REGNUM:
- case SIM_ARM_IWMMXT_COP0R9_REGNUM:
- case SIM_ARM_IWMMXT_COP0R10_REGNUM:
- case SIM_ARM_IWMMXT_COP0R11_REGNUM:
- case SIM_ARM_IWMMXT_COP0R12_REGNUM:
- case SIM_ARM_IWMMXT_COP0R13_REGNUM:
- case SIM_ARM_IWMMXT_COP0R14_REGNUM:
- case SIM_ARM_IWMMXT_COP0R15_REGNUM:
- case SIM_ARM_IWMMXT_COP1R0_REGNUM:
- case SIM_ARM_IWMMXT_COP1R1_REGNUM:
- case SIM_ARM_IWMMXT_COP1R2_REGNUM:
- case SIM_ARM_IWMMXT_COP1R3_REGNUM:
- case SIM_ARM_IWMMXT_COP1R4_REGNUM:
- case SIM_ARM_IWMMXT_COP1R5_REGNUM:
- case SIM_ARM_IWMMXT_COP1R6_REGNUM:
- case SIM_ARM_IWMMXT_COP1R7_REGNUM:
- case SIM_ARM_IWMMXT_COP1R8_REGNUM:
- case SIM_ARM_IWMMXT_COP1R9_REGNUM:
- case SIM_ARM_IWMMXT_COP1R10_REGNUM:
- case SIM_ARM_IWMMXT_COP1R11_REGNUM:
- case SIM_ARM_IWMMXT_COP1R12_REGNUM:
- case SIM_ARM_IWMMXT_COP1R13_REGNUM:
- case SIM_ARM_IWMMXT_COP1R14_REGNUM:
- case SIM_ARM_IWMMXT_COP1R15_REGNUM:
- return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
-
- default:
- return 0;
- }
-
- while (len)
- {
- tomem (state, memory, regval);
-
- len -= 4;
- memory += 4;
- regval = 0;
- }
-
- return length;
-}
-
-typedef struct
-{
- char * swi_option;
- unsigned int swi_mask;
-} swi_options;
-
-#define SWI_SWITCH "--swi-support"
-
-static swi_options options[] =
- {
- { "none", 0 },
- { "demon", SWI_MASK_DEMON },
- { "angel", SWI_MASK_ANGEL },
- { "redboot", SWI_MASK_REDBOOT },
- { "all", -1 },
- { "NONE", 0 },
- { "DEMON", SWI_MASK_DEMON },
- { "ANGEL", SWI_MASK_ANGEL },
- { "REDBOOT", SWI_MASK_REDBOOT },
- { "ALL", -1 }
- };
-
-
-static int
-sim_target_parse_command_line (int argc, char ** argv)
-{
- int i;
-
- for (i = 1; i < argc; i++)
- {
- char * ptr = argv[i];
- int arg;
-
- if ((ptr == NULL) || (* ptr != '-'))
- break;
-
- if (strcmp (ptr, "-t") == 0)
- {
- trace = 1;
- continue;
- }
-
- if (strcmp (ptr, "-z") == 0)
- {
- /* Remove this option from the argv array. */
- for (arg = i; arg < argc; arg ++)
- {
- free (argv[arg]);
- argv[arg] = argv[arg + 1];
- }
- argc --;
- i --;
- trace_funcs = 1;
- continue;
- }
-
- if (strcmp (ptr, "-d") == 0)
- {
- /* Remove this option from the argv array. */
- for (arg = i; arg < argc; arg ++)
- {
- free (argv[arg]);
- argv[arg] = argv[arg + 1];
- }
- argc --;
- i --;
- disas = 1;
- continue;
- }
-
- if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
- continue;
-
- if (ptr[sizeof SWI_SWITCH - 1] == 0)
- {
- /* Remove this option from the argv array. */
- for (arg = i; arg < argc; arg ++)
- {
- free (argv[arg]);
- argv[arg] = argv[arg + 1];
- }
- argc --;
-
- ptr = argv[i];
- }
- else
- ptr += sizeof SWI_SWITCH;
-
- swi_mask = 0;
-
- while (* ptr)
- {
- int o;
-
- for (o = ARRAY_SIZE (options); o--;)
- if (strncmp (ptr, options[o].swi_option,
- strlen (options[o].swi_option)) == 0)
- {
- swi_mask |= options[o].swi_mask;
- ptr += strlen (options[o].swi_option);
-
- if (* ptr == ',')
- ++ ptr;
-
- break;
- }
-
- if (o < 0)
- break;
- }
-
- if (* ptr != 0)
- fprintf (stderr, "Ignoring swi options: %s\n", ptr);
-
- /* Remove this option from the argv array. */
- for (arg = i; arg < argc; arg ++)
- {
- free (argv[arg]);
- argv[arg] = argv[arg + 1];
- }
- argc --;
- i --;
- }
- return argc;
-}
-
-static void
-sim_target_parse_arg_array (char ** argv)
-{
- sim_target_parse_command_line (countargv (argv), argv);
-}
-
-static sim_cia
-arm_pc_get (sim_cpu *cpu)
-{
- return PC;
-}
-
-static void
-arm_pc_set (sim_cpu *cpu, sim_cia pc)
-{
- ARMul_SetPC (state, pc);
-}
-
-static void
-free_state (SIM_DESC sd)
-{
- if (STATE_MODULES (sd) != NULL)
- sim_module_uninstall (sd);
- sim_cpu_free_all (sd);
- sim_state_free (sd);
-}
-
-SIM_DESC
-sim_open (SIM_OPEN_KIND kind,
- host_callback *cb,
- struct bfd *abfd,
- char * const *argv)
-{
- int i;
- char **argv_copy;
- SIM_DESC sd = sim_state_alloc (kind, cb);
- SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
-
- /* Set default options before parsing user options. */
- current_alignment = STRICT_ALIGNMENT;
-
- /* The cpu data is kept in a separately allocated chunk of memory. */
- if (sim_cpu_alloc_all (sd, 0) != SIM_RC_OK)
- {
- free_state (sd);
- return 0;
- }
-
- if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
- {
- free_state (sd);
- return 0;
- }
-
- /* The parser will print an error message for us, so we silently return. */
- if (sim_parse_args (sd, argv) != SIM_RC_OK)
- {
- free_state (sd);
- return 0;
- }
-
- /* Check for/establish the a reference program image. */
- if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
- {
- free_state (sd);
- return 0;
- }
-
- /* Configure/verify the target byte order and other runtime
- configuration options. */
- if (sim_config (sd) != SIM_RC_OK)
- {
- sim_module_uninstall (sd);
- return 0;
- }
-
- if (sim_post_argv_init (sd) != SIM_RC_OK)
- {
- /* Uninstall the modules to avoid memory leaks,
- file descriptor leaks, etc. */
- sim_module_uninstall (sd);
- return 0;
- }
-
- /* CPU specific initialization. */
- for (i = 0; i < MAX_NR_PROCESSORS; ++i)
- {
- SIM_CPU *cpu = STATE_CPU (sd, i);
-
- CPU_REG_FETCH (cpu) = arm_reg_fetch;
- CPU_REG_STORE (cpu) = arm_reg_store;
- CPU_PC_FETCH (cpu) = arm_pc_get;
- CPU_PC_STORE (cpu) = arm_pc_set;
- }
-
- sim_callback = cb;
-
- /* Copy over the argv contents so we can modify them. */
- argv_copy = dupargv (argv);
-
- sim_target_parse_arg_array (argv_copy);
-
- if (argv_copy[1] != NULL)
- {
- /* Scan for memory-size switches. */
- for (i = 0; (argv_copy[i] != NULL) && (argv_copy[i][0] != 0); i++)
- if (argv_copy[i][0] == '-' && argv_copy[i][1] == 'm')
- {
- if (argv_copy[i][2] != '\0')
- mem_size = atoi (&argv_copy[i][2]);
- else if (argv_copy[i + 1] != NULL)
- {
- mem_size = atoi (argv_copy[i + 1]);
- i++;
- }
- else
- {
- sim_callback->printf_filtered (sim_callback,
- "Missing argument to -m option\n");
- return NULL;
- }
- }
- }
-
- freeargv (argv_copy);
-
- return sd;
-}
-
-void
-sim_stop_reason (SIM_DESC sd ATTRIBUTE_UNUSED,
- enum sim_stop *reason,
- int *sigrc)
-{
- if (stop_simulator)
- {
- *reason = sim_stopped;
- *sigrc = GDB_SIGNAL_INT;
- }
- else if (state->EndCondition == 0)
- {
- *reason = sim_exited;
- *sigrc = state->Reg[0] & 255;
- }
- else
- {
- *reason = sim_stopped;
- if (state->EndCondition == RDIError_BreakpointReached)
- *sigrc = GDB_SIGNAL_TRAP;
- else if ( state->EndCondition == RDIError_DataAbort
- || state->EndCondition == RDIError_AddressException)
- *sigrc = GDB_SIGNAL_BUS;
- else
- *sigrc = 0;
- }
-}
CC_FOR_TARGET_AVR
LD_FOR_TARGET_AVR
AS_FOR_TARGET_AVR
-SIM_ENABLE_ARCH_arm_FALSE
-SIM_ENABLE_ARCH_arm_TRUE
-CC_FOR_TARGET_ARM
-LD_FOR_TARGET_ARM
-AS_FOR_TARGET_ARM
SIM_ENABLE_ARCH_aarch64_FALSE
SIM_ENABLE_ARCH_aarch64_TRUE
CC_FOR_TARGET_AARCH64
AS_FOR_TARGET_AARCH64
LD_FOR_TARGET_AARCH64
CC_FOR_TARGET_AARCH64
-AS_FOR_TARGET_ARM
-LD_FOR_TARGET_ARM
-CC_FOR_TARGET_ARM
AS_FOR_TARGET_AVR
LD_FOR_TARGET_AVR
CC_FOR_TARGET_AVR
Linker for aarch64 tests
CC_FOR_TARGET_AARCH64
C compiler for aarch64 tests
- AS_FOR_TARGET_ARM
- Assembler for arm tests
- LD_FOR_TARGET_ARM
- Linker for arm tests
- CC_FOR_TARGET_ARM
- C compiler for arm tests
AS_FOR_TARGET_AVR
Assembler for avr tests
LD_FOR_TARGET_AVR
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12895 "configure"
+#line 12881 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 13001 "configure"
+#line 12987 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
SIM_ENABLE_ARCH_aarch64_FALSE=
fi
- sim_enable_arch_arm=false
- case "${targ}" in
- all|arm*-*-*)
- if test "${targ}" = "${target}"; then
- SIM_PRIMARY_TARGET=arm
- fi
- ENABLE_SIM=yes
- as_fn_append SIM_ENABLED_ARCHES " arm"
- ac_config_files="$ac_config_files arm/.gdbinit:common/gdbinit.in"
-
-
- sim_enable_arch_arm=true
- ;;
- esac
-
-
-
-
- if test "$SIM_PRIMARY_TARGET" = "arm"; then :
- : "${AS_FOR_TARGET_ARM:=\$(AS_FOR_TARGET)}"
- : "${LD_FOR_TARGET_ARM:=\$(LD_FOR_TARGET)}"
- : "${CC_FOR_TARGET_ARM:=\$(CC_FOR_TARGET)}"
-
-fi
-
-as_fn_append SIM_TOOLCHAIN_VARS " AS_FOR_TARGET_ARM LD_FOR_TARGET_ARM CC_FOR_TARGET_ARM"
-
- if ${sim_enable_arch_arm}; then
- SIM_ENABLE_ARCH_arm_TRUE=
- SIM_ENABLE_ARCH_arm_FALSE='#'
-else
- SIM_ENABLE_ARCH_arm_TRUE='#'
- SIM_ENABLE_ARCH_arm_FALSE=
-fi
-
sim_enable_arch_avr=false
case "${targ}" in
all|avr*-*-*)
as_fn_error $? "conditional \"SIM_ENABLE_ARCH_aarch64\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
-if test -z "${SIM_ENABLE_ARCH_arm_TRUE}" && test -z "${SIM_ENABLE_ARCH_arm_FALSE}"; then
- as_fn_error $? "conditional \"SIM_ENABLE_ARCH_arm\" was never defined.
-Usually this means the macro was only invoked conditionally." "$LINENO" 5
-fi
if test -z "${SIM_ENABLE_ARCH_avr_TRUE}" && test -z "${SIM_ENABLE_ARCH_avr_FALSE}"; then
as_fn_error $? "conditional \"SIM_ENABLE_ARCH_avr\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
"libtool") CONFIG_COMMANDS="$CONFIG_COMMANDS libtool" ;;
"depfiles") CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;;
"aarch64/.gdbinit") CONFIG_FILES="$CONFIG_FILES aarch64/.gdbinit:common/gdbinit.in" ;;
- "arm/.gdbinit") CONFIG_FILES="$CONFIG_FILES arm/.gdbinit:common/gdbinit.in" ;;
"avr/.gdbinit") CONFIG_FILES="$CONFIG_FILES avr/.gdbinit:common/gdbinit.in" ;;
"bfin/.gdbinit") CONFIG_FILES="$CONFIG_FILES bfin/.gdbinit:common/gdbinit.in" ;;
"bpf/.gdbinit") CONFIG_FILES="$CONFIG_FILES bpf/.gdbinit:common/gdbinit.in" ;;
do
m4_map([SIM_TARGET], [
[[aarch64*-*-*], [aarch64]],
- [[arm*-*-*], [arm]],
[[avr*-*-*], [avr]],
[[bfin-*-*], [bfin]],
[[bpf-*-*], [bpf]],
projects / thirdparty / binutils-gdb.git / commitdiff
