--- /dev/null
+From 753872373b599384ac7df809aa61ea12d1c4d5d1 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+Date: Thu, 22 Mar 2018 10:11:30 +0100
+Subject: clk: bcm2835: De-assert/assert PLL reset signal when appropriate
+
+From: Boris Brezillon <boris.brezillon@bootlin.com>
+
+commit 753872373b599384ac7df809aa61ea12d1c4d5d1 upstream.
+
+In order to enable a PLL, not only the PLL has to be powered up and
+locked, but you also have to de-assert the reset signal. The last part
+was missing. Add it so PLLs that were not enabled by the FW/bootloader
+can be enabled from Linux.
+
+Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/bcm/clk-bcm2835.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -602,9 +602,7 @@ static void bcm2835_pll_off(struct clk_h
+ const struct bcm2835_pll_data *data = pll->data;
+
+ spin_lock(&cprman->regs_lock);
+- cprman_write(cprman, data->cm_ctrl_reg,
+- cprman_read(cprman, data->cm_ctrl_reg) |
+- CM_PLL_ANARST);
++ cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
+ cprman_write(cprman, data->a2w_ctrl_reg,
+ cprman_read(cprman, data->a2w_ctrl_reg) |
+ A2W_PLL_CTRL_PWRDN);
+@@ -640,6 +638,10 @@ static int bcm2835_pll_on(struct clk_hw
+ cpu_relax();
+ }
+
++ cprman_write(cprman, data->a2w_ctrl_reg,
++ cprman_read(cprman, data->a2w_ctrl_reg) |
++ A2W_PLL_CTRL_PRST_DISABLE);
++
+ return 0;
+ }
+
--- /dev/null
+From ce33f284935e08229046b30635e6aadcbab02b53 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Fri, 16 Feb 2018 16:27:47 +0100
+Subject: clk: fix false-positive Wmaybe-uninitialized warning
+
+From: Arnd Bergmann <arnd@arndb.de>
+
+commit ce33f284935e08229046b30635e6aadcbab02b53 upstream.
+
+When we build this driver with on x86-32, gcc produces a false-positive warning:
+
+drivers/clk/renesas/clk-sh73a0.c: In function 'sh73a0_cpg_clocks_init':
+drivers/clk/renesas/clk-sh73a0.c:155:10: error: 'parent_name' may be used uninitialized in this function [-Werror=maybe-uninitialized]
+ return clk_register_fixed_factor(NULL, name, parent_name, 0,
+
+We can work around that warning by adding a fake initialization, I tried
+and failed to come up with any better workaround. This is currently one
+of few remaining warnings for a 4.14.y randconfig build, so it would be
+good to also have it backported at least to that version. Older versions
+have more randconfig warnings, so we might not care.
+
+I had not noticed this earlier, because one patch in my randconfig test
+tree removes the '-ffreestanding' option on x86-32, and that avoids
+the warning. The -ffreestanding flag was originally global but moved
+into arch/i386 by Andi Kleen in commit 6edfba1b33c7 ("[PATCH] x86_64:
+Don't define string functions to builtin") as a 'temporary workaround'.
+
+Like many temporary hacks, this turned out to be rather long-lived, from
+all I can tell we still need a simple fix to asm/string_32.h before it
+can be removed, but I'm not sure about how to best do that.
+
+Cc: stable@vger.kernel.org
+Cc: Andi Kleen <ak@linux.intel.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/renesas/clk-sh73a0.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/renesas/clk-sh73a0.c
++++ b/drivers/clk/renesas/clk-sh73a0.c
+@@ -46,7 +46,7 @@ struct div4_clk {
+ unsigned int shift;
+ };
+
+-static struct div4_clk div4_clks[] = {
++static const struct div4_clk div4_clks[] = {
+ { "zg", "pll0", CPG_FRQCRA, 16 },
+ { "m3", "pll1", CPG_FRQCRA, 12 },
+ { "b", "pll1", CPG_FRQCRA, 8 },
+@@ -79,7 +79,7 @@ sh73a0_cpg_register_clock(struct device_
+ {
+ const struct clk_div_table *table = NULL;
+ unsigned int shift, reg, width;
+- const char *parent_name;
++ const char *parent_name = NULL;
+ unsigned int mult = 1;
+ unsigned int div = 1;
+
+@@ -135,7 +135,7 @@ sh73a0_cpg_register_clock(struct device_
+ shift = 24;
+ width = 5;
+ } else {
+- struct div4_clk *c;
++ const struct div4_clk *c;
+
+ for (c = div4_clks; c->name; c++) {
+ if (!strcmp(name, c->name)) {
--- /dev/null
+From 89cd7aec21af26fd0c117bfc4bfc781724f201de Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Thu, 1 Mar 2018 11:27:51 +0800
+Subject: clk: mediatek: fix PWM clock source by adding a fixed-factor clock
+
+From: Sean Wang <sean.wang@mediatek.com>
+
+commit 89cd7aec21af26fd0c117bfc4bfc781724f201de upstream.
+
+The clock for which all PWM devices on MT7623 or MT2701 actually depending
+on has to be divided by four from its parent clock axi_sel in the clock
+path prior to PWM devices.
+
+Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of
+clock axi_sel allows that PWM devices can have the correct resolution
+calculation.
+
+Cc: stable@vger.kernel.org
+Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/mediatek/clk-mt2701.c | 15 ++++++++-------
+ 1 file changed, 8 insertions(+), 7 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt2701.c
++++ b/drivers/clk/mediatek/clk-mt2701.c
+@@ -148,6 +148,7 @@ static const struct mtk_fixed_factor top
+ FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
+ FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
+ FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
++ FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
+ };
+
+ static const char * const axi_parents[] = {
+@@ -857,13 +858,13 @@ static const struct mtk_gate peri_clks[]
+ GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
+ GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
+ GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
+- GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
+- GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
+- GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
+- GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
+- GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
+- GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
+- GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
++ GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
++ GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
++ GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
++ GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
++ GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
++ GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
++ GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
+ GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
+ GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
+
--- /dev/null
+From 6a4a4595804548e173f0763a0e7274a3521c59a9 Mon Sep 17 00:00:00 2001
+From: Richard Genoud <richard.genoud@gmail.com>
+Date: Tue, 13 Mar 2018 16:27:02 +0100
+Subject: clk: mvebu: armada-38x: add support for missing clocks
+
+From: Richard Genoud <richard.genoud@gmail.com>
+
+commit 6a4a4595804548e173f0763a0e7274a3521c59a9 upstream.
+
+Clearfog boards can come with a CPU clocked at 1600MHz (commercial)
+or 1333MHz (industrial).
+
+They have also some dip-switches to select a different clock (666, 800,
+1066, 1200).
+
+The funny thing is that the recovery button is on the MPP34 fq selector.
+So, when booting an industrial board with this button down, the frequency
+666MHz is selected (and the kernel didn't boot).
+
+This patch add all the missing clocks.
+
+The only mode I didn't test is 2GHz (uboot found 4294MHz instead :/ ).
+
+Fixes: 0e85aeced4d6 ("clk: mvebu: add clock support for Armada 380/385")
+Cc: <stable@vger.kernel.org> # 3.16.x: 9593f4f56cf5: clk: mvebu: armada-38x: add support for 1866MHz variants
+Cc: <stable@vger.kernel.org> # 3.16.x
+
+Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
+Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/mvebu/armada-38x.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+--- a/drivers/clk/mvebu/armada-38x.c
++++ b/drivers/clk/mvebu/armada-38x.c
+@@ -46,11 +46,11 @@ static u32 __init armada_38x_get_tclk_fr
+ }
+
+ static const u32 armada_38x_cpu_frequencies[] __initconst = {
+- 0, 0, 0, 0,
+- 1066 * 1000 * 1000, 0, 0, 0,
++ 666 * 1000 * 1000, 0, 800 * 1000 * 1000, 0,
++ 1066 * 1000 * 1000, 0, 1200 * 1000 * 1000, 0,
+ 1332 * 1000 * 1000, 0, 0, 0,
+ 1600 * 1000 * 1000, 0, 0, 0,
+- 1866 * 1000 * 1000,
++ 1866 * 1000 * 1000, 0, 0, 2000 * 1000 * 1000,
+ };
+
+ static u32 __init armada_38x_get_cpu_freq(void __iomem *sar)
+@@ -76,11 +76,11 @@ static const struct coreclk_ratio armada
+ };
+
+ static const int armada_38x_cpu_l2_ratios[32][2] __initconst = {
+- {0, 1}, {0, 1}, {0, 1}, {0, 1},
+- {1, 2}, {0, 1}, {0, 1}, {0, 1},
+- {1, 2}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {1, 2}, {0, 1},
++ {1, 2}, {0, 1}, {1, 2}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {0, 1}, {1, 2},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+@@ -91,7 +91,7 @@ static const int armada_38x_cpu_ddr_rati
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+ {1, 2}, {0, 1}, {0, 1}, {0, 1},
+- {1, 2}, {0, 1}, {0, 1}, {0, 1},
++ {1, 2}, {0, 1}, {0, 1}, {7, 15},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
+ {0, 1}, {0, 1}, {0, 1}, {0, 1},
--- /dev/null
+From 2dcabf053c6ecde46f7aa3612c5a57fb8bd185c4 Mon Sep 17 00:00:00 2001
+From: Dmitry Osipenko <digetx@gmail.com>
+Date: Wed, 10 Jan 2018 16:59:42 +0300
+Subject: clk: tegra: Mark HCLK, SCLK and EMC as critical
+
+From: Dmitry Osipenko <digetx@gmail.com>
+
+commit 2dcabf053c6ecde46f7aa3612c5a57fb8bd185c4 upstream.
+
+Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
+as critical.
+
+Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
+Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
+Cc: <stable@vger.kernel.org> # v4.16
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/tegra/clk-emc.c | 2 +-
+ drivers/clk/tegra/clk-tegra-periph.c | 2 +-
+ drivers/clk/tegra/clk-tegra-super-gen4.c | 8 +++++---
+ drivers/clk/tegra/clk-tegra114.c | 3 +--
+ drivers/clk/tegra/clk-tegra124.c | 7 +++----
+ drivers/clk/tegra/clk-tegra20.c | 23 ++++++++++-------------
+ drivers/clk/tegra/clk-tegra210.c | 3 +--
+ drivers/clk/tegra/clk-tegra30.c | 14 ++++----------
+ 8 files changed, 26 insertions(+), 36 deletions(-)
+
+--- a/drivers/clk/tegra/clk-emc.c
++++ b/drivers/clk/tegra/clk-emc.c
+@@ -515,7 +515,7 @@ struct clk *tegra_clk_register_emc(void
+
+ init.name = "emc";
+ init.ops = &tegra_clk_emc_ops;
+- init.flags = 0;
++ init.flags = CLK_IS_CRITICAL;
+ init.parent_names = emc_parent_clk_names;
+ init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
+
+--- a/drivers/clk/tegra/clk-tegra-periph.c
++++ b/drivers/clk/tegra/clk-tegra-periph.c
+@@ -830,7 +830,7 @@ static struct tegra_periph_init_data gat
+ GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
+ GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
+ GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
+- GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
++ GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),
+ GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
+ GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
+ GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
+--- a/drivers/clk/tegra/clk-tegra-super-gen4.c
++++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
+@@ -125,7 +125,8 @@ static void __init tegra_sclk_init(void
+ /* SCLK */
+ dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
+ if (dt_clk) {
+- clk = clk_register_divider(NULL, "sclk", "sclk_mux", 0,
++ clk = clk_register_divider(NULL, "sclk", "sclk_mux",
++ CLK_IS_CRITICAL,
+ clk_base + SCLK_DIVIDER, 0, 8,
+ 0, &sysrate_lock);
+ *dt_clk = clk;
+@@ -137,7 +138,8 @@ static void __init tegra_sclk_init(void
+ clk = tegra_clk_register_super_mux("sclk",
+ gen_info->sclk_parents,
+ gen_info->num_sclk_parents,
+- CLK_SET_RATE_PARENT,
++ CLK_SET_RATE_PARENT |
++ CLK_IS_CRITICAL,
+ clk_base + SCLK_BURST_POLICY,
+ 0, 4, 0, 0, NULL);
+ *dt_clk = clk;
+@@ -151,7 +153,7 @@ static void __init tegra_sclk_init(void
+ clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
+ &sysrate_lock);
+ clk = clk_register_gate(NULL, "hclk", "hclk_div",
+- CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
++ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ clk_base + SYSTEM_CLK_RATE,
+ 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
+ *dt_clk = clk;
+--- a/drivers/clk/tegra/clk-tegra114.c
++++ b/drivers/clk/tegra/clk-tegra114.c
+@@ -955,8 +955,7 @@ static void __init tegra114_pll_init(voi
+
+ /* PLLM */
+ clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
+- CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
+- &pll_m_params, NULL);
++ CLK_SET_RATE_GATE, &pll_m_params, NULL);
+ clks[TEGRA114_CLK_PLL_M] = clk;
+
+ /* PLLM_OUT1 */
+--- a/drivers/clk/tegra/clk-tegra124.c
++++ b/drivers/clk/tegra/clk-tegra124.c
+@@ -1089,8 +1089,7 @@ static void __init tegra124_pll_init(voi
+
+ /* PLLM */
+ clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
+- CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
+- &pll_m_params, NULL);
++ CLK_SET_RATE_GATE, &pll_m_params, NULL);
+ clk_register_clkdev(clk, "pll_m", NULL);
+ clks[TEGRA124_CLK_PLL_M] = clk;
+
+@@ -1099,7 +1098,7 @@ static void __init tegra124_pll_init(voi
+ clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
+ 8, 8, 1, NULL);
+ clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
+- clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
++ clk_base + PLLM_OUT, 1, 0,
+ CLK_SET_RATE_PARENT, 0, NULL);
+ clk_register_clkdev(clk, "pll_m_out1", NULL);
+ clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
+@@ -1272,7 +1271,7 @@ static struct tegra_clk_init_table commo
+ { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
+ { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
+ { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
+- { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1 },
++ { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 0 },
+ { TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },
+ { TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },
+ { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },
+--- a/drivers/clk/tegra/clk-tegra20.c
++++ b/drivers/clk/tegra/clk-tegra20.c
+@@ -576,6 +576,7 @@ static struct tegra_clk tegra20_clks[teg
+ [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
+ [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
+ [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
++ [tegra_clk_emc] = { .dt_id = TEGRA20_CLK_EMC, .present = true },
+ };
+
+ static unsigned long tegra20_clk_measure_input_freq(void)
+@@ -651,8 +652,7 @@ static void tegra20_pll_init(void)
+
+ /* PLLM */
+ clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
+- CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
+- &pll_m_params, NULL);
++ CLK_SET_RATE_GATE, &pll_m_params, NULL);
+ clks[TEGRA20_CLK_PLL_M] = clk;
+
+ /* PLLM_OUT1 */
+@@ -660,7 +660,7 @@ static void tegra20_pll_init(void)
+ clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
+ 8, 8, 1, NULL);
+ clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
+- clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
++ clk_base + PLLM_OUT, 1, 0,
+ CLK_SET_RATE_PARENT, 0, NULL);
+ clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
+
+@@ -723,7 +723,8 @@ static void tegra20_super_clk_init(void)
+
+ /* SCLK */
+ clk = tegra_clk_register_super_mux("sclk", sclk_parents,
+- ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
++ ARRAY_SIZE(sclk_parents),
++ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
+ clks[TEGRA20_CLK_SCLK] = clk;
+
+@@ -814,9 +815,6 @@ static void __init tegra20_periph_clk_in
+ CLK_SET_RATE_NO_REPARENT,
+ clk_base + CLK_SOURCE_EMC,
+ 30, 2, 0, &emc_lock);
+- clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
+- 57, periph_clk_enb_refcnt);
+- clks[TEGRA20_CLK_EMC] = clk;
+
+ clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+ &emc_lock);
+@@ -1019,13 +1017,12 @@ static struct tegra_clk_init_table init_
+ { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
+ { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
+ { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
+- { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },
+- { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
+- { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },
+- { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
+- { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },
++ { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 },
++ { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 0 },
++ { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 0 },
++ { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 0 },
++ { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 },
+ { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
+- { TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1 },
+ { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
+ { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
+ { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
+--- a/drivers/clk/tegra/clk-tegra210.c
++++ b/drivers/clk/tegra/clk-tegra210.c
+@@ -3025,7 +3025,7 @@ static struct tegra_clk_init_table init_
+ { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
+ { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
+ { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
+- { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 1 },
++ { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },
+ { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
+ { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
+ { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
+@@ -3040,7 +3040,6 @@ static struct tegra_clk_init_table init_
+ { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
+ { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
+ { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
+- { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
+ { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
+ { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
+ /* TODO find a way to enable this on-demand */
+--- a/drivers/clk/tegra/clk-tegra30.c
++++ b/drivers/clk/tegra/clk-tegra30.c
+@@ -819,6 +819,7 @@ static struct tegra_clk tegra30_clks[teg
+ [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
+ [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
+ [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
++ [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = true },
+ };
+
+ static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
+@@ -843,8 +844,7 @@ static void __init tegra30_pll_init(void
+
+ /* PLLM */
+ clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
+- CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
+- &pll_m_params, NULL);
++ CLK_SET_RATE_GATE, &pll_m_params, NULL);
+ clks[TEGRA30_CLK_PLL_M] = clk;
+
+ /* PLLM_OUT1 */
+@@ -852,7 +852,7 @@ static void __init tegra30_pll_init(void
+ clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
+ 8, 8, 1, NULL);
+ clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
+- clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
++ clk_base + PLLM_OUT, 1, 0,
+ CLK_SET_RATE_PARENT, 0, NULL);
+ clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
+
+@@ -990,7 +990,7 @@ static void __init tegra30_super_clk_ini
+ /* SCLK */
+ clk = tegra_clk_register_super_mux("sclk", sclk_parents,
+ ARRAY_SIZE(sclk_parents),
+- CLK_SET_RATE_PARENT,
++ CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ clk_base + SCLK_BURST_POLICY,
+ 0, 4, 0, 0, NULL);
+ clks[TEGRA30_CLK_SCLK] = clk;
+@@ -1060,9 +1060,6 @@ static void __init tegra30_periph_clk_in
+ CLK_SET_RATE_NO_REPARENT,
+ clk_base + CLK_SOURCE_EMC,
+ 30, 2, 0, &emc_lock);
+- clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
+- 57, periph_clk_enb_refcnt);
+- clks[TEGRA30_CLK_EMC] = clk;
+
+ clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+ &emc_lock);
+@@ -1252,10 +1249,7 @@ static struct tegra_clk_init_table init_
+ { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
+ { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
+ { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
+- { TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
+- { TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
+ { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
+- { TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 },
+ { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
+ { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
+ { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
--- /dev/null
+From af2ac326087da632e9580f65205f4cc4205caf85 Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Fri, 6 Apr 2018 23:03:12 -0400
+Subject: drm/amd/display: HDMI has no sound after Panel power off/on
+
+From: Charlene Liu <charlene.liu@amd.com>
+
+commit af2ac326087da632e9580f65205f4cc4205caf85 upstream.
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+@@ -736,6 +736,8 @@ static void dce110_stream_encoder_update
+ if (info_frame->avi.valid) {
+ const uint32_t *content =
+ (const uint32_t *) &info_frame->avi.sb[0];
++ /*we need turn on clock before programming AFMT block*/
++ REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
+
+ REG_WRITE(AFMT_AVI_INFO0, content[0]);
+
--- /dev/null
+From 55a5fcafe3a94e8a0777bb993d09107d362258d2 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Thu, 1 Mar 2018 11:27:50 +0800
+Subject: dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4
+
+From: Sean Wang <sean.wang@mediatek.com>
+
+commit 55a5fcafe3a94e8a0777bb993d09107d362258d2 upstream.
+
+Just add binding for a fixed-factor clock axisel_d4, which would be
+referenced by PWM devices on MT7623 or MT2701 SoC.
+
+Cc: stable@vger.kernel.org
+Fixes: 1de9b21633d6 ("clk: mediatek: Add dt-bindings for MT2701 clocks")
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Cc: Mark Rutland <mark.rutland@arm.com>
+Cc: devicetree@vger.kernel.org
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ include/dt-bindings/clock/mt2701-clk.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/include/dt-bindings/clock/mt2701-clk.h
++++ b/include/dt-bindings/clock/mt2701-clk.h
+@@ -176,7 +176,8 @@
+ #define CLK_TOP_AUD_EXT1 156
+ #define CLK_TOP_AUD_EXT2 157
+ #define CLK_TOP_NFI1X_PAD 158
+-#define CLK_TOP_NR 159
++#define CLK_TOP_AXISEL_D4 159
++#define CLK_TOP_NR 160
+
+ /* APMIXEDSYS */
+
--- /dev/null
+From bbe4b3af9d9e3172fb9aa1f8dcdfaedcb381fc64 Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Sat, 24 Feb 2018 13:42:27 +0800
+Subject: iommu/vt-d: Fix a potential memory leak
+
+From: Lu Baolu <baolu.lu@linux.intel.com>
+
+commit bbe4b3af9d9e3172fb9aa1f8dcdfaedcb381fc64 upstream.
+
+A memory block was allocated in intel_svm_bind_mm() but never freed
+in a failure path. This patch fixes this by free it to avoid memory
+leakage.
+
+Cc: Ashok Raj <ashok.raj@intel.com>
+Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
+Cc: <stable@vger.kernel.org> # v4.4+
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Fixes: 2f26e0a9c9860 ('iommu/vt-d: Add basic SVM PASID support')
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/iommu/intel-svm.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/iommu/intel-svm.c
++++ b/drivers/iommu/intel-svm.c
+@@ -396,6 +396,7 @@ int intel_svm_bind_mm(struct device *dev
+ pasid_max - 1, GFP_KERNEL);
+ if (ret < 0) {
+ kfree(svm);
++ kfree(sdev);
+ goto out;
+ }
+ svm->pasid = ret;
--- /dev/null
+From d0a0852b9f81cf5f793bf2eae7336ed40a1a1815 Mon Sep 17 00:00:00 2001
+From: Alexander Kappner <agk@godking.net>
+Date: Wed, 28 Mar 2018 15:18:31 -0700
+Subject: mmc: core: Prevent bus reference leak in mmc_blk_init()
+
+From: Alexander Kappner <agk@godking.net>
+
+commit d0a0852b9f81cf5f793bf2eae7336ed40a1a1815 upstream.
+
+Upon module load, mmc_block allocates a bus with bus_registeri() in
+mmc_blk_init(). This reference never gets freed during module unload, which
+leads to subsequent re-insertions of the module fails and a WARN() splat is
+triggered.
+
+Fix the bug by dropping the reference for the bus in mmc_blk_exit().
+
+Signed-off-by: Alexander Kappner <agk@godking.net>
+Fixes: 97548575bef3 ("mmc: block: Convert RPMB to a character device")
+Cc: <stable@vger.kernel.org>
+Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mmc/core/block.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mmc/core/block.c
++++ b/drivers/mmc/core/block.c
+@@ -3087,6 +3087,7 @@ static void __exit mmc_blk_exit(void)
+ mmc_unregister_driver(&mmc_driver);
+ unregister_blkdev(MMC_BLOCK_MAJOR, "mmc");
+ unregister_chrdev_region(mmc_rpmb_devt, MAX_DEVICES);
++ bus_unregister(&mmc_rpmb_bus_type);
+ }
+
+ module_init(mmc_blk_init);
--- /dev/null
+From a04f0017c22453613d5f423326b190c61e3b4f98 Mon Sep 17 00:00:00 2001
+From: Alex Smith <alex.smith@imgtec.com>
+Date: Wed, 28 Mar 2018 18:00:43 -0300
+Subject: mmc: jz4740: Fix race condition in IRQ mask update
+
+From: Alex Smith <alex.smith@imgtec.com>
+
+commit a04f0017c22453613d5f423326b190c61e3b4f98 upstream.
+
+A spinlock is held while updating the internal copy of the IRQ mask,
+but not while writing it to the actual IMASK register. After the lock
+is released, an IRQ can occur before the IMASK register is written.
+If handling this IRQ causes the mask to be changed, when the handler
+returns back to the middle of the first mask update, a stale value
+will be written to the mask register.
+
+If this causes an IRQ to become unmasked that cannot have its status
+cleared by writing a 1 to it in the IREG register, e.g. the SDIO IRQ,
+then we can end up stuck with the same IRQ repeatedly being fired but
+not handled. Normally the MMC IRQ handler attempts to clear any
+unexpected IRQs by writing IREG, but for those that cannot be cleared
+in this way then the IRQ will just repeatedly fire.
+
+This was resulting in lockups after a while of using Wi-Fi on the
+CI20 (GitHub issue #19).
+
+Resolve by holding the spinlock until after the IMASK register has
+been updated.
+
+Cc: stable@vger.kernel.org
+Link: https://github.com/MIPS/CI20_linux/issues/19
+Fixes: 61bfbdb85687 ("MMC: Add support for the controller on JZ4740 SoCs.")
+Tested-by: Mathieu Malaterre <malat@debian.org>
+Signed-off-by: Alex Smith <alex.smith@imgtec.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mmc/host/jz4740_mmc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mmc/host/jz4740_mmc.c
++++ b/drivers/mmc/host/jz4740_mmc.c
+@@ -362,9 +362,9 @@ static void jz4740_mmc_set_irq_enabled(s
+ host->irq_mask &= ~irq;
+ else
+ host->irq_mask |= irq;
+- spin_unlock_irqrestore(&host->lock, flags);
+
+ writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
++ spin_unlock_irqrestore(&host->lock, flags);
+ }
+
+ static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
--- /dev/null
+From fc167daff581c01ebce8695e9618231cae3561a1 Mon Sep 17 00:00:00 2001
+From: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+Date: Tue, 3 Apr 2018 23:57:03 +0200
+Subject: mmc: tmio: Fix error handling when issuing CMD23
+
+From: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+
+commit fc167daff581c01ebce8695e9618231cae3561a1 upstream.
+
+If an error was detected when CMD23 was issued, command sequence should
+be terminated with errors and CMD23 should be issued after retuning.
+
+Fixes: 8b22c3c18be5 ("mmc: tmio: add CMD23 support")
+Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com>
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Cc: <stable@vger.kernel.org> # 4.13+
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mmc/host/tmio_mmc_core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mmc/host/tmio_mmc_core.c
++++ b/drivers/mmc/host/tmio_mmc_core.c
+@@ -911,7 +911,7 @@ static void tmio_mmc_finish_request(stru
+ host->check_scc_error(host);
+
+ /* If SET_BLOCK_COUNT, continue with main command */
+- if (host->mrq) {
++ if (host->mrq && !mrq->cmd->error) {
+ tmio_process_mrq(host, mrq);
+ return;
+ }
--- /dev/null
+From 78727137fdf49edf9f731bde79d7189067b4047a Mon Sep 17 00:00:00 2001
+From: Dan Williams <dan.j.williams@intel.com>
+Date: Mon, 2 Apr 2018 16:40:04 -0700
+Subject: nfit, address-range-scrub: fix scrub in-progress reporting
+
+From: Dan Williams <dan.j.williams@intel.com>
+
+commit 78727137fdf49edf9f731bde79d7189067b4047a upstream.
+
+There is a small window whereby ARS scan requests can schedule work that
+userspace will miss when polling scrub_show. Hold the init_mutex lock
+over calls to report the status to close this potential escape. Also,
+make sure that requests to cancel the ARS workqueue are treated as an
+idle event.
+
+Cc: <stable@vger.kernel.org>
+Cc: Vishal Verma <vishal.l.verma@intel.com>
+Fixes: 37b137ff8c83 ("nfit, libnvdimm: allow an ARS scrub...")
+Reviewed-by: Dave Jiang <dave.jiang@intel.com>
+Signed-off-by: Dan Williams <dan.j.williams@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/acpi/nfit/core.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/acpi/nfit/core.c
++++ b/drivers/acpi/nfit/core.c
+@@ -1250,8 +1250,11 @@ static ssize_t scrub_show(struct device
+ if (nd_desc) {
+ struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
+
++ mutex_lock(&acpi_desc->init_mutex);
+ rc = sprintf(buf, "%d%s", acpi_desc->scrub_count,
+- (work_busy(&acpi_desc->work)) ? "+\n" : "\n");
++ work_busy(&acpi_desc->work)
++ && !acpi_desc->cancel ? "+\n" : "\n");
++ mutex_unlock(&acpi_desc->init_mutex);
+ }
+ device_unlock(dev);
+ return rc;
--- /dev/null
+From 0731de476a37c33485af82d64041c9d193208df8 Mon Sep 17 00:00:00 2001
+From: Dan Williams <dan.j.williams@intel.com>
+Date: Wed, 21 Mar 2018 21:22:34 -0700
+Subject: nfit: skip region registration for incomplete control regions
+
+From: Dan Williams <dan.j.williams@intel.com>
+
+commit 0731de476a37c33485af82d64041c9d193208df8 upstream.
+
+Per the ACPI specification the only functional purpose for a DIMM
+Control Region to be mapped into the system physical address space, from
+an OSPM perspective, is to support block-apertures. However, there are
+some BIOSen that publish DIMM Control Region SPA entries for pre-boot
+environment consumption. Undo the kernel policy of generating disabled
+'ndblk' regions when this configuration is detected.
+
+Cc: <stable@vger.kernel.org>
+Fixes: 1f7df6f88b92 ("libnvdimm, nfit: regions (block-data-window...)")
+Reviewed-by: Toshi Kani <toshi.kani@hpe.com>
+Signed-off-by: Dan Williams <dan.j.williams@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/acpi/nfit/core.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+--- a/drivers/acpi/nfit/core.c
++++ b/drivers/acpi/nfit/core.c
+@@ -2583,7 +2583,7 @@ static int acpi_nfit_init_mapping(struct
+ struct acpi_nfit_system_address *spa = nfit_spa->spa;
+ struct nd_blk_region_desc *ndbr_desc;
+ struct nfit_mem *nfit_mem;
+- int blk_valid = 0, rc;
++ int rc;
+
+ if (!nvdimm) {
+ dev_err(acpi_desc->dev, "spa%d dimm: %#x not found\n",
+@@ -2603,15 +2603,14 @@ static int acpi_nfit_init_mapping(struct
+ if (!nfit_mem || !nfit_mem->bdw) {
+ dev_dbg(acpi_desc->dev, "spa%d %s missing bdw\n",
+ spa->range_index, nvdimm_name(nvdimm));
+- } else {
+- mapping->size = nfit_mem->bdw->capacity;
+- mapping->start = nfit_mem->bdw->start_address;
+- ndr_desc->num_lanes = nfit_mem->bdw->windows;
+- blk_valid = 1;
++ break;
+ }
+
++ mapping->size = nfit_mem->bdw->capacity;
++ mapping->start = nfit_mem->bdw->start_address;
++ ndr_desc->num_lanes = nfit_mem->bdw->windows;
+ ndr_desc->mapping = mapping;
+- ndr_desc->num_mappings = blk_valid;
++ ndr_desc->num_mappings = 1;
+ ndbr_desc = to_blk_region_desc(ndr_desc);
+ ndbr_desc->enable = acpi_nfit_blk_region_enable;
+ ndbr_desc->do_io = acpi_desc->blk_do_io;
--- /dev/null
+From 1b30dfd376e28e7f37eda5e2033f6823cdda222b Mon Sep 17 00:00:00 2001
+From: Sinan Kaya <okaya@codeaurora.org>
+Date: Tue, 10 Apr 2018 14:44:21 -0500
+Subject: PCI: Mark Broadcom HT1100 and HT2000 Root Port Extended Tags as broken
+
+From: Sinan Kaya <okaya@codeaurora.org>
+
+commit 1b30dfd376e28e7f37eda5e2033f6823cdda222b upstream.
+
+Per PCIe r3.1, sec 2.2.6.2 and 7.8.4, a Requester may not use 8-bit Tags
+unless its Extended Tag Field Enable is set, but all Receivers/Completers
+must handle 8-bit Tags correctly regardless of their Extended Tag Field
+Enable.
+
+Some devices do not handle 8-bit Tags as Completers, so add a quirk for
+them. If we find such a device, we disable Extended Tags for the entire
+hierarchy to make peer-to-peer DMA possible.
+
+The Broadcom HT1100/HT2000/HT2100 seems to have issues with handling 8-bit
+tags. Mark it as broken.
+
+This fixes Xorg hangs and unresponsive keyboards with errors like this:
+
+ radeon 0000:06:00.0: GPU lockup (current fence id 0x000000000000000e last fence id 0x0000000000000
+ [drm:r600_ring_test [radeon]] *ERROR* radeon: ring 0 test failed (scratch(0x8504)=0xCAFEDEAD)
+ [drm:r600_resume [radeon]] *ERROR* r600 startup failed on resume
+
+Fixes: 60db3a4d8cc9 ("PCI: Enable PCIe Extended Tags if supported")
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=196197
+Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
+Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
+CC: stable@vger.kernel.org # v4.11: 62ce94a7a5a5 PCI: Mark Broadcom HT2100 Root Port Extended Tags as broken
+CC: stable@vger.kernel.org # v4.11
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pci/quirks.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -4815,9 +4815,13 @@ static void quirk_no_ext_tags(struct pci
+
+ pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
+ }
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
+
+ #ifdef CONFIG_PCI_ATS
+ /*
--- /dev/null
+From 360cc036563db27881ce08049f69138438f2ddd0 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Thu, 1 Mar 2018 16:19:12 +0800
+Subject: pwm: mediatek: Fix up PWM4 and PWM5 malfunction on MT7623
+
+From: Sean Wang <sean.wang@mediatek.com>
+
+commit 360cc036563db27881ce08049f69138438f2ddd0 upstream.
+
+Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
+control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
+programming on PWM hardware causes waveform cannot be output as expected.
+Thus, the patch adds the extra condition for fixing up the weird case to
+let PWM4 or PWM5 able to work on MT7623.
+
+v1 -> v2: use pwm45_fixup naming instead of pwm45_quirk
+v2 -> v3: add more tags for Reviewed-by, Fixes, and Cc stable
+
+Cc: stable@vger.kernel.org
+Fixes: caf065f8fd58 ("pwm: Add MediaTek PWM support")
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Cc: Zhi Mao <zhi.mao@mediatek.com>
+Cc: John Crispin <john@phrozen.org>
+Cc: Matthias Brugger <matthias.bgg@gmail.com>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pwm/pwm-mediatek.c | 24 +++++++++++++++++++++---
+ 1 file changed, 21 insertions(+), 3 deletions(-)
+
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -29,7 +29,9 @@
+ #define PWMGDUR 0x0c
+ #define PWMWAVENUM 0x28
+ #define PWMDWIDTH 0x2c
++#define PWM45DWIDTH_FIXUP 0x30
+ #define PWMTHRES 0x30
++#define PWM45THRES_FIXUP 0x34
+
+ #define PWM_CLK_DIV_MAX 7
+
+@@ -54,6 +56,7 @@ static const char * const mtk_pwm_clk_na
+
+ struct mtk_pwm_platform_data {
+ unsigned int num_pwms;
++ bool pwm45_fixup;
+ };
+
+ /**
+@@ -66,6 +69,7 @@ struct mtk_pwm_chip {
+ struct pwm_chip chip;
+ void __iomem *regs;
+ struct clk *clks[MTK_CLK_MAX];
++ const struct mtk_pwm_platform_data *soc;
+ };
+
+ static const unsigned int mtk_pwm_reg_offset[] = {
+@@ -131,7 +135,8 @@ static int mtk_pwm_config(struct pwm_chi
+ {
+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
+ struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm];
+- u32 resolution, clkdiv = 0;
++ u32 resolution, clkdiv = 0, reg_width = PWMDWIDTH,
++ reg_thres = PWMTHRES;
+ int ret;
+
+ ret = mtk_pwm_clk_enable(chip, pwm);
+@@ -151,9 +156,18 @@ static int mtk_pwm_config(struct pwm_chi
+ return -EINVAL;
+ }
+
++ if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
++ /*
++ * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
++ * from the other PWMs on MT7623.
++ */
++ reg_width = PWM45DWIDTH_FIXUP;
++ reg_thres = PWM45THRES_FIXUP;
++ }
++
+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
+- mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
+- mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
++ mtk_pwm_writel(pc, pwm->hwpwm, reg_width, period_ns / resolution);
++ mtk_pwm_writel(pc, pwm->hwpwm, reg_thres, duty_ns / resolution);
+
+ mtk_pwm_clk_disable(chip, pwm);
+
+@@ -211,6 +225,7 @@ static int mtk_pwm_probe(struct platform
+ data = of_device_get_match_data(&pdev->dev);
+ if (data == NULL)
+ return -EINVAL;
++ pc->soc = data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pc->regs = devm_ioremap_resource(&pdev->dev, res);
+@@ -251,14 +266,17 @@ static int mtk_pwm_remove(struct platfor
+
+ static const struct mtk_pwm_platform_data mt2712_pwm_data = {
+ .num_pwms = 8,
++ .pwm45_fixup = false,
+ };
+
+ static const struct mtk_pwm_platform_data mt7622_pwm_data = {
+ .num_pwms = 6,
++ .pwm45_fixup = false,
+ };
+
+ static const struct mtk_pwm_platform_data mt7623_pwm_data = {
+ .num_pwms = 5,
++ .pwm45_fixup = true,
+ };
+
+ static const struct of_device_id mtk_pwm_of_match[] = {
--- /dev/null
+From 04c0a4e00dc11fedc0b0a8593adcf0f4310505d4 Mon Sep 17 00:00:00 2001
+From: Sean Wang <sean.wang@mediatek.com>
+Date: Fri, 2 Mar 2018 16:49:14 +0800
+Subject: pwm: mediatek: Improve precision in rate calculation
+
+From: Sean Wang <sean.wang@mediatek.com>
+
+commit 04c0a4e00dc11fedc0b0a8593adcf0f4310505d4 upstream.
+
+Add a way that turning resolution from in nanosecond into in picosecond
+to improve noticeably almost 4.5% precision.
+
+It's necessary to hold the new resolution with type u64 and thus related
+operations on u64 are applied instead in those rate calculations.
+
+And the patch has a dependency on [1].
+
+[1] http://lists.infradead.org/pipermail/linux-mediatek/2018-March/012225.html
+
+Cc: stable@vger.kernel.org
+Fixes: caf065f8fd58 ("pwm: Add MediaTek PWM support")
+Signed-off-by: Sean Wang <sean.wang@mediatek.com>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pwm/pwm-mediatek.c | 17 ++++++++++++-----
+ 1 file changed, 12 insertions(+), 5 deletions(-)
+
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -135,19 +135,25 @@ static int mtk_pwm_config(struct pwm_chi
+ {
+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
+ struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm];
+- u32 resolution, clkdiv = 0, reg_width = PWMDWIDTH,
++ u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
+ reg_thres = PWMTHRES;
++ u64 resolution;
+ int ret;
+
+ ret = mtk_pwm_clk_enable(chip, pwm);
+ if (ret < 0)
+ return ret;
+
+- resolution = NSEC_PER_SEC / clk_get_rate(clk);
++ /* Using resolution in picosecond gets accuracy higher */
++ resolution = (u64)NSEC_PER_SEC * 1000;
++ do_div(resolution, clk_get_rate(clk));
+
+- while (period_ns / resolution > 8191) {
++ cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
++ while (cnt_period > 8191) {
+ resolution *= 2;
+ clkdiv++;
++ cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
++ resolution);
+ }
+
+ if (clkdiv > PWM_CLK_DIV_MAX) {
+@@ -165,9 +171,10 @@ static int mtk_pwm_config(struct pwm_chi
+ reg_thres = PWM45THRES_FIXUP;
+ }
+
++ cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
+- mtk_pwm_writel(pc, pwm->hwpwm, reg_width, period_ns / resolution);
+- mtk_pwm_writel(pc, pwm->hwpwm, reg_thres, duty_ns / resolution);
++ mtk_pwm_writel(pc, pwm->hwpwm, reg_width, cnt_period);
++ mtk_pwm_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
+
+ mtk_pwm_clk_disable(chip, pwm);
+
--- /dev/null
+From 6225f9c64b40bc8a22503e9cda70f55d7a9dd3c6 Mon Sep 17 00:00:00 2001
+From: Ryo Kodama <ryo.kodama.vz@renesas.com>
+Date: Fri, 9 Mar 2018 20:24:21 +0900
+Subject: pwm: rcar: Fix a condition to prevent mismatch value setting to duty
+
+From: Ryo Kodama <ryo.kodama.vz@renesas.com>
+
+commit 6225f9c64b40bc8a22503e9cda70f55d7a9dd3c6 upstream.
+
+This patch fixes an issue that is possible to set mismatch value to duty
+for R-Car PWM if we input the following commands:
+
+ # cd /sys/class/pwm/<pwmchip>/
+ # echo 0 > export
+ # cd pwm0
+ # echo 30 > period
+ # echo 30 > duty_cycle
+ # echo 0 > duty_cycle
+ # cat duty_cycle
+ 0
+ # echo 1 > enable
+ --> Then, the actual duty_cycle is 30, not 0.
+
+So, this patch adds a condition into rcar_pwm_config() to fix this
+issue.
+
+Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
+[shimoda: revise the commit log and add Fixes and Cc tags]
+Fixes: ed6c1476bf7f ("pwm: Add support for R-Car PWM Timer")
+Cc: Cc: <stable@vger.kernel.org> # v4.4+
+Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/pwm/pwm-rcar.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+--- a/drivers/pwm/pwm-rcar.c
++++ b/drivers/pwm/pwm-rcar.c
+@@ -156,8 +156,12 @@ static int rcar_pwm_config(struct pwm_ch
+ if (div < 0)
+ return div;
+
+- /* Let the core driver set pwm->period if disabled and duty_ns == 0 */
+- if (!pwm_is_enabled(pwm) && !duty_ns)
++ /*
++ * Let the core driver set pwm->period if disabled and duty_ns == 0.
++ * But, this driver should prevent to set the new duty_ns if current
++ * duty_cycle is not set
++ */
++ if (!pwm_is_enabled(pwm) && !duty_ns && !pwm->state.duty_cycle)
+ return 0;
+
+ rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
--- /dev/null
+From 1cb19e8267a57c5174da09e0d52d1477baceccca Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Thu, 12 Apr 2018 10:51:52 -0400
+Subject: Revert "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Harry Wentland <harry.wentland@amd.com>
+
+commit 1cb19e8267a57c5174da09e0d52d1477baceccca upstream.
+
+This seems to cause flickering and lock-ups for a wide range of users.
+Revert until we've found a proper fix for the flickering and lock-ups.
+
+This reverts commit 36cc549d59864b7161f0e23d710c1c4d1b9cf022.
+
+Cc: Shirish S <shirish.s@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 ----------------------
+ 1 file changed, 28 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4776,30 +4776,6 @@ static int dm_update_planes_state(struct
+ return ret;
+ }
+
+-static int dm_atomic_check_plane_state_fb(struct drm_atomic_state *state,
+- struct drm_crtc *crtc)
+-{
+- struct drm_plane *plane;
+- struct drm_crtc_state *crtc_state;
+-
+- WARN_ON(!drm_atomic_get_new_crtc_state(state, crtc));
+-
+- drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
+- struct drm_plane_state *plane_state =
+- drm_atomic_get_plane_state(state, plane);
+-
+- if (IS_ERR(plane_state))
+- return -EDEADLK;
+-
+- crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc);
+- if (crtc->primary == plane && crtc_state->active) {
+- if (!plane_state->fb)
+- return -EINVAL;
+- }
+- }
+- return 0;
+-}
+-
+ static int amdgpu_dm_atomic_check(struct drm_device *dev,
+ struct drm_atomic_state *state)
+ {
+@@ -4823,10 +4799,6 @@ static int amdgpu_dm_atomic_check(struct
+ goto fail;
+
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+- ret = dm_atomic_check_plane_state_fb(state, crtc);
+- if (ret)
+- goto fail;
+-
+ if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
+ !new_crtc_state->color_mgmt_changed)
+ continue;
--- /dev/null
+From 1bc8ffbd71380661c5bc9cd65649bb0cf3d0cf09 Mon Sep 17 00:00:00 2001
+From: Harry Wentland <harry.wentland@amd.com>
+Date: Thu, 12 Apr 2018 10:51:51 -0400
+Subject: Revert "drm/amd/display: fix dereferencing possible ERR_PTR()"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Harry Wentland <harry.wentland@amd.com>
+
+commit 1bc8ffbd71380661c5bc9cd65649bb0cf3d0cf09 upstream.
+
+This reverts commit cd2d6c92a8e39d7e50a5af9fcc67d07e6a89e91d.
+
+Cc: Shirish S <shirish.s@amd.com>
+Cc: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
+Signed-off-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -4792,9 +4792,6 @@ static int dm_atomic_check_plane_state_f
+ return -EDEADLK;
+
+ crtc_state = drm_atomic_get_crtc_state(plane_state->state, crtc);
+- if (IS_ERR(crtc_state))
+- return PTR_ERR(crtc_state);
+-
+ if (crtc->primary == plane && crtc_state->active) {
+ if (!plane_state->fb)
+ return -EINVAL;
--- /dev/null
+From 2a872fa4e9c8adc79c830e4009e1cc0c013a9d8a Mon Sep 17 00:00:00 2001
+From: "Steven Rostedt (VMware)" <rostedt@goodmis.org>
+Date: Mon, 2 Apr 2018 10:33:56 -0400
+Subject: ring-buffer: Check if memory is available before allocation
+
+From: Steven Rostedt (VMware) <rostedt@goodmis.org>
+
+commit 2a872fa4e9c8adc79c830e4009e1cc0c013a9d8a upstream.
+
+The ring buffer is made up of a link list of pages. When making the ring
+buffer bigger, it will allocate all the pages it needs before adding to the
+ring buffer, and if it fails, it frees them and returns an error. This makes
+increasing the ring buffer size an all or nothing action. When this was
+first created, the pages were allocated with "NORETRY". This was to not
+cause any Out-Of-Memory (OOM) actions from allocating the ring buffer. But
+NORETRY was too strict, as the ring buffer would fail to expand even when
+there's memory available, but was taken up in the page cache.
+
+Commit 848618857d253 ("tracing/ring_buffer: Try harder to allocate") changed
+the allocating from NORETRY to RETRY_MAYFAIL. The RETRY_MAYFAIL would
+allocate from the page cache, but if there was no memory available, it would
+simple fail the allocation and not trigger an OOM.
+
+This worked fine, but had one problem. As the ring buffer would allocate one
+page at a time, it could take up all memory in the system before it failed
+to allocate and free that memory. If the allocation is happening and the
+ring buffer allocates all memory and then tries to take more than available,
+its allocation will not trigger an OOM, but if there's any allocation that
+happens someplace else, that could trigger an OOM, even though once the ring
+buffer's allocation fails, it would free up all the previous memory it tried
+to allocate, and allow other memory allocations to succeed.
+
+Commit d02bd27bd33dd ("mm/page_alloc.c: calculate 'available' memory in a
+separate function") separated out si_mem_availble() as a separate function
+that could be used to see how much memory is available in the system. Using
+this function to make sure that the ring buffer could be allocated before it
+tries to allocate pages we can avoid allocating all memory in the system and
+making it vulnerable to OOMs if other allocations are taking place.
+
+Link: http://lkml.kernel.org/r/1522320104-6573-1-git-send-email-zhaoyang.huang@spreadtrum.com
+
+CC: stable@vger.kernel.org
+Cc: linux-mm@kvack.org
+Fixes: 848618857d253 ("tracing/ring_buffer: Try harder to allocate")
+Requires: d02bd27bd33dd ("mm/page_alloc.c: calculate 'available' memory in a separate function")
+Reported-by: Zhaoyang Huang <huangzhaoyang@gmail.com>
+Tested-by: Joel Fernandes <joelaf@google.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ kernel/trace/ring_buffer.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/kernel/trace/ring_buffer.c
++++ b/kernel/trace/ring_buffer.c
+@@ -1136,6 +1136,11 @@ static int __rb_allocate_pages(long nr_p
+ struct buffer_page *bpage, *tmp;
+ long i;
+
++ /* Check if the available memory is there first */
++ i = si_mem_available();
++ if (i < nr_pages)
++ return -ENOMEM;
++
+ for (i = 0; i < nr_pages; i++) {
+ struct page *page;
+ /*
libnvdimm-dimm-fix-dpa-reservation-vs-uninitialized-label-area.patch
libnvdimm-namespace-use-a-safe-lookup-for-dimm-device-name.patch
vsprintf-do-not-preprocess-non-dereferenced-pointers-for-bprintf-px-and-pk.patch
+nfit-address-range-scrub-fix-scrub-in-progress-reporting.patch
+nfit-skip-region-registration-for-incomplete-control-regions.patch
+ring-buffer-check-if-memory-is-available-before-allocation.patch
+um-compile-with-modern-headers.patch
+um-use-posix-ucontext_t-instead-of-struct-ucontext.patch
+iommu-vt-d-fix-a-potential-memory-leak.patch
+mmc-core-prevent-bus-reference-leak-in-mmc_blk_init.patch
+mmc-jz4740-fix-race-condition-in-irq-mask-update.patch
+mmc-tmio-fix-error-handling-when-issuing-cmd23.patch
+revert-drm-amd-display-fix-dereferencing-possible-err_ptr.patch
+revert-drm-amd-display-disable-crtcs-with-null-fb-on-their-primary-plane-v2.patch
+drm-amd-display-hdmi-has-no-sound-after-panel-power-off-on.patch
+trace_uprobe-use-lx-to-display-offset.patch
+pci-mark-broadcom-ht1100-and-ht2000-root-port-extended-tags-as-broken.patch
+clk-mvebu-armada-38x-add-support-for-missing-clocks.patch
+clk-fix-false-positive-wmaybe-uninitialized-warning.patch
+clk-mediatek-fix-pwm-clock-source-by-adding-a-fixed-factor-clock.patch
+clk-bcm2835-de-assert-assert-pll-reset-signal-when-appropriate.patch
+clk-tegra-mark-hclk-sclk-and-emc-as-critical.patch
+pwm-rcar-fix-a-condition-to-prevent-mismatch-value-setting-to-duty.patch
+pwm-mediatek-fix-up-pwm4-and-pwm5-malfunction-on-mt7623.patch
+pwm-mediatek-improve-precision-in-rate-calculation.patch
+thermal-imx-fix-race-condition-in-imx_thermal_probe.patch
+dt-bindings-clock-mediatek-add-binding-for-fixed-factor-clock-axisel_d4.patch
+watchdog-f71808e_wdt-fix-wd_en-register-read.patch
--- /dev/null
+From cf1ba1d73a33944d8c1a75370a35434bf146b8a7 Mon Sep 17 00:00:00 2001
+From: Mikhail Lappo <mikhail.lappo@esrlabs.com>
+Date: Fri, 2 Feb 2018 16:17:46 -0200
+Subject: thermal: imx: Fix race condition in imx_thermal_probe()
+
+From: Mikhail Lappo <mikhail.lappo@esrlabs.com>
+
+commit cf1ba1d73a33944d8c1a75370a35434bf146b8a7 upstream.
+
+When device boots with T > T_trip_1 and requests interrupt,
+the race condition takes place. The interrupt comes before
+THERMAL_DEVICE_ENABLED is set. This leads to an attempt to
+reading sensor value from irq and disabling the sensor, based on
+the data->mode field, which expected to be THERMAL_DEVICE_ENABLED,
+but still stays as THERMAL_DEVICE_DISABLED. Afher this issue
+sensor is never re-enabled, as the driver state is wrong.
+
+Fix this problem by setting the 'data' members prior to
+requesting the interrupts.
+
+Fixes: 37713a1e8e4c ("thermal: imx: implement thermal alarm interrupt handling")
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Mikhail Lappo <mikhail.lappo@esrlabs.com>
+Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
+Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
+Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
+Signed-off-by: Zhang Rui <rui.zhang@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/thermal/imx_thermal.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/imx_thermal.c
++++ b/drivers/thermal/imx_thermal.c
+@@ -637,6 +637,9 @@ static int imx_thermal_probe(struct plat
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
+
++ data->irq_enabled = true;
++ data->mode = THERMAL_DEVICE_ENABLED;
++
+ ret = devm_request_threaded_irq(&pdev->dev, data->irq,
+ imx_thermal_alarm_irq, imx_thermal_alarm_irq_thread,
+ 0, "imx_thermal", data);
+@@ -649,9 +652,6 @@ static int imx_thermal_probe(struct plat
+ return ret;
+ }
+
+- data->irq_enabled = true;
+- data->mode = THERMAL_DEVICE_ENABLED;
+-
+ return 0;
+ }
+
--- /dev/null
+From 18d45b11d96e6f9b3814960a1394083a3d6b7f74 Mon Sep 17 00:00:00 2001
+From: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
+Date: Thu, 15 Mar 2018 13:57:55 +0530
+Subject: trace_uprobe: Use %lx to display offset
+
+From: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
+
+commit 18d45b11d96e6f9b3814960a1394083a3d6b7f74 upstream.
+
+tu->offset is unsigned long, not a pointer, thus %lx should
+be used to print it, not the %px.
+
+Link: http://lkml.kernel.org/r/20180315082756.9050-1-ravi.bangoria@linux.vnet.ibm.com
+
+Cc: stable@vger.kernel.org
+Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
+Fixes: 0e4d819d0893 ("trace_uprobe: Display correct offset in uprobe_events")
+Suggested-by: Kees Cook <keescook@chromium.org>
+Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
+Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ kernel/trace/trace_uprobe.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/kernel/trace/trace_uprobe.c
++++ b/kernel/trace/trace_uprobe.c
+@@ -608,7 +608,7 @@ static int probes_seq_show(struct seq_fi
+
+ /* Don't print "0x (null)" when offset is 0 */
+ if (tu->offset) {
+- seq_printf(m, "0x%px", (void *)tu->offset);
++ seq_printf(m, "0x%0*lx", (int)(sizeof(void *) * 2), tu->offset);
+ } else {
+ switch (sizeof(void *)) {
+ case 4:
--- /dev/null
+From 530ba6c7cb3c22435a4d26de47037bb6f86a5329 Mon Sep 17 00:00:00 2001
+From: "Jason A. Donenfeld" <Jason@zx2c4.com>
+Date: Thu, 14 Dec 2017 03:23:37 +0100
+Subject: um: Compile with modern headers
+
+From: Jason A. Donenfeld <Jason@zx2c4.com>
+
+commit 530ba6c7cb3c22435a4d26de47037bb6f86a5329 upstream.
+
+Recent libcs have gotten a bit more strict, so we actually need to
+include the right headers and use the right types. This enables UML to
+compile again.
+
+Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Richard Weinberger <richard@nod.at>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/um/os-Linux/file.c | 1 +
+ arch/um/os-Linux/signal.c | 1 +
+ arch/x86/um/stub_segv.c | 1 +
+ 3 files changed, 3 insertions(+)
+
+--- a/arch/um/os-Linux/file.c
++++ b/arch/um/os-Linux/file.c
+@@ -12,6 +12,7 @@
+ #include <sys/mount.h>
+ #include <sys/socket.h>
+ #include <sys/stat.h>
++#include <sys/sysmacros.h>
+ #include <sys/un.h>
+ #include <sys/types.h>
+ #include <os.h>
+--- a/arch/um/os-Linux/signal.c
++++ b/arch/um/os-Linux/signal.c
+@@ -16,6 +16,7 @@
+ #include <os.h>
+ #include <sysdep/mcontext.h>
+ #include <um_malloc.h>
++#include <sys/ucontext.h>
+
+ void (*sig_info[NSIG])(int, struct siginfo *, struct uml_pt_regs *) = {
+ [SIGTRAP] = relay_signal,
+--- a/arch/x86/um/stub_segv.c
++++ b/arch/x86/um/stub_segv.c
+@@ -6,6 +6,7 @@
+ #include <sysdep/stub.h>
+ #include <sysdep/faultinfo.h>
+ #include <sysdep/mcontext.h>
++#include <sys/ucontext.h>
+
+ void __attribute__ ((__section__ (".__syscall_stub")))
+ stub_segv_handler(int sig, siginfo_t *info, void *p)
--- /dev/null
+From 4d1a535b8ec5e74b42dfd9dc809142653b2597f6 Mon Sep 17 00:00:00 2001
+From: Krzysztof Mazur <krzysiek@podlesie.net>
+Date: Wed, 15 Nov 2017 11:12:39 +0100
+Subject: um: Use POSIX ucontext_t instead of struct ucontext
+
+From: Krzysztof Mazur <krzysiek@podlesie.net>
+
+commit 4d1a535b8ec5e74b42dfd9dc809142653b2597f6 upstream.
+
+glibc 2.26 removed the 'struct ucontext' to "improve" POSIX compliance
+and break programs, including User Mode Linux. Fix User Mode Linux
+by using POSIX ucontext_t.
+
+This fixes:
+
+arch/um/os-Linux/signal.c: In function 'hard_handler':
+arch/um/os-Linux/signal.c:163:22: error: dereferencing pointer to incomplete type 'struct ucontext'
+ mcontext_t *mc = &uc->uc_mcontext;
+arch/x86/um/stub_segv.c: In function 'stub_segv_handler':
+arch/x86/um/stub_segv.c:16:13: error: dereferencing pointer to incomplete type 'struct ucontext'
+ &uc->uc_mcontext);
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Krzysztof Mazur <krzysiek@podlesie.net>
+Signed-off-by: Richard Weinberger <richard@nod.at>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/um/os-Linux/signal.c | 2 +-
+ arch/x86/um/stub_segv.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/um/os-Linux/signal.c
++++ b/arch/um/os-Linux/signal.c
+@@ -160,7 +160,7 @@ static void (*handlers[_NSIG])(int sig,
+
+ static void hard_handler(int sig, siginfo_t *si, void *p)
+ {
+- struct ucontext *uc = p;
++ ucontext_t *uc = p;
+ mcontext_t *mc = &uc->uc_mcontext;
+ unsigned long pending = 1UL << sig;
+
+--- a/arch/x86/um/stub_segv.c
++++ b/arch/x86/um/stub_segv.c
+@@ -11,7 +11,7 @@
+ void __attribute__ ((__section__ (".__syscall_stub")))
+ stub_segv_handler(int sig, siginfo_t *info, void *p)
+ {
+- struct ucontext *uc = p;
++ ucontext_t *uc = p;
+
+ GET_FAULTINFO_FROM_MC(*((struct faultinfo *) STUB_DATA),
+ &uc->uc_mcontext);
--- /dev/null
+From 977f6f68331f94bb72ad84ee96b7b87ce737d89d Mon Sep 17 00:00:00 2001
+From: Igor Pylypiv <igor.pylypiv@gmail.com>
+Date: Tue, 6 Mar 2018 23:47:25 -0800
+Subject: watchdog: f71808e_wdt: Fix WD_EN register read
+
+From: Igor Pylypiv <igor.pylypiv@gmail.com>
+
+commit 977f6f68331f94bb72ad84ee96b7b87ce737d89d upstream.
+
+F71808FG_FLAG_WD_EN defines bit position, not a bitmask
+
+Signed-off-by: Igor Pylypiv <igor.pylypiv@gmail.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+Cc: stable <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/watchdog/f71808e_wdt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/watchdog/f71808e_wdt.c
++++ b/drivers/watchdog/f71808e_wdt.c
+@@ -496,7 +496,7 @@ static bool watchdog_is_running(void)
+
+ is_running = (superio_inb(watchdog.sioaddr, SIO_REG_ENABLE) & BIT(0))
+ && (superio_inb(watchdog.sioaddr, F71808FG_REG_WDT_CONF)
+- & F71808FG_FLAG_WD_EN);
++ & BIT(F71808FG_FLAG_WD_EN));
+
+ superio_exit(watchdog.sioaddr);
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
