RISC-V: Add patterns for vector-scalar IEEE floating-point max

These patterns enable the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into an unspec_vfmax RTL instruction.

Before this patch, we have two instructions, e.g.:
  vfmv.v.f       v2,fa0
  vfmax.vv       v1,v2,v1

After, we get only one:
  vfmax.vf       v1,v1,fa0

In some cases, it also shaves off one vsetvli.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*vfmin_vf_ieee_<mode>): Rename into...
	(*v<ieee_fmaxmin_op>_vf_<mode>): New pattern to combine vec_duplicate +
	vf{max,min}.vv (unspec) into vf{max,min}.vf.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c: Add vfmax.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c: Add vfmax. Also add
	missing -fno-fast-math.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c: Likewise.

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 328ee0e096fe46a33e3ad9576450ba95ad7b037d..d2a89a5d63b4da0356fa9f1efaec702ed74190f0 100644 (file)
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -2107,38 +2107,40 @@
   [(set_attr "type" "vfminmax")]
 )
 
-(define_insn_and_split "*vfmin_vf_ieee_<mode>"
+(define_insn_and_split "*v<ieee_fmaxmin_op>_vf_<mode>"
   [(set (match_operand:V_VLSF 0 "register_operand")
     (unspec:V_VLSF [
       (vec_duplicate:V_VLSF
        (match_operand:<VEL> 2 "register_operand"))
       (match_operand:V_VLSF 1 "register_operand")
-      ] UNSPEC_VFMIN))]
+      ] UNSPEC_VFMAXMIN))]
   "TARGET_VECTOR && !HONOR_SNANS (<MODE>mode) && can_create_pseudo_p ()"
   "#"
   "&& 1"
   [(const_int 0)]
   {
-    riscv_vector::emit_vlmax_insn (code_for_pred_scalar (UNSPEC_VFMIN, <MODE>mode),
+    riscv_vector::emit_vlmax_insn (code_for_pred_scalar (<IEEE_FMAXMIN_OP>,
+                                                        <MODE>mode),
                                   riscv_vector::BINARY_OP, operands);
     DONE;
   }
   [(set_attr "type" "vfminmax")]
 )
 
-(define_insn_and_split "*vfmin_vf_ieee_<mode>"
+(define_insn_and_split "*v<ieee_fmaxmin_op>_vf_<mode>"
   [(set (match_operand:V_VLSF 0 "register_operand")
     (unspec:V_VLSF [
       (match_operand:V_VLSF 1 "register_operand")
       (vec_duplicate:V_VLSF
        (match_operand:<VEL> 2 "register_operand"))
-      ] UNSPEC_VFMIN))]
+      ] UNSPEC_VFMAXMIN))]
   "TARGET_VECTOR && !HONOR_SNANS (<MODE>mode) && can_create_pseudo_p ()"
   "#"
   "&& 1"
   [(const_int 0)]
   {
-    riscv_vector::emit_vlmax_insn (code_for_pred_scalar (UNSPEC_VFMIN, <MODE>mode),
+    riscv_vector::emit_vlmax_insn (code_for_pred_scalar (<IEEE_FMAXMIN_OP>,
+                                                        <MODE>mode),
                                   riscv_vector::BINARY_OP, operands);
     DONE;
   }

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c
index 1a20ee78536be718faaa40ee9e1aff01a5d97d94..ba8eec0bb7ce9d69fc6f981b50689705c0199331 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c
@@ -4,5 +4,7 @@
 #include "vf_binop.h"
 
 DEF_VF_BINOP_CASE_2_WRAP (_Float16, __builtin_fminf16, min)
+DEF_VF_BINOP_CASE_2_WRAP (_Float16, __builtin_fmaxf16, max)
 
 /* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmax.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c
index 1e0f7f5cb154f2a246b53f5cf7210184fe930e8d..b5a1991ab8999ed7bf9629d01a1b456a579bbfe3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c
@@ -4,5 +4,7 @@
 #include "vf_binop.h"
 
 DEF_VF_BINOP_CASE_2_WRAP (float, __builtin_fminf, min)
+DEF_VF_BINOP_CASE_2_WRAP (float, __builtin_fmaxf, max)
 
 /* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmax.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c
index 61db2df4521ae166affba91f3b73e47b385d4662..a6fc781d87a83013e23029c6b6d4b3ba6b75439e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c
@@ -4,5 +4,7 @@
 #include "vf_binop.h"
 
 DEF_VF_BINOP_CASE_2_WRAP (double, __builtin_fmin, min)
+DEF_VF_BINOP_CASE_2_WRAP (double, __builtin_fmax, max)
 
 /* { dg-final { scan-assembler-times {vfmin.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmax.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c
index 392580abddcc3305373657d9e3040497d6b9338b..afd64e78072a23afd48fb60d7b0fecc4d105ee6e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c
@@ -4,3 +4,4 @@
 #include "vf-5-f16.c"
 
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c
index 9dbd226c04287fd7e25d83edd5211b9c4e1e900d..edcecffdf0617367f6754f2d5655d29e83b0d23b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c
@@ -4,3 +4,4 @@
 #include "vf-5-f32.c"
 
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c
index 44a17cd1ff6a5c852bc22f3484959698576517d4..fafaa254cd9aebc55f60626d8fb8126689499128 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c
@@ -4,3 +4,4 @@
 #include "vf-5-f64.c"
 
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c
index 0883c882201ac432c1a6d304b52c9b18c18d760f..362fdfa69c0fce69f5f6ccd8d9cf575afc501d7a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c
@@ -3,6 +3,10 @@
 
 #include "vf_binop.h"
 
-DEF_VF_BINOP_CASE_3_WRAP (_Float16, __builtin_fminf16, min, VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (_Float16, __builtin_fminf16, min,
+                         VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (_Float16, __builtin_fmaxf16, max,
+                         VF_BINOP_FUNC_BODY_X128)
 
 /* { dg-final { scan-assembler {vfmin.vf} } } */
+/* { dg-final { scan-assembler {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c
index 85282404ad27120d6960306677a034c167148904..2944a35451d35b9a8adf3447bf7c70132cf0d0be 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c
@@ -4,5 +4,7 @@
 #include "vf_binop.h"
 
 DEF_VF_BINOP_CASE_3_WRAP (float, __builtin_fminf, min, VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (float, __builtin_fmaxf, max, VF_BINOP_FUNC_BODY_X128)
 
 /* { dg-final { scan-assembler {vfmin.vf} } } */
+/* { dg-final { scan-assembler {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c
index 474b33900ce83c90bd883b4fde5046cc0e286190..f785f85582021019cd42d98494a7ff6a7a93d52b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c
@@ -4,5 +4,7 @@
 #include "vf_binop.h"
 
 DEF_VF_BINOP_CASE_3_WRAP (double, __builtin_fmin, min, VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (double, __builtin_fmax, max, VF_BINOP_FUNC_BODY_X128)
 
 /* { dg-final { scan-assembler {vfmin.vf} } } */
+/* { dg-final { scan-assembler {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c
index bd68b3cdf2204f7ec78a12e1f9ddf90612d2bd8b..5c91c88a920acfd68d07ff26740f4b441fdf927f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=4" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=4" } */
 
 #include "vf-7-f16.c"
 
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c
index 000402c1520bf947e33fd8a246354366b8ecb3bd..13237f12897954b669038436c5fe645101779a20 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=4" } */
 
 #include "vf-7-f32.c"
 
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c
index 89dec81fba4ce2ef70a9826c35bc22eede993dec..109913c4290bc4b9f6974534bb0cda6aa6414ffa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -fno-fast-math --param=fpr2vr-cost=4" } */
 
 #include "vf-7-f64.c"
 
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */