]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
wifi: iwlwifi: add support for external 32 KHz clock
authorEmmanuel Grumbach <emmanuel.grumbach@intel.com>
Wed, 12 Feb 2025 05:43:27 +0000 (07:43 +0200)
committerJohannes Berg <johannes.berg@intel.com>
Wed, 26 Feb 2025 14:48:54 +0000 (15:48 +0100)
In case the BIOS allows it, instruct the firmware to use the external 32
KHz clock.
The op mode specific implementation (i.e. reading the BIOS table) will
come in a later patch.

Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
Link: https://patch.msgid.link/20250212073923.9aae3f74fee0.I25ae45ef02b9ea387b512f974c1f3e5367a537e5@changeid
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h
drivers/net/wireless/intel/iwlwifi/iwl-trans.h
drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c

index cd25a1b9f2ff424f4db0f8aad9a81d8c43566fa5..20563a32a21a840b37e4c8bc4fee2670e9097191 100644 (file)
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2018, 2020-2024 Intel Corporation
+ * Copyright (C) 2018, 2020-2025 Intel Corporation
  */
 #ifndef __iwl_context_info_file_gen3_h__
 #define __iwl_context_info_file_gen3_h__
@@ -80,10 +80,12 @@ enum iwl_prph_scratch_flags {
  * enum iwl_prph_scratch_ext_flags - PRPH scratch control ext flags
  * @IWL_PRPH_SCRATCH_EXT_URM_FW: switch to URM mode based on fw setting
  * @IWL_PRPH_SCRATCH_EXT_URM_PERM: switch to permanent URM mode
+ * @IWL_PRPH_SCRATCH_EXT_32KHZ_CLK_VALID: use external 32 KHz clock
  */
 enum iwl_prph_scratch_ext_flags {
-       IWL_PRPH_SCRATCH_EXT_URM_FW     = BIT(4),
-       IWL_PRPH_SCRATCH_EXT_URM_PERM   = BIT(5),
+       IWL_PRPH_SCRATCH_EXT_URM_FW             = BIT(4),
+       IWL_PRPH_SCRATCH_EXT_URM_PERM           = BIT(5),
+       IWL_PRPH_SCRATCH_EXT_32KHZ_CLK_VALID    = BIT(8),
 };
 
 /**
index 021691513a576798e1c9fa3cbaeac9369f385df2..25fb4c50e38b1f8e1a2c773fa906a039f65f83d6 100644 (file)
@@ -888,6 +888,7 @@ struct iwl_txq {
  * @trans_specific: data for the specific transport this is allocated for/with
  * @dsbr_urm_fw_dependent: switch to URM based on fw settings
  * @dsbr_urm_permanent: switch to URM permanently
+ * @ext_32khz_clock_valid: if true, the external 32 KHz clock can be used
  */
 struct iwl_trans {
        bool csme_own;
@@ -916,6 +917,8 @@ struct iwl_trans {
        u8 dsbr_urm_fw_dependent:1,
           dsbr_urm_permanent:1;
 
+       bool ext_32khz_clock_valid;
+
        u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size;
 
        bool pm_support;
index 838c426db7f05397f1dcc28a62c3b7be5f303fc5..8aa7c455bdee306c5f8347533720371d58ba3dce 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2018-2024 Intel Corporation
+ * Copyright (C) 2018-2025 Intel Corporation
  */
 #include <linux/dmi.h>
 #include "iwl-trans.h"
@@ -137,6 +137,9 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
        if (trans->dsbr_urm_permanent)
                control_flags_ext |= IWL_PRPH_SCRATCH_EXT_URM_PERM;
 
+       if (trans->ext_32khz_clock_valid)
+               control_flags_ext |= IWL_PRPH_SCRATCH_EXT_32KHZ_CLK_VALID;
+
        /* Allocate prph scratch */
        prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
                                          &trans_pcie->prph_scratch_dma_addr,