drm/xe: Track maximum GTs per tile on a per-platform basis

Today all of our platforms fall into one of three cases:
 * Single tile platforms with a single (primary) GT
 * Single tile platforms with two GTs (primary + media)
 * Two-tile platforms with a single GT (primary) in each

Our numbering of GTs has been a bit inconsistent between platforms
(e.g., GT1 is the media GT on some platforms, but the second tile's
primary GT on others).  In the future we'll likely have platforms that
are both multi-tile and multi-GT, which will make the situation more
confusing.  We could also wind up with more than just two types of GTs
at some point in the future.

Going forward we should standardize the way we assign uapi GT IDs to
internal GT structures.  Let's declare that for userspace GT ID n,

  GT[n]'s tile             = n / (max gt per tile)
  GT[n]'s slot within tile = n % (max gt per tile)

We don't want the GT numbering to change for any of our current
platforms since the current IDs are part of our ABI contract with
userspace so this means we should track the 'max gt per tile' value on a
per-platform basis rather than just using a single value across the
driver.  Encode this into device descriptors in xe_pci.c and use the
per-platform number for various checks in the code.  Constant
XE_MAX_GT_PER_TILE will remain just as the maximum across all platforms
for easy of sizing array allocations.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20250701201320.2514369-12-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index e4da797a984b59b41f4d0441538ac7edb9f1a64c..4e719d398c8826a1276ce36ef605887efc0d6ded 100644 (file)
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -60,35 +60,32 @@ static inline struct xe_tile *xe_device_get_root_tile(struct xe_device *xe)
        return &xe->tiles[0];
 }
 
+/*
+ * Highest GT/tile count for any platform.  Used only for memory allocation
+ * sizing.  Any logic looping over GTs or mapping userspace GT IDs into GT
+ * structures should use the per-platform xe->info.max_gt_per_tile instead.
+ */
 #define XE_MAX_GT_PER_TILE 2
 
-static inline struct xe_gt *xe_tile_get_gt(struct xe_tile *tile, u8 gt_id)
-{
-       if (drm_WARN_ON(&tile_to_xe(tile)->drm, gt_id >= XE_MAX_GT_PER_TILE))
-               gt_id = 0;
-
-       return gt_id ? tile->media_gt : tile->primary_gt;
-}
-
 static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
 {
-       struct xe_tile *root_tile = xe_device_get_root_tile(xe);
+       struct xe_tile *tile;
        struct xe_gt *gt;
 
-       /*
-        * FIXME: This only works for now because multi-tile and standalone
-        * media are mutually exclusive on the platforms we have today.
-        *
-        * id => GT mapping may change once we settle on how we want to handle
-        * our UAPI.
-        */
-       if (MEDIA_VER(xe) >= 13) {
-               gt = xe_tile_get_gt(root_tile, gt_id);
-       } else {
-               if (drm_WARN_ON(&xe->drm, gt_id >= XE_MAX_TILES_PER_DEVICE))
-                       gt_id = 0;
-
-               gt = xe->tiles[gt_id].primary_gt;
+       if (gt_id >= xe->info.tile_count * xe->info.max_gt_per_tile)
+               return NULL;
+
+       tile = &xe->tiles[gt_id / xe->info.max_gt_per_tile];
+       switch (gt_id % xe->info.max_gt_per_tile) {
+       default:
+               xe_assert(xe, false);
+               fallthrough;
+       case 0:
+               gt = tile->primary_gt;
+               break;
+       case 1:
+               gt = tile->media_gt;
+               break;
        }
 
        if (!gt)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 7e4f6d846af65b3f21c701083cf5a2771c22a7d8..78c4acafd268b797e28bb885be88c4f5d9b485e5 100644 (file)
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -294,6 +294,8 @@ struct xe_device {
                u8 vram_flags;
                /** @info.tile_count: Number of tiles */
                u8 tile_count;
+               /** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */
+               u8 max_gt_per_tile;
                /** @info.gt_count: Total number of GTs for entire device */
                u8 gt_count;
                /** @info.vm_max_level: Max VM level */

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 08e21d4099e0c62f2e8bc85a7cba32fa56a098eb..ace910e4a1d26b8072d4b1a16a8e1932faa20d19 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -57,6 +57,7 @@ struct xe_device_desc {
 
        u8 dma_mask_size;
        u8 max_remote_tiles:2;
+       u8 max_gt_per_tile:2;
 
        u8 require_force_probe:1;
        u8 is_dgfx:1;
@@ -208,6 +209,7 @@ static const struct xe_device_desc tgl_desc = {
        .dma_mask_size = 39,
        .has_display = true,
        .has_llc = true,
+       .max_gt_per_tile = 1,
        .require_force_probe = true,
 };
 
@@ -218,6 +220,7 @@ static const struct xe_device_desc rkl_desc = {
        .dma_mask_size = 39,
        .has_display = true,
        .has_llc = true,
+       .max_gt_per_tile = 1,
        .require_force_probe = true,
 };
 
@@ -230,6 +233,7 @@ static const struct xe_device_desc adl_s_desc = {
        .dma_mask_size = 39,
        .has_display = true,
        .has_llc = true,
+       .max_gt_per_tile = 1,
        .require_force_probe = true,
        .subplatforms = (const struct xe_subplatform_desc[]) {
                { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
@@ -246,6 +250,7 @@ static const struct xe_device_desc adl_p_desc = {
        .dma_mask_size = 39,
        .has_display = true,
        .has_llc = true,
+       .max_gt_per_tile = 1,
        .require_force_probe = true,
        .subplatforms = (const struct xe_subplatform_desc[]) {
                { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
@@ -260,6 +265,7 @@ static const struct xe_device_desc adl_n_desc = {
        .dma_mask_size = 39,
        .has_display = true,
        .has_llc = true,
+       .max_gt_per_tile = 1,
        .require_force_probe = true,
 };
 
@@ -275,6 +281,7 @@ static const struct xe_device_desc dg1_desc = {
        .has_display = true,
        .has_gsc_nvm = 1,
        .has_heci_gscfi = 1,
+       .max_gt_per_tile = 1,
        .require_force_probe = true,
 };
 
@@ -298,6 +305,7 @@ static const struct xe_device_desc ats_m_desc = {
        .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
        .pre_gmdid_media_ip = &media_ip_xehpm,
        .dma_mask_size = 46,
+       .max_gt_per_tile = 1,
        .require_force_probe = true,
 
        DG2_FEATURES,
@@ -308,6 +316,7 @@ static const struct xe_device_desc dg2_desc = {
        .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
        .pre_gmdid_media_ip = &media_ip_xehpm,
        .dma_mask_size = 46,
+       .max_gt_per_tile = 1,
        .require_force_probe = true,
 
        DG2_FEATURES,
@@ -324,6 +333,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
        .has_display = false,
        .has_gsc_nvm = 1,
        .has_heci_gscfi = 1,
+       .max_gt_per_tile = 1,
        .max_remote_tiles = 1,
        .require_force_probe = true,
        .has_mbx_power_limits = false,
@@ -336,6 +346,7 @@ static const struct xe_device_desc mtl_desc = {
        .dma_mask_size = 46,
        .has_display = true,
        .has_pxp = true,
+       .max_gt_per_tile = 2,
 };
 
 static const struct xe_device_desc lnl_desc = {
@@ -343,6 +354,7 @@ static const struct xe_device_desc lnl_desc = {
        .dma_mask_size = 46,
        .has_display = true,
        .has_pxp = true,
+       .max_gt_per_tile = 2,
        .needs_scratch = true,
 };
 
@@ -355,6 +367,7 @@ static const struct xe_device_desc bmg_desc = {
        .has_mbx_power_limits = true,
        .has_gsc_nvm = 1,
        .has_heci_cscfi = 1,
+       .max_gt_per_tile = 2,
        .needs_scratch = true,
 };
 
@@ -363,6 +376,7 @@ static const struct xe_device_desc ptl_desc = {
        .dma_mask_size = 46,
        .has_display = true,
        .has_sriov = true,
+       .max_gt_per_tile = 2,
        .require_force_probe = true,
        .needs_scratch = true,
 };
@@ -611,6 +625,10 @@ static int xe_info_init_early(struct xe_device *xe,
        xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
                                 xe_modparam.probe_display &&
                                 desc->has_display;
+
+       xe_assert(xe, desc->max_gt_per_tile > 0);
+       xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE);
+       xe->info.max_gt_per_tile = desc->max_gt_per_tile;
        xe->info.tile_count = 1 + desc->max_remote_tiles;
 
        err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0);

diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index e8e1743dcb1e06cbd77752d03ca7876a52ea7ee7..e615b091621777bd021ec5b86d44f45a01cac145 100644 (file)
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -141,7 +141,7 @@ query_engine_cycles(struct xe_device *xe,
                return -EINVAL;
 
        eci = &resp.eci;
-       if (eci->gt_id >= XE_MAX_GT_PER_TILE)
+       if (eci->gt_id >= xe->info.max_gt_per_tile)
                return -EINVAL;
 
        gt = xe_device_get_gt(xe, eci->gt_id);