clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP

Add clocks, resets and power domains for ADC IP available on the Renesas
RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20241206111337.726244-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index 559afc417c6c4b342ac64e62e9962b2abb1f0009..0e7e3bf05b52d1ce6f4b626dba75456b088f4dd5 100644 (file)
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -187,6 +187,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
        DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
        DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),
        DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2),
+       DEF_FIXED("TSU", R9A08G045_CLK_TSU, CLK_PLL2_DIV2, 1, 8),
 };
 
 static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
@@ -238,6 +239,8 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
        DEF_MOD("scif4_clk_pck",        R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4),
        DEF_MOD("scif5_clk_pck",        R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5),
        DEF_MOD("gpio_hclk",            R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
+       DEF_MOD("adc_adclk",            R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0),
+       DEF_MOD("adc_pclk",             R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1),
        DEF_MOD("vbat_bclk",            R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
 };
 
@@ -274,6 +277,8 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
        DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
        DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
        DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
+       DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0),
+       DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1),
        DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
 };
 
@@ -346,6 +351,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
                                DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(5)), 0),
        DEF_PD("scif5",         R9A08G045_PD_SCIF5,
                                DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0),
+       DEF_PD("adc",           R9A08G045_PD_ADC,
+                               DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0),
        DEF_PD("vbat",          R9A08G045_PD_VBAT,
                                DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
                                GENPD_FLAG_ALWAYS_ON),