aarch64: Add missing FEAT_MEC dc encodings and gate sysregs

FEAT_MEC support was introduced in [1]. However, the dc instruction was
missing these encodings:
- DC CIPAE
- DC CIGDPAE

Furthermore, the Arm ARM states that FEAT_MEC is an optional extension,
introduced for v9.2-a.
Therefore, these sysregs:
- MECIDR_EL2
- MECID_P0_EL2
- MECID_A0_EL2
- MECID_P1_EL2
- MECID_A1_EL2
- VMECID_P_EL2
- VMECID_A_EL2
- MECID_RL_A_EL3

which were introduced in that commit now require -march=armv9.2-a at the very
least to be enabled, as well as the dc encodings.

opcodes/ChangeLog:
	* aarch64-opc.c (aarch64_sys_regs_dc): Add "cipae" and "cigdpae".
	* aarch64-sys-regs.def: Add V8_7A as a requirement for the above system
	registers.

gas/testsuite/gas/ChangeLog
	* aarch64/mec-invalid.s: Add .arch directive.
	* aarch64/mec.d: Add .arch directive and check for cipae, cigdpae.
	* aarch64/mec.s: Add MEC data cache operations test.
	* aarch64/mec-arch-bad.d: New test to check for bad arch version.
	* aarch64/mec-arch-bad.l: Above.

[1]: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=31f2faf5cf112931cfb8c0564a2b78477c907fe3

Regression tested on aarch64-none-elf

diff --git a/gas/testsuite/gas/aarch64/mec-arch-bad.d b/gas/testsuite/gas/aarch64/mec-arch-bad.d
new file mode 100644 (file)
index 0000000..d2e6416
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mec-arch-bad.d
@@ -0,0 +1,4 @@
+#name: MEC unavailable for architecture below armv9.2-a
+#as: -march=armv9.1-a
+#source: mec.s
+#error_output: mec-arch-bad.l

diff --git a/gas/testsuite/gas/aarch64/mec-arch-bad.l b/gas/testsuite/gas/aarch64/mec-arch-bad.l
new file mode 100644 (file)
index 0000000..9025dba
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/mec-arch-bad.l
@@ -0,0 +1,18 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support system register name 'mecidr_el2'
+.*: Error: selected processor does not support system register name 'mecid_p0_el2'
+.*: Error: selected processor does not support system register name 'mecid_a0_el2'
+.*: Error: selected processor does not support system register name 'mecid_p1_el2'
+.*: Error: selected processor does not support system register name 'mecid_a1_el2'
+.*: Error: selected processor does not support system register name 'vmecid_p_el2'
+.*: Error: selected processor does not support system register name 'vmecid_a_el2'
+.*: Error: selected processor does not support system register name 'mecid_rl_a_el3'
+.*: Error: selected processor does not support system register name 'mecid_p0_el2'
+.*: Error: selected processor does not support system register name 'mecid_a0_el2'
+.*: Error: selected processor does not support system register name 'mecid_p1_el2'
+.*: Error: selected processor does not support system register name 'mecid_a1_el2'
+.*: Error: selected processor does not support system register name 'vmecid_p_el2'
+.*: Error: selected processor does not support system register name 'vmecid_a_el2'
+.*: Error: selected processor does not support system register name 'mecid_rl_a_el3'
+.*: Error: selected processor does not support system register name 'cipae'
+.*: Error: selected processor does not support system register name 'cigdpae'

diff --git a/gas/testsuite/gas/aarch64/mec-invalid.s b/gas/testsuite/gas/aarch64/mec-invalid.s
index 9f7f1cd9fb210fbd7503760e48a125feeb411308..89917ab09213881b14f788080f9faa60a8ed6857 100644 (file)
--- a/gas/testsuite/gas/aarch64/mec-invalid.s
+++ b/gas/testsuite/gas/aarch64/mec-invalid.s
@@ -1,4 +1,6 @@
 // Memory Encryption Contexts, an extension of RME.
 
+.arch armv9.2-a
+
 // Illegal write to MEC system registers.
 msr mecidr_el2, x0

diff --git a/gas/testsuite/gas/aarch64/mec.d b/gas/testsuite/gas/aarch64/mec.d
index 118575d642b8581c5b95a4cb7f4d1b9c6e73d075..070f831a300a3e91547ede7652cdba6fad95e32d 100644 (file)
--- a/gas/testsuite/gas/aarch64/mec.d
+++ b/gas/testsuite/gas/aarch64/mec.d
@@ -1,4 +1,5 @@
 #name: MEC System registers
+#as: -march=armv9.2-a
 #objdump: -dr
 
 .*:     file format .*
@@ -22,3 +23,5 @@ Disassembly of section .text:
 [^:]*: d51ca900        msr     vmecid_p_el2, x0
 [^:]*: d51ca920        msr     vmecid_a_el2, x0
 [^:]*: d51eaa20        msr     mecid_rl_a_el3, x0
+[^:]*: d50c7e00        dc      cipae, x0
+[^:]*: d50c7ee0        dc      cigdpae, x0

diff --git a/gas/testsuite/gas/aarch64/mec.s b/gas/testsuite/gas/aarch64/mec.s
index d89a2748d9b913e00353af9ca08812afc3db4eb6..c5fb380cd4ab84f9c6e70f96fbbd224842ce21f6 100644 (file)
--- a/gas/testsuite/gas/aarch64/mec.s
+++ b/gas/testsuite/gas/aarch64/mec.s
@@ -18,3 +18,7 @@ msr mecid_a1_el2, x0
 msr vmecid_p_el2, x0
 msr vmecid_a_el2, x0
 msr mecid_rl_a_el3, x0
+
+// MEC data cache operations.
+dc cipae, x0
+dc cigdpae, x0

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 5c434a6c9cfc91c3d9d63ebdf72e5feb15b3d7bf..4f0c71696fa6e064c0dc877c19faf21ab6c61023 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -5222,6 +5222,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
     { "cisw",       CPENS (0, C7, C14, 2), F_HASXT, AARCH64_NO_FEATURES },
     { "cigsw",      CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (MEMTAG) },
     { "cigdsw",     CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (MEMTAG) },
+    { "cipae",      CPENS (4, C7, C14, 0), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_7A) },
+    { "cigdpae",    CPENS (4, C7, C14, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_7A) },
     { "cipapa",     CPENS (6, C7, C14, 1), F_HASXT, AARCH64_NO_FEATURES },
     { "cigdpapa",   CPENS (6, C7, C14, 5), F_HASXT, AARCH64_NO_FEATURES },
     { 0,       CPENS(0,0,0,0), 0, AARCH64_NO_FEATURES }

diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index f9dc5ee975c96c7d37f32d18d11254b1d85361ed..c1b07c710f869a24589f2720705ea85fd5a70969 100644 (file)
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -575,12 +575,12 @@
   SYSREG ("mdscr_el1",         CPENC (2,0,0,2,2),      0,                      AARCH64_NO_FEATURES)
   SYSREG ("mdselr_el1",                CPENC (2,0,0,4,2),      F_ARCHEXT,              AARCH64_FEATURE (DEBUGv8p9))
   SYSREG ("mdstepop_el1",      CPENC (2,0,0,5,2),      F_ARCHEXT,              AARCH64_FEATURE (STEP2))
-  SYSREG ("mecid_a0_el2",      CPENC (3,4,10,8,1),     0,                      AARCH64_NO_FEATURES)
-  SYSREG ("mecid_a1_el2",      CPENC (3,4,10,8,3),     0,                      AARCH64_NO_FEATURES)
-  SYSREG ("mecid_p0_el2",      CPENC (3,4,10,8,0),     0,                      AARCH64_NO_FEATURES)
-  SYSREG ("mecid_p1_el2",      CPENC (3,4,10,8,2),     0,                      AARCH64_NO_FEATURES)
-  SYSREG ("mecid_rl_a_el3",    CPENC (3,6,10,10,1),    0,                      AARCH64_NO_FEATURES)
-  SYSREG ("mecidr_el2",                CPENC (3,4,10,8,7),     F_REG_READ,             AARCH64_NO_FEATURES)
+  SYSREG ("mecid_a0_el2",      CPENC (3,4,10,8,1),     F_ARCHEXT,              AARCH64_FEATURE (V8_7A))
+  SYSREG ("mecid_a1_el2",      CPENC (3,4,10,8,3),     F_ARCHEXT,              AARCH64_FEATURE (V8_7A))
+  SYSREG ("mecid_p0_el2",      CPENC (3,4,10,8,0),     F_ARCHEXT,              AARCH64_FEATURE (V8_7A))
+  SYSREG ("mecid_p1_el2",      CPENC (3,4,10,8,2),     F_ARCHEXT,              AARCH64_FEATURE (V8_7A))
+  SYSREG ("mecid_rl_a_el3",    CPENC (3,6,10,10,1),    F_ARCHEXT,              AARCH64_FEATURE (V8_7A))
+  SYSREG ("mecidr_el2",                CPENC (3,4,10,8,7),     F_REG_READ|F_ARCHEXT,   AARCH64_FEATURE (V8_7A))
   SYSREG ("mfar_el3",          CPENC (3,6,6,0,5),      0,                      AARCH64_NO_FEATURES)
   SYSREG ("midr_el1",          CPENC (3,0,0,0,0),      F_REG_READ,             AARCH64_NO_FEATURES)
   SYSREG ("mpam0_el1",         CPENC (3,0,10,5,1),     0,                      AARCH64_NO_FEATURES)
@@ -1233,8 +1233,8 @@
   SYSREG ("vbar_el3",          CPENC (3,6,12,0,0),     0,                      AARCH64_NO_FEATURES)
   SYSREG ("vdisr_el2",         CPENC (3,4,12,1,1),     F_ARCHEXT,              AARCH64_FEATURE (RAS))
   SYSREG ("vdisr_el3",         CPENC (3,6,12,1,1),     F_ARCHEXT,              AARCH64_FEATURE (E3DSE))
-  SYSREG ("vmecid_a_el2",      CPENC (3,4,10,9,1),     0,                      AARCH64_NO_FEATURES)
-  SYSREG ("vmecid_p_el2",      CPENC (3,4,10,9,0),     0,                      AARCH64_NO_FEATURES)
+  SYSREG ("vmecid_a_el2",      CPENC (3,4,10,9,1),     F_ARCHEXT,              AARCH64_FEATURE (V8_7A))
+  SYSREG ("vmecid_p_el2",      CPENC (3,4,10,9,0),     F_ARCHEXT,              AARCH64_FEATURE (V8_7A))
   SYSREG ("vmpidr_el2",                CPENC (3,4,0,0,5),      0,                      AARCH64_NO_FEATURES)
   SYSREG ("vncr_el2",          CPENC (3,4,2,2,0),      F_ARCHEXT,              AARCH64_FEATURE (V8_4A))
   SYSREG ("vpidr_el2",         CPENC (3,4,0,0,0),      0,                      AARCH64_NO_FEATURES)