drm/i915/dmc: Shuffle code around

Shuffle the DMC_EVT_CTL related stuff around once more. We'll need
this stuff during intel_dmc_enable_pipe(), and this lets us avoid
forward declarations.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-4-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index ef61870b882912b1284dcab3d4d8aa3788215331..cee4e3748b8da17e9ac4230318dfa17763e4ea74 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -506,42 +506,6 @@ static u32 pipedmc_interrupt_mask(struct intel_display *display)
                PIPEDMC_ATS_FAULT;
 }
 
-void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe)
-{
-       enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
-
-       if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
-               return;
-
-       if (DISPLAY_VER(display) >= 20) {
-               intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
-               intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));
-       }
-
-       if (DISPLAY_VER(display) >= 14)
-               intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
-       else
-               intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
-}
-
-void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe)
-{
-       enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
-
-       if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
-               return;
-
-       if (DISPLAY_VER(display) >= 14)
-               intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
-       else
-               intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
-
-       if (DISPLAY_VER(display) >= 20) {
-               intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);
-               intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
-       }
-}
-
 static u32 dmc_evt_ctl_disable(void)
 {
        return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
@@ -579,6 +543,78 @@ static bool is_event_handler(struct intel_display *display,
                REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id;
 }
 
+static bool disable_dmc_evt(struct intel_display *display,
+                           enum intel_dmc_id dmc_id,
+                           i915_reg_t reg, u32 data)
+{
+       if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))
+               return false;
+
+       /* keep all pipe DMC events disabled by default */
+       if (dmc_id != DMC_FW_MAIN)
+               return true;
+
+       /* also disable the flip queue event on the main DMC on TGL */
+       if (display->platform.tigerlake &&
+           is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data))
+               return true;
+
+       /* also disable the HRR event on the main DMC on TGL/ADLS */
+       if ((display->platform.tigerlake || display->platform.alderlake_s) &&
+           is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg, data))
+               return true;
+
+       return false;
+}
+
+static u32 dmc_mmiodata(struct intel_display *display,
+                       struct intel_dmc *dmc,
+                       enum intel_dmc_id dmc_id, int i)
+{
+       if (disable_dmc_evt(display, dmc_id,
+                           dmc->dmc_info[dmc_id].mmioaddr[i],
+                           dmc->dmc_info[dmc_id].mmiodata[i]))
+               return dmc_evt_ctl_disable();
+       else
+               return dmc->dmc_info[dmc_id].mmiodata[i];
+}
+
+void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe)
+{
+       enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
+
+       if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
+               return;
+
+       if (DISPLAY_VER(display) >= 20) {
+               intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
+               intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));
+       }
+
+       if (DISPLAY_VER(display) >= 14)
+               intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe));
+       else
+               intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
+}
+
+void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe)
+{
+       enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
+
+       if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id))
+               return;
+
+       if (DISPLAY_VER(display) >= 14)
+               intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0);
+       else
+               intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
+
+       if (DISPLAY_VER(display) >= 20) {
+               intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0);
+               intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display));
+       }
+}
+
 static void dmc_configure_event(struct intel_display *display,
                                enum intel_dmc_id dmc_id,
                                unsigned int event_id,
@@ -639,42 +675,6 @@ void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display
        dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable);
 }
 
-static bool disable_dmc_evt(struct intel_display *display,
-                           enum intel_dmc_id dmc_id,
-                           i915_reg_t reg, u32 data)
-{
-       if (!is_dmc_evt_ctl_reg(display, dmc_id, reg))
-               return false;
-
-       /* keep all pipe DMC events disabled by default */
-       if (dmc_id != DMC_FW_MAIN)
-               return true;
-
-       /* also disable the flip queue event on the main DMC on TGL */
-       if (display->platform.tigerlake &&
-           is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data))
-               return true;
-
-       /* also disable the HRR event on the main DMC on TGL/ADLS */
-       if ((display->platform.tigerlake || display->platform.alderlake_s) &&
-           is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg, data))
-               return true;
-
-       return false;
-}
-
-static u32 dmc_mmiodata(struct intel_display *display,
-                       struct intel_dmc *dmc,
-                       enum intel_dmc_id dmc_id, int i)
-{
-       if (disable_dmc_evt(display, dmc_id,
-                           dmc->dmc_info[dmc_id].mmioaddr[i],
-                           dmc->dmc_info[dmc_id].mmiodata[i]))
-               return dmc_evt_ctl_disable();
-       else
-               return dmc->dmc_info[dmc_id].mmiodata[i];
-}
-
 /**
  * intel_dmc_load_program() - write the firmware from memory to register.
  * @display: display instance