[PR target/67591] ARM v8 Thumb IT blocks are deprecated

2017-09-15  Christophe Lyon  <christophe.lyon@linaro.org>

	PR target/67591
	* config/arm/arm.md (*cmp_and): Add enabled_for_depr_it attribute.
	(*cmp_ior): Likewise.
	(*ior_scc_scc): Add alternative for enabled_for_depr_it attribute.
	(*ior_scc_scc_cmp): Likewise.
	(*and_scc_scc): Likewise.
	(*and_scc_scc_cmp): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@252817 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fa5f73476243b122dc4ea450e20627fa874268e2..47913475d5acee7a51ec8190b1727fcd97311bd1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2017-09-15  Christophe Lyon  <christophe.lyon@linaro.org>
+
+       PR target/67591
+       * config/arm/arm.md (*cmp_and): Add enabled_for_depr_it attribute.
+       (*cmp_ior): Likewise.
+       (*ior_scc_scc): Add alternative for enabled_for_depr_it attribute.
+       (*ior_scc_scc_cmp): Likewise.
+       (*and_scc_scc): Likewise.
+       (*and_scc_scc_cmp): Likewise.
+
 2017-09-15  Richard Sandiford  <richard.sandiford@linaro.org>
            Alan Hayard  <alan.hayward@arm.com>
            David Sherwood  <david.sherwood@arm.com>

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 6c4e361913cf2d5f22d038b753ba128a8f8f1b8c..f241f9d0b7d24bd3414960c79420ab5e03a247f5 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -9563,6 +9563,7 @@
   [(set_attr "conds" "set")
    (set_attr "predicable" "no")
    (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
+   (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no")
    (set_attr_alternative "length"
       [(const_int 6)
        (const_int 8)
@@ -9645,6 +9646,7 @@
   "
   [(set_attr "conds" "set")
    (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
+   (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no")
    (set_attr_alternative "length"
       [(const_int 6)
        (const_int 8)
@@ -9667,13 +9669,13 @@
 )
 
 (define_insn_and_split "*ior_scc_scc"
-  [(set (match_operand:SI 0 "s_register_operand" "=Ts")
+  [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
        (ior:SI (match_operator:SI 3 "arm_comparison_operator"
-                [(match_operand:SI 1 "s_register_operand" "r")
-                 (match_operand:SI 2 "arm_add_operand" "rIL")])
+                [(match_operand:SI 1 "s_register_operand" "l,r")
+                 (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
                (match_operator:SI 6 "arm_comparison_operator"
-                [(match_operand:SI 4 "s_register_operand" "r")
-                 (match_operand:SI 5 "arm_add_operand" "rIL")])))
+                [(match_operand:SI 4 "s_register_operand" "l,r")
+                 (match_operand:SI 5 "arm_add_operand" "lPy,rIL")])))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_32BIT
    && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y)
@@ -9692,6 +9694,7 @@
                                                  DOM_CC_X_OR_Y),
                    CC_REGNUM);"
   [(set_attr "conds" "clob")
+   (set_attr "enabled_for_depr_it" "yes,no")
    (set_attr "length" "16")
    (set_attr "type" "multiple")]
 )
@@ -9701,13 +9704,13 @@
 (define_insn_and_split "*ior_scc_scc_cmp"
   [(set (match_operand 0 "dominant_cc_register" "")
        (compare (ior:SI (match_operator:SI 3 "arm_comparison_operator"
-                         [(match_operand:SI 1 "s_register_operand" "r")
-                          (match_operand:SI 2 "arm_add_operand" "rIL")])
+                         [(match_operand:SI 1 "s_register_operand" "l,r")
+                          (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
                         (match_operator:SI 6 "arm_comparison_operator"
-                         [(match_operand:SI 4 "s_register_operand" "r")
-                          (match_operand:SI 5 "arm_add_operand" "rIL")]))
+                         [(match_operand:SI 4 "s_register_operand" "l,r")
+                          (match_operand:SI 5 "arm_add_operand" "lPy,rIL")]))
                 (const_int 0)))
-   (set (match_operand:SI 7 "s_register_operand" "=Ts")
+   (set (match_operand:SI 7 "s_register_operand" "=Ts,Ts")
        (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
                (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
   "TARGET_32BIT"
@@ -9722,18 +9725,19 @@
    (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
   ""
   [(set_attr "conds" "set")
+   (set_attr "enabled_for_depr_it" "yes,no")
    (set_attr "length" "16")
    (set_attr "type" "multiple")]
 )
 
 (define_insn_and_split "*and_scc_scc"
-  [(set (match_operand:SI 0 "s_register_operand" "=Ts")
+  [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
        (and:SI (match_operator:SI 3 "arm_comparison_operator"
-                [(match_operand:SI 1 "s_register_operand" "r")
-                 (match_operand:SI 2 "arm_add_operand" "rIL")])
+                [(match_operand:SI 1 "s_register_operand" "l,r")
+                 (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
                (match_operator:SI 6 "arm_comparison_operator"
-                [(match_operand:SI 4 "s_register_operand" "r")
-                 (match_operand:SI 5 "arm_add_operand" "rIL")])))
+                [(match_operand:SI 4 "s_register_operand" "l,r")
+                 (match_operand:SI 5 "arm_add_operand" "lPy,rIL")])))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_32BIT
    && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
@@ -9754,6 +9758,7 @@
                                                  DOM_CC_X_AND_Y),
                    CC_REGNUM);"
   [(set_attr "conds" "clob")
+   (set_attr "enabled_for_depr_it" "yes,no")
    (set_attr "length" "16")
    (set_attr "type" "multiple")]
 )
@@ -9763,13 +9768,13 @@
 (define_insn_and_split "*and_scc_scc_cmp"
   [(set (match_operand 0 "dominant_cc_register" "")
        (compare (and:SI (match_operator:SI 3 "arm_comparison_operator"
-                         [(match_operand:SI 1 "s_register_operand" "r")
-                          (match_operand:SI 2 "arm_add_operand" "rIL")])
+                         [(match_operand:SI 1 "s_register_operand" "l,r")
+                          (match_operand:SI 2 "arm_add_operand" "lPy,rIL")])
                         (match_operator:SI 6 "arm_comparison_operator"
-                         [(match_operand:SI 4 "s_register_operand" "r")
-                          (match_operand:SI 5 "arm_add_operand" "rIL")]))
+                         [(match_operand:SI 4 "s_register_operand" "l,r")
+                          (match_operand:SI 5 "arm_add_operand" "lPy,rIL")]))
                 (const_int 0)))
-   (set (match_operand:SI 7 "s_register_operand" "=Ts")
+   (set (match_operand:SI 7 "s_register_operand" "=Ts,Ts")
        (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
                (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
   "TARGET_32BIT"
@@ -9784,6 +9789,7 @@
    (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))]
   ""
   [(set_attr "conds" "set")
+   (set_attr "enabled_for_depr_it" "yes,no")
    (set_attr "length" "16")
    (set_attr "type" "multiple")]
 )