arm.md (ior_xor): New code iterator.

	* arm.md (ior_xor): New code iterator.
	(split for ior/xor with shift and zero-extend): New split pattern.
	* arm/predicates.md (subreg_lowpart_operator): New special predicate.

From-SVN: r149673

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e3f5d0c1e44486c1b31e60fcd721d72a7073ebb7..8ae44d8bdb6cc33641ba0e2b154116315d3b5a5a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2009-07-15  Richard Earnshaw  <rearnsha@arm.com>
+
+       * arm.md (ior_xor): New code iterator.
+       (split for ior/xor with shift and zero-extend): New split pattern.
+       * arm/predicates.md (subreg_lowpart_operator): New special predicate.
+
 2009-07-15  Richard Guenther  <rguenther@suse.de>
 
        * tree-ssa-structalias.c (make_constraint_from_heapvar): Initialize

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 0fd0a1982eac8700a73c1ad9c40b7cb4cfb37633..809f2c49b97e1e205548aac74a79abf120e5ee4d 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4207,6 +4207,28 @@
   ""
 )
 
+(define_code_iterator ior_xor [ior xor])
+
+(define_split
+  [(set (match_operand:SI 0 "s_register_operand" "")
+       (ior_xor:SI (and:SI (ashift:SI
+                            (match_operand:SI 1 "s_register_operand" "")
+                            (match_operand:SI 2 "const_int_operand" ""))
+                           (match_operand:SI 3 "const_int_operand" ""))
+                   (zero_extend:SI
+                    (match_operator 5 "subreg_lowpart_operator"
+                     [(match_operand:SI 4 "s_register_operand" "")]))))]
+  "TARGET_32BIT
+   && (INTVAL (operands[3])
+       == (GET_MODE_MASK (GET_MODE (operands[5]))
+           & (GET_MODE_MASK (GET_MODE (operands[5]))
+             << (INTVAL (operands[2])))))"
+  [(set (match_dup 0) (ior_xor:SI (ashift:SI (match_dup 1) (match_dup 2))
+                                 (match_dup 4)))
+   (set (match_dup 0) (zero_extend:SI (match_dup 5)))]
+  "operands[5] = gen_lowpart (GET_MODE (operands[5]), operands[0]);"
+)
+
 (define_insn "*compareqi_eq0"
   [(set (reg:CC_Z CC_REGNUM)
        (compare:CC_Z (match_operand:QI 0 "s_register_operand" "r")

diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 7997cc94cf5ec311ef7560f531ca3e7be42f945a..d351f443851defd929b60fcd8024fb3b96a774c6 100644 (file)
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -73,6 +73,10 @@
              || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
 })
 
+(define_special_predicate "subreg_lowpart_operator"
+  (and (match_code "subreg")
+       (match_test "subreg_lowpart_p (op)")))
+
 ;; Reg, subreg(reg) or const_int.
 (define_predicate "reg_or_int_operand"
   (ior (match_code "const_int")