Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 5 +++++
- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 10 +++++++++
- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 10 +++++++++
- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 ++++++++--
- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++++++
- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 27 ++-----------------------
+ drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 5 +++++
+ drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 10 ++++++++++
+ drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 10 ++++++++++
+ drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +++++++++--
+ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++++++
+ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 27 ++-------------------------
6 files changed, 43 insertions(+), 27 deletions(-)
-diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
-index 1f83bc18d5008..80f3b1da9fc26 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
-@@ -164,6 +164,11 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
+@@ -164,6 +164,11 @@ static int a2xx_hw_init(struct msm_gpu *
if (ret)
return ret;
/* NOTE: PM4/micro-engine firmware registers look to be the same
* for a2xx and a3xx.. we could possibly push that part down to
* adreno_gpu base class. Or push both PM4 and PFP but
-diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
-index 5f7e98028eaf4..eeba2deeca1e8 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
-@@ -215,6 +215,16 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
+@@ -215,6 +215,16 @@ static int a3xx_hw_init(struct msm_gpu *
if (ret)
return ret;
/* setup access protection: */
gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);
-diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
-index ab2b752566d81..05cfa81d4c540 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
-@@ -265,6 +265,16 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
+@@ -265,6 +265,16 @@ static int a4xx_hw_init(struct msm_gpu *
if (ret)
return ret;
/* Load PM4: */
ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data);
len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4;
-diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
-index 4a484b06319ff..24b55103bfe00 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
-@@ -677,14 +677,21 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
+@@ -677,14 +677,21 @@ static int a5xx_hw_init(struct msm_gpu *
if (ret)
return ret;
/* Disable the interrupts through the initial bringup stage */
gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK);
-diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
-index ea073cd9d248e..dae32c6ac2120 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
-@@ -550,6 +550,13 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
+@@ -549,6 +549,13 @@ static int a6xx_hw_init(struct msm_gpu *
if (ret)
goto out;
/* Always come up on rb 0 */
a6xx_gpu->cur_ring = gpu->rb[0];
-diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
-index 053da39da1cc0..3802ad38c519c 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -354,26 +354,6 @@ int adreno_hw_init(struct msm_gpu *gpu)
}
struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
---
-2.25.1
-
+++ /dev/null
-From 161a7be6455794c1be2abce4bffc297ae31b7a0d Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 3 Sep 2020 20:03:11 -0600
-Subject: drm/msm: Enable expanded apriv support for a650
-
-From: Jordan Crouse <jcrouse@codeaurora.org>
-
-[ Upstream commit 604234f33658cdd72f686be405a99646b397d0b3 ]
-
-a650 supports expanded apriv support that allows us to map critical buffers
-(ringbuffer and memstore) as as privileged to protect them from corruption.
-
-Cc: stable@vger.kernel.org
-Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
-Signed-off-by: Rob Clark <robdclark@chromium.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++-
- drivers/gpu/drm/msm/msm_gpu.c | 2 +-
- drivers/gpu/drm/msm/msm_gpu.h | 11 +++++++++++
- drivers/gpu/drm/msm/msm_ringbuffer.c | 4 ++--
- 4 files changed, 19 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
-index c3a81594f4fb7..ea073cd9d248e 100644
---- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
-+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
-@@ -533,7 +533,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
- A6XX_PROTECT_RDONLY(0x980, 0x4));
- gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
-
-- if (adreno_is_a650(adreno_gpu)) {
-+ /* Enable expanded apriv for targets that support it */
-+ if (gpu->hw_apriv) {
- gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
- (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
- }
-@@ -908,6 +909,9 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
- adreno_gpu->registers = NULL;
- adreno_gpu->reg_offsets = a6xx_register_offsets;
-
-+ if (adreno_is_a650(adreno_gpu))
-+ adreno_gpu->base.hw_apriv = true;
-+
- ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
- if (ret) {
- a6xx_destroy(&(a6xx_gpu->base.base));
-diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
-index edd45f434ccd6..8653a2f7ae1c9 100644
---- a/drivers/gpu/drm/msm/msm_gpu.c
-+++ b/drivers/gpu/drm/msm/msm_gpu.c
-@@ -932,7 +932,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
-
- memptrs = msm_gem_kernel_new(drm,
- sizeof(struct msm_rbmemptrs) * nr_rings,
-- MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,
-+ check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo,
- &memptrs_iova);
-
- if (IS_ERR(memptrs)) {
-diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
-index ab8f0f9c9dc88..15254239e5ec6 100644
---- a/drivers/gpu/drm/msm/msm_gpu.h
-+++ b/drivers/gpu/drm/msm/msm_gpu.h
-@@ -14,6 +14,7 @@
- #include "msm_drv.h"
- #include "msm_fence.h"
- #include "msm_ringbuffer.h"
-+#include "msm_gem.h"
-
- struct msm_gem_submit;
- struct msm_gpu_perfcntr;
-@@ -131,6 +132,8 @@ struct msm_gpu {
- } devfreq;
-
- struct msm_gpu_state *crashstate;
-+ /* True if the hardware supports expanded apriv (a650 and newer) */
-+ bool hw_apriv;
- };
-
- /* It turns out that all targets use the same ringbuffer size */
-@@ -319,4 +322,12 @@ static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
- mutex_unlock(&gpu->dev->struct_mutex);
- }
-
-+/*
-+ * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
-+ * support expanded privileges
-+ */
-+#define check_apriv(gpu, flags) \
-+ (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
-+
-+
- #endif /* __MSM_GPU_H__ */
-diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c
-index 39ecb5a18431e..935bf9b1d9418 100644
---- a/drivers/gpu/drm/msm/msm_ringbuffer.c
-+++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
-@@ -27,8 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
- ring->id = id;
-
- ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
-- MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &ring->bo,
-- &ring->iova);
-+ check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY),
-+ gpu->aspace, &ring->bo, &ring->iova);
-
- if (IS_ERR(ring->start)) {
- ret = PTR_ERR(ring->start);
---
-2.25.1
-
+++ /dev/null
-From 34221545d2069dc947131f42392fd4cebabe1b39 Mon Sep 17 00:00:00 2001
-From: Jordan Crouse <jcrouse@codeaurora.org>
-Date: Thu, 3 Sep 2020 20:03:10 -0600
-Subject: drm/msm: Split the a5xx preemption record
-
-From: Jordan Crouse <jcrouse@codeaurora.org>
-
-commit 34221545d2069dc947131f42392fd4cebabe1b39 upstream.
-
-The main a5xx preemption record can be marked as privileged to
-protect it from user access but the counters storage needs to be
-remain unprivileged. Split the buffers and mark the critical memory
-as privileged.
-
-Cc: stable@vger.kernel.org
-Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
-Signed-off-by: Rob Clark <robdclark@chromium.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
----
- drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 1 +
- drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 25 ++++++++++++++++++++-----
- 2 files changed, 21 insertions(+), 5 deletions(-)
-
---- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
-+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
-@@ -31,6 +31,7 @@ struct a5xx_gpu {
- struct msm_ringbuffer *next_ring;
-
- struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS];
-+ struct drm_gem_object *preempt_counters_bo[MSM_GPU_MAX_RINGS];
- struct a5xx_preempt_record *preempt[MSM_GPU_MAX_RINGS];
- uint64_t preempt_iova[MSM_GPU_MAX_RINGS];
-
---- a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c
-+++ b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c
-@@ -226,19 +226,31 @@ static int preempt_init_ring(struct a5xx
- struct adreno_gpu *adreno_gpu = &a5xx_gpu->base;
- struct msm_gpu *gpu = &adreno_gpu->base;
- struct a5xx_preempt_record *ptr;
-- struct drm_gem_object *bo = NULL;
-- u64 iova = 0;
-+ void *counters;
-+ struct drm_gem_object *bo = NULL, *counters_bo = NULL;
-+ u64 iova = 0, counters_iova = 0;
-
- ptr = msm_gem_kernel_new(gpu->dev,
- A5XX_PREEMPT_RECORD_SIZE + A5XX_PREEMPT_COUNTER_SIZE,
-- MSM_BO_UNCACHED, gpu->aspace, &bo, &iova);
-+ MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);
-
- if (IS_ERR(ptr))
- return PTR_ERR(ptr);
-
-+ /* The buffer to store counters needs to be unprivileged */
-+ counters = msm_gem_kernel_new(gpu->dev,
-+ A5XX_PREEMPT_COUNTER_SIZE,
-+ MSM_BO_UNCACHED, gpu->aspace, &counters_bo, &counters_iova);
-+ if (IS_ERR(counters)) {
-+ msm_gem_kernel_put(bo, gpu->aspace, true);
-+ return PTR_ERR(counters);
-+ }
-+
- msm_gem_object_set_name(bo, "preempt");
-+ msm_gem_object_set_name(counters_bo, "preempt_counters");
-
- a5xx_gpu->preempt_bo[ring->id] = bo;
-+ a5xx_gpu->preempt_counters_bo[ring->id] = counters_bo;
- a5xx_gpu->preempt_iova[ring->id] = iova;
- a5xx_gpu->preempt[ring->id] = ptr;
-
-@@ -249,7 +261,7 @@ static int preempt_init_ring(struct a5xx
- ptr->data = 0;
- ptr->cntl = MSM_GPU_RB_CNTL_DEFAULT;
- ptr->rptr_addr = rbmemptr(ring, rptr);
-- ptr->counter = iova + A5XX_PREEMPT_RECORD_SIZE;
-+ ptr->counter = counters_iova;
-
- return 0;
- }
-@@ -260,8 +272,11 @@ void a5xx_preempt_fini(struct msm_gpu *g
- struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
- int i;
-
-- for (i = 0; i < gpu->nr_rings; i++)
-+ for (i = 0; i < gpu->nr_rings; i++) {
- msm_gem_kernel_put(a5xx_gpu->preempt_bo[i], gpu->aspace, true);
-+ msm_gem_kernel_put(a5xx_gpu->preempt_counters_bo[i],
-+ gpu->aspace, true);
-+ }
- }
-
- void a5xx_preempt_init(struct msm_gpu *gpu)
scsi-target-iscsi-fix-hang-in-iscsit_access_np-when-getting-tpg-np_login_sem.patch
drm-i915-gvt-do-not-check-len-max_len-for-lri.patch
drm-tve200-stabilize-enable-disable.patch
-drm-msm-split-the-a5xx-preemption-record.patch
drm-msm-disable-preemption-on-all-5xx-targets.patch
mmc-sdio-use-mmc_pre_req-mmc_post_req.patch
mmc-sdhci-of-esdhc-don-t-walk-device-tree-on-every-interrupt.patch
usb-typec-ucsi-acpi-check-the-_dep-dependencies.patch
drm-msm-gpu-make-ringbuffer-readonly.patch
drm-msm-a6xx-update-a6xx_hw_init-for-a640-and-a650.patch
-drm-msm-enable-expanded-apriv-support-for-a650.patch
drm-msm-disable-the-rptr-shadow.patch
+++ /dev/null
-From 215f0aaf021bdbf9dc426fc1209555f287e9017d Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 3 Sep 2020 20:03:11 -0600
-Subject: drm/msm: Enable expanded apriv support for a650
-
-From: Jordan Crouse <jcrouse@codeaurora.org>
-
-[ Upstream commit 604234f33658cdd72f686be405a99646b397d0b3 ]
-
-a650 supports expanded apriv support that allows us to map critical buffers
-(ringbuffer and memstore) as as privileged to protect them from corruption.
-
-Cc: stable@vger.kernel.org
-Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
-Signed-off-by: Rob Clark <robdclark@chromium.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++-
- drivers/gpu/drm/msm/msm_gpu.c | 2 +-
- drivers/gpu/drm/msm/msm_gpu.h | 11 +++++++++++
- drivers/gpu/drm/msm/msm_ringbuffer.c | 4 ++--
- 4 files changed, 19 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
-index b7dc350d96fc8..ee99cdeb449ca 100644
---- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
-+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
-@@ -541,7 +541,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
- A6XX_PROTECT_RDONLY(0x980, 0x4));
- gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
-
-- if (adreno_is_a650(adreno_gpu)) {
-+ /* Enable expanded apriv for targets that support it */
-+ if (gpu->hw_apriv) {
- gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
- (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
- }
-@@ -926,6 +927,9 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
- adreno_gpu->registers = NULL;
- adreno_gpu->reg_offsets = a6xx_register_offsets;
-
-+ if (adreno_is_a650(adreno_gpu))
-+ adreno_gpu->base.hw_apriv = true;
-+
- ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
- if (ret) {
- a6xx_destroy(&(a6xx_gpu->base.base));
-diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
-index a22d306223068..9b839d6f4692a 100644
---- a/drivers/gpu/drm/msm/msm_gpu.c
-+++ b/drivers/gpu/drm/msm/msm_gpu.c
-@@ -905,7 +905,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
-
- memptrs = msm_gem_kernel_new(drm,
- sizeof(struct msm_rbmemptrs) * nr_rings,
-- MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,
-+ check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo,
- &memptrs_iova);
-
- if (IS_ERR(memptrs)) {
-diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
-index 429cb40f79315..f22e0f67ba40e 100644
---- a/drivers/gpu/drm/msm/msm_gpu.h
-+++ b/drivers/gpu/drm/msm/msm_gpu.h
-@@ -14,6 +14,7 @@
- #include "msm_drv.h"
- #include "msm_fence.h"
- #include "msm_ringbuffer.h"
-+#include "msm_gem.h"
-
- struct msm_gem_submit;
- struct msm_gpu_perfcntr;
-@@ -138,6 +139,8 @@ struct msm_gpu {
- } devfreq;
-
- struct msm_gpu_state *crashstate;
-+ /* True if the hardware supports expanded apriv (a650 and newer) */
-+ bool hw_apriv;
- };
-
- /* It turns out that all targets use the same ringbuffer size */
-@@ -326,4 +329,12 @@ static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
- mutex_unlock(&gpu->dev->struct_mutex);
- }
-
-+/*
-+ * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
-+ * support expanded privileges
-+ */
-+#define check_apriv(gpu, flags) \
-+ (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
-+
-+
- #endif /* __MSM_GPU_H__ */
-diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c
-index 39ecb5a18431e..935bf9b1d9418 100644
---- a/drivers/gpu/drm/msm/msm_ringbuffer.c
-+++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
-@@ -27,8 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
- ring->id = id;
-
- ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
-- MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &ring->bo,
-- &ring->iova);
-+ check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY),
-+ gpu->aspace, &ring->bo, &ring->iova);
-
- if (IS_ERR(ring->start)) {
- ret = PTR_ERR(ring->start);
---
-2.25.1
-
usb-typec-intel_pmc_mux-do-not-configure-altmode-hpd-high.patch
usb-typec-intel_pmc_mux-do-not-configure-sbu-and-hsl-orientation-in-alternate-modes.patch
drm-msm-gpu-make-ringbuffer-readonly.patch
-drm-msm-enable-expanded-apriv-support-for-a650.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
