riscv: dts: thead: add zfh for th1520

th1520 support Zfh ISA extension.
It supports the same RISC-V extensions as SG2042.

commit cb074bed1186 ("riscv: dts: sophgo: add zfh for sg2042")

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 8e50e24040c2b59a9a2d0a8a4d62a55e622b026c..dfc868e5b19aad943f00c45132afb03f1551b932 100644 (file)
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -26,7 +26,7 @@
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
                                               "ziccrse", "zicntr", "zicsr",
-                                              "zifencei", "zihpm",
+                                              "zifencei", "zihpm", "zfh",
                                               "xtheadvector";
                        thead,vlenb = <16>;
                        reg = <0>;
@@ -53,7 +53,7 @@
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
                                               "ziccrse", "zicntr", "zicsr",
-                                              "zifencei", "zihpm",
+                                              "zifencei", "zihpm", "zfh",
                                               "xtheadvector";
                        thead,vlenb = <16>;
                        reg = <1>;
@@ -80,7 +80,7 @@
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
                                               "ziccrse", "zicntr", "zicsr",
-                                              "zifencei", "zihpm",
+                                              "zifencei", "zihpm", "zfh",
                                               "xtheadvector";
                        thead,vlenb = <16>;
                        reg = <2>;
@@ -107,7 +107,7 @@
                        riscv,isa-base = "rv64i";
                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
                                               "ziccrse", "zicntr", "zicsr",
-                                              "zifencei", "zihpm",
+                                              "zifencei", "zihpm", "zfh",
                                               "xtheadvector";
                        thead,vlenb = <16>;
                        reg = <3>;